Abstract: A semiconductor device includes: a drain electrode including a plurality of drain finger parts; a source electrode including a plurality of source finger parts and a Kelvin source part electrically connected with the source finger parts; a sense electrode positioned between a drain finger part and the Kelvin source part, which are next to each other in a particular direction; and a gate electrode positioned between a drain finger part and a source finger part, which are next to each other in the particular direction, and between a drain finger part and the sense electrode, which are next to each other in the particular direction. The sense electrode and the Kelvin source part are electrically connected via a sense resistance due to a spacing between the sense electrode and the Kelvin source part in the particular direction.

Abstract: An improved high electron mobility transistor (HEMT) structure includes a substrate, a nitride nucleation layer, a nitride buffer layer, a nitride channel layer, and a barrier layer. The nitride buffer layer includes a metal dopant. The nitride channel layer has a metal doping concentration less than that of the nitride buffer layer. A two-dimensional electron gas is formed in the nitride channel layer along an interface between the nitride channel layer and the barrier layer. A metal doping concentration X at an interface between the nitride buffer layer and the nitride channel layer is defined as the number of metal atoms per cubic centimeter, and a thickness Y of the nitride channel later is in microns (?m) and satisfies Y?(0.2171)ln(X)?8.34, thereby reducing an influence of the metal dopant to a sheet resistance value of the nitride channel layer and providing the improved HEMT structure having a better performance.

Abstract: An improved high electron mobility transistor (HEMT) structure includes in order a substrate, a nucleation layer, a buffer layer, a channel layer, and a barrier layer, wherein the buffer layer includes a dopant. The channel layer having a dopant doping concentration less than that of the buffer layer. A two-dimension electron gas is formed in the channel layer along an interface between the channel layer and the barrier layer. A dopant doping concentration of the channel layer at an interface between the channel layer and the barrier layer is equal to or greater than 1×1015 cm?3.

Abstract: A method of manufacturing a silicon carbide semiconductor device includes a step of forming gate trench, a step of forming Schottky trench, a step of forming a silicon oxide film in the gate trench and the Schottky trench, a step of forming a polycrystalline silicon film inside the silicon oxide film, a step of etching back the polycrystalline silicon film, a step of forming an interlayer insulating film on a gate electrode in the gate trench, a step of removing, by wet etching, the polycrystalline silicon film in the Schottky trench after opening a hole in the interlayer insulating film, a step of forming an ohmic electrode on a source region, a step of removing the silicon oxide film in the Schottky trench, and a step of forming a source electrode in the Schottky trench, which is in Schottky junction with a drift layer.

Abstract: A semiconductor device includes a semiconductor part, first to third electrodes, a control electrode and first to third insulating films. The semiconductor part is provided between the first and second electrodes. The third electrode extends in a first direction inside a trench of the semiconductor part. The control electrode is provided inside the trench at an opening side thereof. The control electrode includes first and second control portions arranged in a second direction crossing the first direction. The third electrode has an end portion between the first and second control portions. The first insulating film is provided between the semiconductor part and the third electrode. The second insulating film is provided between the semiconductor part and the control electrode. The third insulating film covers the end portion of the third electrode. The first insulating film includes an extending portion extending between the third insulating film and the control electrode.

Abstract: A semiconductor device includes an insulating layer, a semiconductor layer on the insulating layer, and a control electrode on the semiconductor layer. The semiconductor layer includes first and second semiconductor parts and a separation trench between the first and second semiconductor parts. The first and second semiconductor parts extending along the insulating film. The first semiconductor part includes first and second regions of a first conductivity type, and a fifth region of a second conductivity type between the first and second regions. The second semiconductor part includes third and fourth regions of the second conductivity type, and a sixth region of the second conductivity type between the third and fourth regions. The control electrode extends over the fifth and sixth regions. The semiconductor layer further including a seventh region of the second conductivity type at a bottom of the separation trench and electrically connecting the fifth and sixth regions.

Abstract: A semiconductor substrate has a first surface, a second surface opposing the first surface, and a trench extending from the second surface toward the first surface. A gate electrode is arranged in the trench and has a lower end located at a bottom of the trench and an upper end opposing the lower end. The upper end is located in a first surface side with respect to the second surface. An n-type source region has a first region having a first concentration, and a second region having a second concentration higher than the first concentration. The first region has a portion located in the first surface side with respect to an upper end of the gate electrode. The second region is located in the second surface side with respect to the upper end of the gate electrode.

Abstract: A semiconductor device includes: a semiconductor layer in a rectangular shape in a plan view; a transistor provided in a first region; and a drain lead-out region provided in a second region. A border line is a straight line parallel to longer sides of the semiconductor layer. The first region includes a plurality of source pads and gate pads. The second region includes a plurality of drain pads. One gate pad among the gate pads is disposed to dispose none of the plurality of source pads between (i) the one gate pad and (ii) one longer side and one shorter side. One drain pad among the plurality of drain pads is in the same shape as the one gate pad and is disposed close to a second vertex. The plurality of source pads include a source pad that is in a rectangular shape or an obround shape having a longitudinal direction parallel to the longer sides of the semiconductor layer.

Abstract: A performance of a semiconductor device including a main MOSFET and a sensing MOSFET having a double-gate structure including a gate electrode and a field plate electrode inside a trench is improved. A main MOSFET including a gate electrode and a field plate electrode inside a second trench and a sensing MOSFET for electric-current detection including a gate electrode and a field plate electrode inside a fourth trench are surrounded by different termination rings, respectively.

Abstract: According to various embodiments, there is provided a MOSFET device. The MOSFET device may include a substrate; a first doped region disposed in the substrate; a second doped region disposed in the substrate, wherein the first doped region and the second doped region are laterally adjacent to each other; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a gate disposed on the substrate, over the first and second doped regions, and between the third and fourth doped regions; and at least one high resistance region embedded in at least the second doped region, wherein the first doped region has a first conductivity type, wherein the second doped region, the third doped region, and the fourth doped region have a second conductivity type, wherein the first conductivity type and the second conductivity type are different.

Abstract: Integrated circuit devices including a fin shaped active region and methods of forming the same are provided. The devices may include a fin shaped active region, a plurality of semiconductor patterns on the fin shaped active region, a gate electrode on the plurality of semiconductor patterns, and source/drain regions on opposing sides of the gate electrode, respectively. The gate electrode may include a main gate portion extending on an uppermost semiconductor pattern and a sub-gate portion extending between two adjacent ones of the plurality of semiconductor patterns. The sub-gate portion may include a sub-gate center portion and sub-gate edge portions. In a horizontal cross-sectional view, a first width of the sub-gate center portion in a first direction may be less than a second width of one of the sub-gate edge portions in the first direction.

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, and an oxide semiconductor layer provided between the first electrode and the second electrode and including a first region, a second region between the first region and the second electrode, and a third region between the first region and the second region. A gate electrode surrounds the third region, and a gate insulating layer is between the gate electrode and the third region. A first resistivity of the first region is higher than a second resistivity of the second region. A first distance between the first electrode and the gate electrode in a first direction from the first electrode toward the second electrode is shorter than a second distance between the gate electrode and the second electrode in the first direction.

Abstract: A transistor device includes a channel region, a first source/drain region adjacent to a first end of the channel region and a second source/drain region adjacent to a second end of the channel region, a gate structure disposed on the channel region, the first source/drain region and the second source/drain region, and an interlayer dielectric (ILD) structure disposed on the gate structure. The ILD structure includes a first dielectric layer including a first set of sublayers. The first set of sublayers includes a first sublayer including a first dielectric material having a first hydrogen concentration and a second sublayer including the first dielectric material having a second hydrogen concentration lower than the first hydrogen concentration. The ILD structure further includes a second dielectric layer including a second set of sublayers. The second set of sublayers includes a third sublayer including a second dielectric material different from the first dielectric material.

Abstract: A diode structure includes a substrate having a first conductivity type, a first well region having a second conductivity type opposite to the first conductivity type and disposed in the substrate, a first doped region having the first conductivity type and disposed in the first well region, a ring-shaped well region having the second conductivity type, disposed in the first well region and surrounding the first doped region, an anode disposed on the first doped region, a second well region having the second conductivity type, separated from the first well region and disposed in the substrate, a second doped region having the second conductivity type and disposed in the second well region, and a cathode disposed on the second doped region.

Abstract: A single chip power diode includes a semiconductor body having an anode region coupled to a first load terminal and a cathode region coupled to a second load terminal. An edge termination region surrounding an active region is terminated by a chip edge. The semiconductor body thickness is defined by a distance between at least one first interface area formed between the first load terminal and the anode region and a second interface area formed between the second load terminal and the cathode region. At least one inactive subregion is included in the active region. Each inactive subregion: has a blocking area with a minimal lateral extension of at least 20% of a drift region thickness; configured to prevent crossing of the load current between the first load terminal and the semiconductor body through the blocking area; and at least partially not arranged adjacent to the edge termination region.

Abstract: Semiconductor structures and manufacturing methods thereof. A semiconductor structure includes: a first epitaxial layer; a bonding layer, on first epitaxial layer and provided with a first through-hole exposing first epitaxial layer; a silicon substrate, on a side of bonding layer away from first epitaxial layer, first epitaxial layer and the silicon substrate being bonded through the bonding layer; a through-silicon-via, in silicon substrate, through-silicon-via communicating with first through-hole; a second epitaxial layer, on first epitaxial layer exposed by first through-hole; a first electrode, on a side of first epitaxial layer away from bonding layer, and electrically coupled with first epitaxial layer; a second electrode, on a side of second epitaxial layer away from first epitaxial layer, and electrically coupled with second epitaxial layer.

Abstract: A semiconductor device includes a semiconductor substrate having a principal surface, a semiconductor layer formed on the principal surface of the semiconductor substrate, the semiconductor layer including a first-conductivity-type low concentration layer in contact with the principal surface of the semiconductor substrate and a first-conductivity-type high concentration layer that is formed at a surface layer portion of a surface, which is on a side opposite to the principal surface, of the semiconductor layer and that has a higher impurity concentration than the low concentration layer, and a Schottky electrode that is formed on the surface of the semiconductor layer and that forms a Schottky junction portion between the high concentration layer and the Schottky electrode.

Abstract: Provided is a semiconductor element including at least, a semiconductor layer including a crystalline oxide semiconductor as a major component; an electrode layer laminated on the semiconductor layer; and a conductive substrate laminated on the electrode layer directly or with another layer in between, the conductive substrate containing at least a first metal selected from the metals in group 11 in the periodic table and a second metal different from the first metal in coefficient of liner thermal expansion.

Abstract: A semiconductor product, including: a base region doped with a first conductivity type; a plurality of stripe regions doped with a second conductivity type, provided on an upper surface of the base region, and the second conductivity type is different from the first conductivity type; a plurality of cell regions doped with the second conductivity type, provided on the upper surface of the base region; and a metal layer arranged on the upper surface of the base region, so that the metal layer defines a Schottky barrier with the base region and covers the plurality of stripe regions and the plurality of cell regions; and each cell region of a majority of the plurality of cell regions contacts at least one neighboring stripe region of the plurality of stripe regions and the stripe regions and the cell regions extend into the base region to different depths.

Abstract: An electron extraction type free-wheeling diode device and a preparation method thereof are provided by the present disclosure, and more than one first structures for increasing the density of electron extraction pathways are provided on a N-type drift region. Each of the first structures includes a lightly doped P-type base region, a heavily doped N-type emitter region located on the lightly doped P-type base region, a P-type trench anode region, and a trench region located on the P-type trench anode region. The barrier height of the punch-through NPN triode can be tuned in a wide range, which has beneficial effects on soft and fast adjustment of the reverse recovery process.

Abstract: A cross-coupled tunnel diode (XTD) device with large peak-to-valley current ratio (PVCR) is disclosed. A memory cell circuit comprising XTD devices is also disclosed. The XTD device includes an N-type semiconductor coupled to a P-type semiconductor. A first gate is disposed on the N-type semiconductor and a second gate is disposed on the P-type semiconductor. The first gate is coupled to the output terminal, which is further coupled to the P-type semiconductor. The second gate is coupled to the input terminal, which is coupled to the N-type semiconductor. As reverse bias voltage increases, band-to-band tunneling from valence band to conduction band initially generates increasing current, but the rising bias voltage closes the band to band tunneling window, creating a gated negative differential resistance behavior. The current drops off as the bias voltage further increases. In some examples, a ratio of peak-to-valley current ratio may exceed 103 or 105.

Abstract: The present disclosure provides a resonant tunneling diode and a manufacturing method thereof. The resonant tunneling diode includes: a first barrier layer; a second barrier layer; and a potential well layer between the first barrier layer and the second barrier layer, a material of the first barrier layer being AlxInyN1-x-y, 1>x>0, 1>y>0, and/or a material of the second barrier layer being AlmInnN1-m-n, 1>m>0, 1>n>0, and a material of the well layer including a gallium element.

Abstract: A conductive contact structure of a solar cell is provided, includes a substrate; a semiconductor region; and an electrode. The semiconductor region is disposed on or in the substrate. The electrode is disposed in the semiconductor region. The electrode includes a seed layer in contact with the semiconductor region. The seed layer includes an alloy material, and includes a main component and an improved component. The main component is one or more metals having an average refractive index lower than 2 and a wavelength in a range of 850-1200 nm, and the improved component includes any one or more of Mo, Ni, Ti, W, Cr, Mn, Pd, Bi, Nb, Ta, Pa, Si, and V.

Abstract: A photovoltaic cell may include a substrate configured as a single light absorption region. The cell may include at least one first semiconductor region and at least one second semiconductor region arranged on or in the substrate. The cell may include a plurality of first conductive contacts arranged on the substrate and physically separated from one another and a plurality of second conductive contacts arranged on the substrate and physically separated from one another. Each first conductive contact may be configured to facilitate electrical connection with the at least one first semiconductor region. Each second semiconductor conductive contact may be configured to facilitate electrical connection with the at least one second semiconductor region. Each of the first conductive contacts may form at least one separate cell partition with at least one of the second conductive contacts, thereby forming a plurality of cell partitions on or in the substrate.

Abstract: A system including at least one photovoltaic module configured to be installed on a roof deck having an underlayment layer. The photovoltaic module includes at least one solar cell having a first side and a second side opposite the first side, an encapsulant layer juxtaposed with the first side of the solar cell, a glass layer juxtaposed with the encapsulant layer, and a encapsulant-backsheet layer juxtaposed with the second side of the solar cell. The encapsulant layer and the encapsulant-backsheet layer encapsulate the at least one solar cell. The system does not include an intervening layer between the encapsulant-backsheet layer and the underlayment layer.

Abstract: An semiconductor detector includes an n-type semiconductor substrate, a detection electrode formed on a first surface of the semiconductor substrate, a plurality of drift electrodes formed to surround the detection electrode and applied with a voltage causing a potential gradient in which a potential changes toward the detection electrode, a radiation incidence window provided on a second surface of the semiconductor substrate, a P-type semiconductor region formed by adding boron to a surface side on the second surface of the semiconductor substrate through the radiation incidence window, and a depleting electrode causing a reverse bias between the P-type semiconductor region formed on the second surface and an N-type semiconductor region formed in the semiconductor substrate. F is added to the P-type semiconductor region, and a region with the highest concentration of F is located deeper than a region with the highest concentration of B.

Abstract: A display may include a color filter layer, a liquid crystal layer, and a thin-film transistor layer. A camera window may be formed in the display to accommodate a camera. The camera window may be formed by creating a notch in the thin-film transistor layer that extends inwardly from the edge of the thin-film transistor layer. The notch may be formed by scribing the thin-film transistor layer around the notch location and breaking away a portion of the thin-film transistor layer. A camera window may also be formed by grinding a hole in the display. The hole may penetrate partway into the thin-film transistor layer, may penetrate through the transistor layer but not into the color filter layer, or may pass through the thin-film transistor layer and partly into the color filter layer.

Abstract: The embodiments of the present disclosure describe a stressed Ge PD and fabrications techniques for making the same. In one embodiment, a stressor material is deposited underneath an already formed Ge PD. To do so, wafer bonding can be used to bond the wafer containing the Ge PD to a second, handler wafer. Doing so provides support to remove the substrate of the wafer so that a stressor material (e.g., silicon nitride, diamond-like carbon, or silicon-germanium) can be disposed underneath the Ge PD. The stress material induces a stress or strain in the crystal lattice of the Ge which changes its bandgap and improves its responsivity.

Abstract: The present invention relates to a method for planarizing a CIS-based thin film, the method including: electropolishing a CIS-based compound layer by applying current or voltage to an electrochemical cell including: a CIS-based compound layer provided on a conductive base material, as a working electrode; a counter electrode; and an electrolyte solution including a precursor of elements constituting the CIS-based compound layer, a supporting electrolyte, a complexing agent, and an additive including a hydroxy functional group.

Abstract: Disclosed is a method of manufacturing a III-V group nanorod solar cell so that a substrate can be reused. The method may includes a first growth process of forming an etch stop layer on a substrate, a second growth process of growing a sacrificial layer on the etch stop layer, a third growth process of forming, on the sacrificial layer, a pattern layer including an opening at each location at which each nanorod solar cell is able to be grown, a fourth growth process of growing the nanorod solar cells on the sacrificial layer through the openings within the pattern layer, a forming process of forming a solar cell protection layer on outsides of the nanorod solar cells, a first etching process of etching the sacrificial layer and the pattern layer, and a second etching process of etching the etch stop layer.

Abstract: The disclosure discloses a method for manufacturing a solar cell, a solar module, and a power generation system. The manufacturing method includes the following steps: S1: perforating film layer in a first region and/or a second region of a solar cell where an electrode is to be disposed, thus forming a plurality holes; S2: growing a plurality seed layers on the solar cell, contacting with the first region and/or the second region through the plurality of holes or grooves in S1; and S3: horizontally transporting a to-be-electroplated solar cell on a horizontal electroplating device, to form a cathode on the seed layer, where an anode terminal is disposed in an electroplating liquid in an electroplating bath, and a moving mechanism disposed in the electroplating bath drives the solar cell to move from inlet to outlet, thus achieving electroplating.

Abstract: A light emitting device includes a first light emitting diode (LED). The first LED includes a first metallic layer. The first LED additionally includes a first-doped semiconductor layer over the first metallic layer. Additionally, the first LED includes a multi quantum well (MQW) semiconductor layer over the first-doped semiconductor layer. Moreover, the first LED includes a second-doped semiconductor layer over the MQW semiconductor layer. Next, the first LED includes a second metallic layer over the second-doped semiconductor layer. The light emitting device also includes a second LED over the first LED. Further, the light emitting device includes a third LED over the second LED.

Abstract: A light emitting diode (LED) comprises: an n-doped portion; a p-doped portion; and a light emitting region located between the n-doped portion and the p-doped portion. The light emitting region comprises: a light-emitting layer which emits light at a peak wavelength between 400 and 599 nm under electrical bias thereacross; a III-nitride layer located on the light-emitting layer; and a III-nitride barrier layer located on the III-nitride layer. The light emitting diode comprises a porous region of III-nitride material. An LED array and a method of manufacturing an LED with a peak emission wavelength between 400 nm and 599 nm under electrical bias are also provided.

Abstract: A nanorod semiconductor layer having a flat upper surface, a micro-LED including the nanorod semiconductor layer, a pixel plate including the micro-LED , a display device including the pixel plate, and an electronic device including the pixel plate are provided. The nanorod semiconductor layer includes: a main body; and an upper end formed from the main body, wherein the upper end includes: a first inclined surface; a second inclined surface facing the first inclined surface; and a flat upper surface between the first inclined surface and the second inclined surface, and a width of the upper end becomes narrower in an upward direction, and when a length of the upper end protruded from the main body (a thickness of the upper end) is L1, an inclination angle between a surface extending parallel to a surface selected from the first and second inclined surfaces and the flat upper surface is ?, and a width of the main body is D, a width D1 of the flat upper surface satisfies Equation 1.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure may include: a first epitaxial layer disposed on a substrate; a bonding layer disposed on the first epitaxial layer (where the bonding layer is provided with a first through-hole to expose the first epitaxial layer); a silicon substrate disposed on a side of the bonding layer away from the first epitaxial layer (where the first epitaxial layer is bonded to the silicon substrate by the bonding layer, the silicon substrate is provided with a through-silicon-via, and the through-silicon-via communicates with the first through-hole); a silicon device disposed on the silicon substrate; and a second epitaxial layer disposed on the first epitaxial layer exposed by the first through-hole. The present disclosure can improve the quality of the second epitaxial layer, and realize the integration of a silicon device and a III-V semiconductor device.

Abstract: A light-emitting device includes a semiconductor diode structure with one or more light-emitting active layers, an anti-reflection coating on its front surface, and a redirection layer on its back surface. Active-layer output light propagates within the diode structure. The anti-reflection coating on the front surface increases transmission of active-layer output light incident below the critical angle ?c. Active-layer output light incident on the redirection layer at an incidence angle greater than ?c is redirected to propagate toward the front surface at an incidence angle that is less than ?c. Device output light is transmitted by the front surface to propagate in an ambient medium, and includes first and second portions of the active-layer output light incident on the front surface at an incidence angle less than ?c, the first portion without redirection by the redirection layer and the second portion with redirection by the redirection layer.

Abstract: A light-emitting device includes a light-emitting element including an epitaxial structure and a DBR. The DBR includes first and second reflective units. The first reflective unit includes first reflective structures. The second reflective unit includes second reflective structures. Each of the first and second reflective structures has first and second material layers. The first material layer of each of the first reflective structures has an optical thickness different from that of the first material layer of each of the second reflective structures. The second material layer of each of the first reflective structures has an optical thickness different from that of the second material layer of each of the second reflective structures. In each of the first and second reflective structures, the first material layer has a refractive index different from that of the second material layer.

Abstract: An optoelectronic unit includes a semiconductor chip configured to emit primary radiation with a first wavelength range during operation of the optoelectronic unit. The optoelectronic unit also includes a component including an optically active material. The component is arranged at least partially in the beam path of the semiconductor chip. The optically active material is not intended to be excited by the primary radiation with the first wavelength range. The optically active material incudes a proportion in the component of 0.004 wt%, inclusive, to 1 wt%, inclusive.

Abstract: Exemplary pixel structures are described that include a first light emitting diode structure, operable to generate blue light characterized by a peak emission wavelength of greater than or about 450 nm, and a second light emitting diode structure positioned on the first light emitting diode structure. The second light emitting diode structure is operable to generate ultraviolet light characterized by a peak emission wavelength of less than or about 380 nm. The pixel structures may also include a photoluminescent region, containing a photoluminescent material, that is positioned on the second light emitting diode structure.

Abstract: A light-emitting diode (LED) lamp having high color-rendering property includes a lamp housing, a light source board, a plurality of white LEDs and a plurality of purple LEDs. The light source board is disposed in the lamp housing. The white LEDs are disposed on the light source board. The purple LEDs are disposed on the light source board. The wavelength range of the lights emitted by the purple LEDs is within the ultraviolet A (UVA) band.

Abstract: A lighting device with high color-rendering property includes a substrate, a blue light-emitting diode (LED) die, a purple LED die and a transparent housing. The blue LED die is disposed on the substrate. The purple LED die is disposed on the substrate. The transparent housing is disposed on the substrate to form an accommodating space between the substrate and the transparent housing. The blue LED die and the purple LED die are inside the accommodating space, and the inner surface of the transparent housing is coated by a phosphor.

Abstract: An LED package device includes a substrate, an LED chip arranged on the substrate and a transparent groove. A quantum dot layer is provided inside the transparent groove, a barrier film layer is provided on the quantum dot layer, side walls of the barrier film layer are connected and sealed with side walls of the transparent groove, and a phosphor layer is provided on the barrier film layer. The transparent groove is inverted on the sealing adhesive layer and connected with the sealing adhesive layer, and an opening of the transparent groove is sealed by the sealing adhesive layer to cover the quantum dot layer, the barrier film layer and the phosphor layer. The device can isolate water vapor and oxygen, thereby effectively avoiding the failure problem of the quantum dot layer and reducing the failure risk caused by strong blue light to the quantum dot material.

Abstract: A light emitting module is provided. The light emitting module includes a substrate, light emitting elements, an encapsulant material and dimming structures. The light emitting elements are disposed over the substrate. The encapsulant material covers the light emitting elements and the substrate, and the encapsulant material has an encapsulant height H. The dimming structures are disposed over the encapsulant material or embedded in the encapsulant material. The dimming structures have a maximum dimming thickness h. The encapsulant thickness H and the maximum dimming thickness h satisfy the following relationship: 0.01?h/H?1.

Abstract: A display device is provided. The display device includes a substrate, a light-shielding layer, a plurality of first light-emitting elements, and a plurality of second light-emitting elements. The light-shielding layer is disposed on the substrate. The first light-emitting elements are disposed on the substrate. The second light-emitting elements are disposed between the light-shielding layer and the substrate. One of the second light-emitting elements is alternately disposed between any two adjacent first light-emitting elements.

Abstract: A light-emitting module includes: a first light source unit including: a first light source, and a first lens on which light emitted from the first light source is incident; a driver configured to rotate the first lens; and a controller configured to, conjunctively with the driver, control an output of the first light source. A central axis of light emitted from the first lens is oblique to a rotation axis of the first lens. The controller is configured to control the output of the first light source according to a position along a trajectory of the central axis of the light emitted from the first lens.

Abstract: The present invention is applicable to a display device-related technical field, and relates to, for example, a display device using a micro light-emitting diode (LED). The present invention provides the display device using an LED, wherein the display device may comprise: a thin film transistor (TFT) substrate including a TFT for driving an active matrix and a connection pad connected to the TFT; a light-emitting package including a unit pixel disposed on the TFT substrate and electrically connected to the connection pad, and including a transparent resin layer, a wiring layer positioned on the TFT substrate, and at least one LED positioned between the TFT substrate and the transparent resin layer, electrically connected to the wiring layer, and each forming a sub-pixel; and connection wiring electrically connecting the wiring layer and the connection pad to each other.

Abstract: The invention relates to a radiation-emitting component, comprising: a radiation-emitting semiconductor chip, which during operation emits electromagnetic radiation from a radiation-emitting main face and has two electrical contacts, which are arranged on a main face of the radiation-emitting semiconductor chip opposite the radiation-emitting main face, a lead frame with two electrical connection points, each of which has a mounting face, wherein at least one mounting face is delimited by a wall each electrical contact of the radiation-emitting semiconductor chip is applied to a mounting face, and the radiation-emitting semiconductor chip protrudes beyond the wall. Additionally described are a method for producing a radiation-emitting component and a module comprising a radiation-emitting component.

Abstract: Provided is a display device. The display device includes a substrate, a display panel including a display disposed on a front surface of the substrate and a flexible base material extending from the display to surround a portion of each of a side surface and a rear surface of the substrate, and a support layer disposed between the side surface of the substrate and the flexible base material to support the flexible base material. The flexible base material includes: a pair of curved portions spaced apart from the support layer and a side cover portion that is configured to connect the pair of curved portions to each other and is in contact with the support layer.

Abstract: A display module includes a substrate, a plurality of substrate electrode pads provided on the substrate, and a plurality of micro light-emitting diodes (LEDs) connected to the plurality of substrate electrode pads, where each of the plurality of substrate electrode pads includes a first region in which a plurality of contact protrusions are formed, and a second region configured to be connected with a repair micro LED.

Abstract: A semiconductor light-emitting device includes a junction or active layer between doped semiconductor layers coextensive over a contiguous device area, corresponding sets of electrical contacts connected to the semiconductor layers, and multiple nanostructured optical elements at a surface of one semiconductor layer opposite the other semiconductor layer. Composite electrical contacts of one set include a conductive layer, a transparent dielectric layer between the conductive and semiconductor layers, and vias through the dielectric layer connecting the conductive and semiconductor layers. The nanostructured elements redirect light, propagating laterally in optical modes supported by the semiconductor layers, to exit the device. The composite electrical contacts can be independent and define independently addressable pixel areas of the device. The nanostructured elements and thin semiconductor layers can yield high contrast between adjacent pixel areas without trenches between them.