Abstract: An electro-static discharge (ESD) protection device includes a first well region, a second well region, a first diffusion region disposed in the first well region, a plurality of second diffusion regions disposed in the first well region separated from each other by the first diffusion region in a first direction, a third diffusion region disposed in the second well region, a plurality of fourth diffusion regions disposed in the second well region separated from each other by the third diffusion region in the first direction, a resistive pattern coupled to the first diffusion region through a first contact plug, a first electrode coupled to the plurality of second diffusion regions and electrically coupled to the resistive pattern, and a second electrode coupled to the third diffusion region and coupled to the plurality of fourth diffusion regions.

Abstract: A semiconductor device includes a semiconductor substrate, an internal circuit provided on the semiconductor substrate, a first and a second pads connected to the internal circuit, a first ESD protection circuit connectable to the first pad, and a second ESD protection circuit connectable to the second pad. The first ESD protection circuit includes a first ESD protection element, and the second ESD protection circuit includes a second and a third ESD protection elements. The second pad is connected to the internal circuit via the second ESD protection element, and the first pad is directly connected to the internal circuit.

Abstract: An apparatus includes a junction termination edge, a unipolar power transistor, and an RC snubber. The RC snubber has a capacitor between a poly silicon structure and a semiconductor substrate, and part of the junction termination edge. The capacitor has a p-n junction. The RC snubber has a poly silicon resistor between a source of the unipolar power transistor and a first layer forming the capacitor. The unipolar transistor and the RC snubber are coupled in parallel. The RC snubber and the unipolar power transistor are formed monolithically on the semiconductor substrate.

Abstract: The present application discloses a semiconductor device, an electronic system and an electrostatic discharge (ESD) protection method for a semiconductor device thereof. The semiconductor device includes a substrate, an operation solder structure disposed on a first surface of the substrate for receiving an operation signal, a detection solder structure disposed on the first surface of the substrate for receiving a chip connection signal, and a semiconductor chip disposed on a second surface of the substrate. The semiconductor chip includes an operation electrical contact coupled to the operation solder structure, a detection electrical contact coupled to the detection solder structure, an ESD protection unit coupled to the operation electrical contact, and a logic circuit coupled to the detection electrical contact for adjusting capacitance of the ESD protection unit according to the chip connection signal.

Abstract: A semiconductor device includes a resistor having a resistor body including polysilicon, with fluorine in the polysilicon. The resistor body has a laterally alternating distribution of silicon grain sizes. The semiconductor device further includes an MOS transistor having a gate including polysilicon with fluorine. The fluorine in the gate has a higher average concentration than the fluorine in the resistor body. The semiconductor device may be formed by forming a gate/resistor layer including polysilicon. A fluorine implant mask is formed over the gate/resistor layer, exposing the gate/resistor layer in an area for the gate and over implant segments in an area for the resistor body. The implant segments do not cover the entire area for the resistor body. Fluorine is implanted into the gate/resistor layer where exposed by the fluorine implant mask. The gate/resistor layer is patterned to form the gate and the resistor body.

Abstract: A lower nanosheet stack including alternating layers of a first work function metal and a semiconductor channel material, an upper nanosheet stack including alternating layers of a second work function metal and the semiconductor channel material, one or more dielectric layers between the lower nanosheet stack and the upper nanosheet stack, each separated by an inner spacer. An embodiment where the one or more partial dielectric layers each include an opening. Forming an upper nanosheet stack vertically aligned above an intermediate stack, vertically aligned above a lower nanosheet stack, the upper nanosheet stack, the lower nanosheet stack each including alternating layers of a first sacrificial material and a semiconductor channel material, the intermediate stack including one or more alternating layers of the sacrificial material and a second sacrificial material, recessing the second sacrificial material; and forming second inner spacers where the second sacrificial material was recessed.

Abstract: An integrated circuit device including an active region; an active cutting region at a side of the active region in a first direction; a fin active pattern extending on the active region in the first direction, the fin active pattern including a source region and a drain region; a gate pattern extending across the active region and the fin active pattern in a second direction perpendicular to the first direction, the gate pattern not being in the active cutting region; and an isolated gate contact region in contact with the gate pattern outside of the active region.

Abstract: Gate-all-around integrated circuit structures having dual metal gates and gate dielectrics with a single polarity dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A P-type gate stack is over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a P-type conductive layer over a first gate dielectric including a high-k dielectric layer and a dipole material layer. An N-type gate stack is over the second vertical arrangement of horizontal nanowires, the N-type gate stack having a mid-gap conductive layer over a second gate dielectric including the high-k dielectric layer and the dipole material layer.

Abstract: An integrated circuit includes: (i) a first transistor having a first gate extending in a first direction, a first drain, and a first source that is separated from the first drain in a second direction, which is perpendicular to the first direction, (ii) a second transistor having a second gate extending in one of the first and second directions, a second drain, and a second source that is separated from the second drain in a third direction, which is perpendicular to the first and second directions, and (iii) a first connection structure that electrically connects the first transistor to the second transistor, and includes a pattern extending in the first direction between the first transistor and the second transistor.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a semiconductor fin having a first portion having a first width and a second portion having a second width substantially less than the first width. The first portion has a first surface, the second portion has a second surface, and the first and second surfaces are connected by a third surface. The third surface forms an angle with respect to the second surface, and the angle ranges from about 90 degrees to about 130 degrees. The structure further includes a gate electrode layer disposed over the semiconductor fin and source/drain epitaxial features disposed on the semiconductor fin on opposite sides of the gate electrode layer.

Abstract: A semiconductor device includes a first conductivity-type substrate, and a cell region including: a second conductivity type deep well; first and second non-deep wells having the second conductivity-type, the first and second non-deep wells being in corresponding first and second portions of the substrate, the first and second portions of the substrate being in the deep well; and first, second, third and fourth transistor-regions. The first and second transistor-regions are correspondingly in the first and second non-deep wells and include first conductivity-type first transistors. The third and fourth transistor-regions are in the third and fourth portions of the substrate which are in the deep well, and include second transistors having the second conductivity-type. The first transistor-region is configured for a first power domain. The second, third and fourth transistor-regions are configured for a second power domain that is different than the first power domain.

Abstract: Apparatus and circuits with dual threshold voltage transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first layer comprising a first III-V semiconductor material formed over the substrate; a first transistor formed over the first layer, and a second transistor formed over the first layer. The first transistor comprises a first gate structure comprising a first material, a first source region and a first drain region. The second transistor comprises a second gate structure comprising a second material, a second source region and a second drain region. The first material is different from the second material.

Abstract: A semiconductor device includes a substrate including an N-stack cell, a buffer cell and an M-stack cell that are on the substrate, the buffer cell being between the N-stack and M-stack cells, an active pattern extending from the N-stack cell to the M-stack cell via the buffer cell, an N-stack channel pattern on the active pattern of the N-stack cell, an M-stack channel pattern on the active pattern of the M-stack cell, a dummy channel pattern on the active pattern of the buffer cell, an N-stack epitaxial pattern between the N-stack channel pattern and the dummy channel pattern, and an M-stack epitaxial pattern between the M-stack channel pattern and the dummy channel pattern. The N-stack channel pattern includes stacked N semiconductor patterns. The M-stack channel pattern includes stacked M semiconductor patterns. Each of N and M is an integer number of 2 or more, and M is greater than N.

Abstract: An integrated circuit may include a first active pattern group extending in a first direction in a first row and including a plurality of first active patterns overlapping each other in the first direction, the first row extending in the first direction, and a plurality of gate electrodes extending in a second direction perpendicular to the first direction in the first row. The plurality of first active patterns may include any two first active patterns that are adjacent to each other in the first direction, the two first active patterns have first and second widths in the second direction, respectively, and the first and second widths are identical or are different by a first offset or a second offset.

Abstract: In a semiconductor integrated circuit device, a cell having no logical function placed in an end row of a plurality of cell rows includes: a third transistor opposed to a transistor of a cell adjacent in the Y direction; a third buried power line supplying VSS placed on the same side of the third transistor as the transistor of the adjacent cell; and a fourth buried power line supplying VDD placed on the opposite side of the third transistor from the transistor of the adjacent cell. The fourth buried power line is greater in size in the Y direction than the third buried power line.

Abstract: A device includes an active semiconductor layer on top of and in contact with an insulating layer which overlies a semiconductor substrate. A transistor for the device includes a source region, a drain region, and a body region arranged in the active semiconductor layer. The body region of the transistor is electrically coupled to the semiconductor substrate using a conductive via that crosses through the insulating layer.

Abstract: A method for forming an integrated circuit includes following operations. A substrate is received. The substrate includes a first region, a second region and an isolation structure. The isolation structure has a first top surface, a second top surface lower than the first top surface, and a boundary between the first top surface and the second top surface. A first device is formed in the first region, a second device is formed in the second region, and a dummy structure is formed on a portion of the first top surface, a top of the second top surface and the boundary. A dielectric structures is formed over the substrate. Top surfaces of the dielectric structure, the first device, the second device and the dummy structure are aligned with each other. A first metal gate is formed in the first device, and a second metal gate is formed in the second device.

Abstract: An array substrate includes a substrate; a gate disposed on the substrate; a first insulating layer covering the gate; a first semiconductor layer and a second semiconductor layer that are provided on the first insulating layer, a channel corresponding to the gate being provided in the first semiconductor layer and second semiconductor layer, the second semiconductor layer including a first metal oxide semiconductor layer and a second metal oxide semiconductor layer which are stacked, both the first metal oxide semiconductor layer and the second metal oxide semiconductor layer being disconnected at the channel, and the oxygen vacancy concentration of the second metal oxide semiconductor layer being less than the oxygen vacancy concentration of the first metal oxide semiconductor layer; and a source and a drain that are provided on the second semiconductor layer, both the source and the drain being in electrically conductive contact with the second semiconductor layer.

Abstract: A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, and a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the first oxide semiconductor layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.

Abstract: A display device includes pixels. Each of the pixels includes electrodes disposed on a base layer; a first insulating layer disposed on the electrodes; a light emitting element disposed on the first insulating layer; a bank disposed on the first insulating layer and protruding in a thickness direction of the base layer; and a second insulating layer, at least a portion of the second insulating layer being disposed on the first insulating layer. At least part of the electrodes of a pixel among the pixels are spaced apart from at least part of the electrodes of another pixel adjacent to the pixel with an open area being disposed between the electrodes. The first insulating layer includes a first opening overlapping the open area in a plan view, and the second insulating layer includes a second opening overlapping the open area in a plan view.

Abstract: There are provided an imaging device and an electronic device that minimize an ineffective region inside a pixel and achieve reduction in size, high SN, high sensitivity, high resolution, and a reduced afterimage.

Abstract: Provided are an imaging device and an electronic device capable of suppressing deterioration in characteristic. An imaging device is provided with an N-type first semiconductor region, a P-type second semiconductor region in contact with one surface of the first semiconductor region, a light absorbing region provided on a side opposite to the first semiconductor region across the second semiconductor region, and an anode electrode provided at a position facing the second semiconductor region across the light absorbing region. The anode electrode includes a P-type semiconductor having a refractive index of 1.8 or larger and an optical bandgap of 1.9 eV or larger.

Abstract: An imaging device includes: a photoelectric converter that generates a signal charge by photoelectric conversion; a semiconductor substrate that includes a first semiconductor layer containing an impurity of a first conductivity type; a charge accumulation region that is an impurity region of a second conductivity type in the first semiconductor layer and that accumulates the signal charge; a transistor that includes, as one of a source and a drain, a first impurity region of the second conductivity type in the first semiconductor layer; and a blocking structure located between the charge accumulation region and the first impurity region. The blocking structure includes a second impurity region of the first conductivity type in the first semiconductor layer and a third impurity region of the first conductivity type in the first semiconductor layer, the third impurity region having an impurity concentration different from that of the second impurity region.

Abstract: An image sensor includes a first photodiode group, a second photodiode group, a first transfer transistor group, a second transfer transistor group, a floating diffusion region of a substrate in which electric charges generated in the first photodiode group are stored, and a power supply node for applying a power supply voltage to the second photodiode group. A barrier voltage is applied to at least one transfer transistor of the second transfer transistor group. The power supply voltage allows electric charges, generated in the second photodiode group, to migrate to the power supply node, and the barrier voltage forms a potential barrier between the second photodiode group and the floating diffusion region.

Abstract: An image sensor includes a charge accumulation region having a first conductivity type and disposed in a substrate, a charge storage region having the first conductivity type and disposed in the substrate to be laterally spaced apart from the charge accumulation region, a transfer gate electrode disposed on a channel region between the charge accumulation region and the charge storage region to transfer a charge from the charge accumulation region to the charge storage region, a first well region having a second conductivity type and disposed below the charge storage region to inhibit a charge generated below the charge storage region from being moved to the charge storage region, and a second well region having the second conductivity type and disposed below a portion of one side of the first well region adjacent to a neighboring image cell.

Abstract: In example embodiments, an optical component includes a dielectric structure having a substantially rectangular cross-section with an upper surface and a lower surface. A first electrically conducting layer is provided on the upper surface, where the first electrically conducting layer has a first opening positioned to accept incoming electromagnetic radiation. The second electrically conducting layer has a second opening positioned to emit electromagnetic radiation, e.g. toward a CMOS sensor pixel in a silicon substrate. The dimensions of the optical component are configured to provide constructive interference for incident radiation of a selected wavelength.

Abstract: Provided are a color separation element and an image sensor including the same. The color separation element includes a spacer layer; and a color separation lens array, which includes at least one nano-post arranged in the spacer layer and is configured to form a phase distribution for splitting and focusing incident light according to wavelengths, wherein periodic regions in which color separation lens arrays are repeatedly arranged are provided, and the color separation lens array is configured to interrupt phase distribution at the boundary of the periodic regions.

Abstract: A solid-state image sensor includes a substrate, photoelectric conversion elements positioned on the substrate, a filter module positioned above the photoelectric conversion elements positioned on the substrate, lenses positioned above the filter module positioned above the photoelectric conversion elements, a resin layer formed such that the resin layer is surrounding an outer edge of the filter module positioned on the substrate, and an anti-reflection film formed on the lenses and resin layer such that the anti-reflection film has a peripheral film portion covering a peripheral portion of the resin layer. The filter module is positioned such that light is transmitted through the filter module before being incident on the photoelectric conversion elements, and the anti-reflection film is formed such that the peripheral film portion has an uneven shape having unevenness in thickness direction of the resin layer and at least part of an outer edge protruding outside the resin layer.

Abstract: A photoelectric conversion apparatus includes a semiconductor layer including a front surface, a back surface, and a plurality of photoelectric conversion portions, a first insulation film on a back surface side of the semiconductor layer, a light shielding film between the first insulation film and the back surface, a first light shielding wall in the first insulation film, and a second light shielding wall in the first insulation film, wherein an end portion of the first light shielding wall that is on the back surface side is in contact with the light shielding film, and wherein a distance between an end portion of the light shielding film that is on the back surface side and the back surface is greater than a distance between an end portion of the second light shielding wall that is on the back surface side and the back surface.

Abstract: A semiconductor device is provided as a back-illuminated solid-state imaging device. The device is manufactured by bonding a first semiconductor wafer with a pixel array in a half-finished product state and a second semiconductor wafer with a logic circuit in a half-finished product state together, making the first semiconductor wafer into a thin film, electrically connecting the pixel array and the logic circuit, making the pixel array and the logic circuit into a finished product state, and dividing the first semiconductor wafer and the second semiconductor being bonded together into microchips.

Abstract: A back side illuminated image sensor includes a pixel formed by three doped photosensitive regions that are superposed vertically in a semiconductor substrate. Each photosensitive region is laterally framed by a respective vertical annular gate. The vertical annular gates are biased by a control circuit during an integration phase so as to generate an electrostatic potential comprising potential wells in the central portion of the volume of each doped photosensitive region and a potential barrier at each interface between two neighboring doped photosensitive regions.

Abstract: Provided is an imaging apparatus including an imaging unit having a plurality of pixels, the pixels each having: a conversion element converting incident light into photoelectrons; a floating diffusion layer electrically connected to the conversion element and converting the photoelectrons into a voltage signal; a differential amplifier circuit electrically connected to the floating diffusion layer, including an amplifier transistor to which a potential of the floating diffusion layer is input, and amplifying the potential of the floating diffusion layer; a feedback transistor electrically connected to the amplifier transistor and initializing the differential amplifier circuit; a clamp capacitance connected in series between the floating diffusion layer and the amplifier transistor; and a reset transistor connected in parallel between the floating diffusion layer and the clamp capacitance and initializing the potential of the floating diffusion layer.

Abstract: A pixel structure, an image sensor, an electronic device and a method for controlling an image sensor are provided.

Abstract: A method of manufacturing an image sensor includes forming a first chip structure including a circuit wiring structure, forming a second chip structure on the first chip structure, the second chip structure including a plurality of photoelectric conversion device regions, forming a lens material layer on the second chip structure, forming an isolation groove defining a plurality of lens regions in the lens material layer, forming internal grooves in the plurality of lens regions of the lens material layer surrounded by the isolation groove, and forming lens patterns using the lens material layer in which the isolation groove and the internal grooves are formed.

Abstract: The present disclosure provides a method for forming a backside illumination CMOS image sensor, including: providing a first substrate having a first surface and a second surface opposite to each other; forming a photoelectric epitaxial layer on the second surface, wherein the photoelectric epitaxial layer has a third surface and a fourth surface opposite to each other, and the second surface is adjacent to the third surface, wherein the photoelectric epitaxial layer is includes a groove extending from the fourth surface to the third surface, and the photoelectric epitaxial layer includes a plurality of first doped areas and a plurality of second doped areas surrounding the plurality of first doped areas respectively; forming a device layer after forming the groove and the photoelectric epitaxial layer; and forming an isolation layer in the groove. The method can reduce generation of dark current and improve performance of the CMOS image sensor.

Abstract: A method of manufacturing an LED device comprises the steps of: forming an n-doped connecting layer of III-nitride material over a porous region of III-nitride material; forming a first electrically-insulating mask layer on the n-doped connecting layer; removing a portion of the first mask layer to expose a first exposed region of the n-doped connecting layer; forming a first LED structure, which is configured to emit light at a first emission wavelength, on the first exposed region of the n-doped connecting layer; forming a second electrically-insulating mask layer over the first LED structure and the n-doped connecting layer; removing a portion of the second mask layer to expose a second exposed region of the n-doped connecting layer; and forming a second LED structure, which is configured to emit light at a second emission wavelength different from the first emission wavelength, on the second exposed region of the n-doped connecting layer.

Abstract: A display device includes a substrate including an emission area and a non-emission area, a first connection electrode provided on the substrate and electrically connected to a first driving power, a second connection electrode provided to be spaced apart from the first connection electrode in a first direction and electrically connected to a second driving power, a dummy electrode provided to be spaced apart from the first connection electrode in a second direction intersecting the first direction, light emitting elements provided between the second connection electrode and the dummy electrode in a plan view and forming the emission area, a first pixel electrode provided on the first and second connection electrodes and electrically connected to the first connection electrode, and a second pixel electrode provided on the first and second connection electrodes and electrically connected to the second connection electrode.

Abstract: A method for manufacturing an image display device includes: forming a conductive layer on a first substrate, wherein at least a part of the conductive layer is formed of a single-crystal metal; forming a semiconductor layer on said part of the conductive layer, the semiconductor layer comprising a light-emitting layer; forming a light-emitting element by patterning the semiconductor layer; forming a first insulating film that covers the first substrate, the conductive layer, and the light-emitting element; forming a circuit element on the first insulating film; forming a second insulating film that covers the first insulating film and the circuit element; exposing a surface that includes a light-emitting surface of the light-emitting element by removing a portion of the first insulating film and a portion of the second insulating film; and forming a wiring layer on the second insulating film.

Abstract: A method of forming a semiconductor device includes: forming a passivation layer over a conductive pad that is disposed over a substrate; and forming an inductive component over the passivation layer, including: forming a first insulation layer and a first magnetic layer successively over the passivation layer; forming a first polymer layer over the first magnetic layer; forming a first conductive feature over the first polymer layer; forming a second polymer layer over the first polymer layer and the first conductive feature; patterning the second polymer layer, where after the patterning, a first sidewall of the second polymer layer includes multiple segments, where an extension of a first segment of the multiple segments intersects the second polymer layer; and after patterning the second polymer layer, forming a second insulation layer and a second magnetic layer successively over the second polymer layer.

Abstract: A semiconductor device includes a capacitor structure. The capacitor structure includes a bottom electrode, a dielectric layer, and a top electrode that are sequentially stacked in a first direction. The dielectric layer includes first dielectric layers and second dielectric layers interposed between the bottom electrode and the top electrode and are that are alternately stacked in the first direction. The first dielectric layers include a ferroelectric material, and the second dielectric layers include an anti-ferroelectric material. A lowermost second dielectric layer is interposed between a lowermost first dielectric layer and the bottom electrode, and an uppermost second dielectric layer is interposed between an uppermost first dielectric layer and the top electrode.

Abstract: A semiconductor device includes a capacitor structure. The capacitor structure includes a bottom electrode, a dielectric layer, and a top electrode that are stacked in a first direction. The dielectric layer includes a first dielectric layer, a second dielectric layer stacked on the first dielectric layer in the first direction, and a first impurity provided in the first dielectric layer. The first dielectric layer includes a ferroelectric material, and the second dielectric layer includes an anti-ferroelectric material.

Abstract: An integrated circuit (IC) includes a transistor, and a first layer including electrically conductive material. In an example, the first layer is conductively coupled to the transistor. The IC further includes a second layer including electrically conductive material above the first layer. The IC further includes one or more intervening layers between the first and second layers. In an example, the one or more intervening layers include at least a third layer, wherein the third layer includes (i) a first metal, (ii) oxygen, and (iii) one or both of a second metal or an oxide thereof within the third layer. In an example, the first layer, the second layer, and the one or more intervening layers form a metal-insulator-metal (MIM) capacitor. In an example, the MIM capacitor and the transistor, in combination, form a memory cell of a dynamic random access memory (DRAM) array.

Abstract: A device includes at least one capacitor. The capacitor includes an assembly of two metal pads and at least two metal plates, each plate extending at least from one pad to the other, a first insulating layer conformally covering said assembly, a second conductive layer conformally covering the first layer.

Abstract: A semiconductor device includes a substrate, lower electrodes on the substrate, a dielectric layer covering the lower electrodes, and an upper electrode covering the dielectric layer. The dielectric layer includes a first region in contact with the lower electrodes, a second region in contact with the upper electrode, and a third region between the first and second regions. The third region includes a first insertion layer including a first oxide including a first metal having a first valence and a second oxide including a second metal having a second valence different from the first valence. A thickness of the dielectric layer is about 40 ? to about 60 ?. A thickness of the first insertion layer is about 3 ? to about 10 ?. A ratio of the second metal to total elements in the dielectric layer is about 5 at % to about 15 at %.

Abstract: A trench-gate transistor device includes a substrate and a transistor structure. The transistor structure includes a plurality of superjunctions arranged in a first direction, a rectifying area that has at least one Schottky-based diode, and at least one active unit that is located at a side of said rectifying area in a second direction that intersects with the first direction.

Abstract: A drift layer has a SJ structure with a parallel pn layer; an n+-type buffer layer is between the parallel pn layer and an n++-type drain layer. An impurity concentration of the n+-type buffer layer is adjusted to be at least equal to that of n-type column regions of the parallel pn layer, to be relatively low in a portion facing the parallel pn layer and approach the impurity concentration of the n-type column regions, and to increase closer to the n++-type drain layer. The impurity concentration of the n+-type buffer layer is adjusted so that an impurity concentration difference between the n+-type buffer layer and the n++-type drain layer near the border between the n+-type buffer layer and the n++-type drain layer is as small as possible. An impurity concentration distribution of the n+-type buffer layer is formed by stacking n+-type buffer layers in descending order of impurity concentration from the n++-type drain layer.

Abstract: A semiconductor device including a semiconductor substrate; a first parallel pn layer in which first first-conductivity-type column regions and first second-conductivity-type column regions repeatedly alternate with one another in an active region; a second parallel pn layer in which second first-conductivity-type column regions and second second-conductivity-type column regions repeatedly alternate with one another, in a termination region; a device structure provided between the first main surface of the semiconductor substrate and the first parallel pn layer; a first electrode provided at the first main surface and electrically connected to the device structure; and a second electrode provided at the second main surface of the semiconductor substrate. The plurality of second first-conductivity-type column regions and the plurality of second second-conductivity-type column regions are disposed in concentric shapes surrounding a perimeter of the first parallel pn layer in a plan view.

Abstract: A semiconductor device includes active regions on a substrate, a gate structure intersecting the active regions, a source/drain region on the active regions and at a side surface of the gate structure, a gate spacer between the gate structure and the source/drain region, the gate spacer contacting the side surface of the gate structure, a lower source/drain contact plug connected to the source/drain region, a gate isolation layer on the gate spacer, an upper end of the gate isolation layer being at a higher level than an upper surface of the gate structure and an upper surface of the lower source/drain contact plug, a capping layer covering the gate structure, the lower source/drain contact plug, and the gate isolation layer, and an upper source/drain contact plug connected to the lower source/drain contact plug and extending through the capping layer.

Abstract: A fuse element, a semiconductor device, and a method for activating a backup unit are provided. The fuse element includes an active area, which includes a source region and a drain region beside the source region, a gate region disposed on the active area, and a shallow trench isolation (STI) structure surrounding the active area. In addition, the drain region includes a terminal configured to receive a stress voltage, such that a conductive path is established through the drain region to the source region.

Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first to fifth semiconductor regions, and a gate electrode. The first semiconductor region is provided on the first electrode, and electrically connected to the first electrode. The second semiconductor region is provided on a part of the first semiconductor region. The third semiconductor region is provided on another part of the first semiconductor region. The third semiconductor region includes first and second regions. The fourth semiconductor region is provided on the second semiconductor region. The fifth semiconductor region is provided on a part of the fourth semiconductor region. The gate electrode faces the fourth semiconductor region with a gate insulating layer interposed between the gate electrode and the fourth semiconductor region. The second electrode is provided on the fourth and fifth semiconductor regions. The second electrode is electrically connected to the fourth and fifth semiconductor regions.