Patents Issued in September 14, 2023
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Publication number: 20230290721Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Individual of the conductive tiers comprise laterally-outer edges comprising conductive molybdenum-containing metal material extending horizontally-along its memory block. Channel-material strings extend through the insulative tiers and the conductive tiers. At least one of conductive or semiconductive material is formed extending horizontally-along the memory blocks laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material that extends horizontally-along its memory block. Insulator material extending horizontally-along the memory blocks is formed laterally-outward of the at least one of the conductive or the semiconductive material that is laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material.Type: ApplicationFiled: March 8, 2022Publication date: September 14, 2023Applicant: Micron Technology, Inc.Inventors: Jordan D. Greenlee, Jiewei Chen, Sijia Yu, Chieh Hsien Quek, Rita J. Klein, Nancy M. Lomeli
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Publication number: 20230290722Abstract: An integrated circuit (IC) includes a first memory cell and a second memory cell. The first memory cell includes (i) a first transistor and (ii) a first capacitor coupled to the first transistor, where an upper electrode of the first capacitor is coupled to a first conductive structure. The second memory cell is above the first memory cell. The second memory cell includes (i) a second transistor and (ii) a second capacitor coupled to the second transistor. An upper electrode of the second capacitor is coupled to a second conductive structure. In an example, an interconnect feature includes a continuous and monolithic body of conductive material. In an example, the continuous and monolithic body extends through the second conductive structure, and further extends through the first conductive structure. In an example, the first and second memory cells are dynamic random access memory (DRAM) memory cells.Type: ApplicationFiled: March 11, 2022Publication date: September 14, 2023Applicant: Intel CorporationInventors: Travis W. Lajoie, Juan Alzate Vinasco, Abhishek Anil Sharma, Van H. Le, Moshe Dolejsi, Yu-Wen Huang, Kimberly Pierce, Jared Stoeger, Shem Ogadhoh
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Publication number: 20230290723Abstract: A semiconductor structure including: a substrate including a plurality of conductive layers and a plurality of insulating layers stacked alternately with each other along a vertical direction of the substrate; a first conductive via structure extending from a top conductive layer of the conductive layers to a bottom conductive layer of the conductive layers and including a first capacitive structure, the first capacitive structure extending in a first conductive layer of the conductive layers; a second conductive via structure extending from the top conductive layer to the bottom conductive layer and including a second capacitive structure extending in the first conductive layer; and a third capacitive structure extending in the first conductive layer or a second conductive layer of the conductive layers, wherein the third capacitive structure forms a first mutual capacitance with the first capacitive structure and a second mutual capacitance with the second capacitive structure.Type: ApplicationFiled: August 12, 2022Publication date: September 14, 2023Inventors: YANBIN CHEN, TENGFEI WANG, TINGTING PANG, SHUAI WANG, HUILI FU, WENKAI FAN, XU YAN, HUAN LIU, JIANWEI GUO
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Publication number: 20230290724Abstract: A semiconductor component for a memory device is provided. The semiconductor component comprises a first active region extending in a first direction; a second active region extending in the first direction; a first conductive layer disposed across the first active region and the second active region, in a second direction substantially perpendicular to the first direction; a second conductive layer extending in the first direction; and a first conductive via connecting the first conductive layer and the second conductive layer.Type: ApplicationFiled: May 19, 2023Publication date: September 14, 2023Inventor: CHIN-MING FU
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Publication number: 20230290725Abstract: A method for activating a backup unit includes providing a fuse element connected to the backup unit. The fuse element includes an active area, which includes a source region and a drain region beside the source region, a gate region disposed on the active area, and a shallow trench isolation (STI) structure surrounding the active area. The method also includes applying a stress voltage on the drain region of the fuse element; accumulating electrons in a portion of the STI structure adjacent to the drain region; generating a conductive path through the drain region and the source region so that the fuse element is conductive; and activating the backup unit through the fuse element.Type: ApplicationFiled: March 10, 2022Publication date: September 14, 2023Inventors: YI-JU CHEN, JUI-HSIU JAO
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Publication number: 20230290726Abstract: An integrated circuit includes a first conductive structure, a second conductive structure, and a first spacer and a second spacer each comprising a first dielectric material. The integrated circuit further includes a layer comprising a second dielectric material that is compositionally different from the first dielectric material. The integrated circuit further includes a first interconnect feature above and at least partially landed on the first conductive structure. In an example, the first interconnect feature is laterally between the first spacer and the second spacer. The integrated circuit further includes a second interconnect feature above and at least partially landed on the second conductive structure. In an example, the second interconnect feature is laterally between the second spacer and the layer comprising the second dielectric material.Type: ApplicationFiled: March 11, 2022Publication date: September 14, 2023Applicant: Intel CorporationInventors: Moshe Dolejsi, Travis W. Lajoie, Abhishek Anil Sharma
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Publication number: 20230290727Abstract: A semiconductor device may include a substrate including a cell region and a core/peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core/peripheral regions of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. A peripheral contact plug may be formed in the core/peripheral regions of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.Type: ApplicationFiled: May 23, 2023Publication date: September 14, 2023Inventors: Sangoh Park, Dongjun Lee, Keunnam Kim, Seunghune Yang
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Publication number: 20230290728Abstract: Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.Type: ApplicationFiled: May 19, 2023Publication date: September 14, 2023Inventors: Andrew COLLINS, Bharat P. PENMECHA, Rajasekaran SWAMINATHAN, Ram VISWANATH
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Publication number: 20230290729Abstract: Provided herein may be a memory device and a method of manufacturing the same. The memory device may include a plurality of insulating layers and a plurality of gate lines configured to be alternately stacked, and a cell plug configured to pass through the plurality of insulating layers and the plurality of gate lines, wherein the plurality of gate lines, each made of a conductive material, are etched together with the plurality of insulating layers, and the cell plug includes a blocking layer, a charge trap layer, a tunnel insulating layer, a channel layer, and a core pillar.Type: ApplicationFiled: August 5, 2022Publication date: September 14, 2023Applicant: SK hynix Inc.Inventors: Dae Hyun KIM, Sei Yon KIM
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Publication number: 20230290730Abstract: A package device and a manufacturing method thereof are provided. The package device includes a substrate, a plurality of conductive pillars, at least one bridge chip, a photosensitive encapsulation layer, a redistribution layer, and at least two active chips. The conductive pillars and the bridge chip are disposed on the substrate. The photosensitive encapsulation layer surrounds the bridge chip and the conductive pillars, in which a distance between a top surface of the bridge chip and a top surface of the photosensitive encapsulation layer is less than a distance between a top surface of one of the conductive pillars and the top surface of the photosensitive encapsulation layer. The redistribution layer is disposed on the photosensitive encapsulation layer, the active chips are disposed on the redistribution layer, and the bridge chip is coupled between the active chips.Type: ApplicationFiled: December 8, 2022Publication date: September 14, 2023Applicant: POWERTECH TECHNOLOGY INC.Inventors: Shang-Yu Chang Chien, Nan-Chun Lin, Hung-Hsin Hsu
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Publication number: 20230290731Abstract: A chip package including a first semiconductor die, a support structure and a second semiconductor die is provided. The first semiconductor die includes a first dielectric layer and a plurality of conductive vias, the first dielectric layer includes a first region and a second region, the conductive vias is embedded in the first region of the first dielectric layer; a plurality of conductive pillars is disposed on and electrically connected to the conductive vias. The second semiconductor die is stacked over the support structure and the second region of the first dielectric layer; and an insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the support structure and the conductive pillars, wherein the second semiconductor die is electrically connected to the first semiconductor die through the conductive pillars.Type: ApplicationFiled: May 19, 2023Publication date: September 14, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Lung Pan, Hao-Yi Tsai, Tin-Hao Kuo
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Publication number: 20230290732Abstract: A wafer assembly with alignment marks, a method for forming the wafer assembly and a wafer alignment method are disclosed. The alignment marks are disposed in bonding layers and dielectric layers on first and second wafers. Light reflected by a first dot mark and a first block mark on the first wafer, which are disposed in different layers, are superimposed with each other, ensuring clarity of patterns of these alignment marks. The first dot mark is disposed in a first bonding layer in such a manner that a top surface of the first dot mark is flush with a top surface of the first bonding layer. The first dot mark located on the bonding surface ensures that the bonding surface is macroscopically flat and does not leave any gap after bonding. Moreover, the first dot mark located on the bonding surface also avoids overlay errors between different layers. The same is applied to the second wafer.Type: ApplicationFiled: September 28, 2020Publication date: September 14, 2023Inventors: Guoliang YE, Xing HU, Hongsheng YI
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Publication number: 20230290733Abstract: A package structure includes a plurality of semiconductor die, an insulating encapsulant and a redistribution layer. Each of the plurality of semiconductor dies includes a semiconductor substrate, conductive pads disposed on the semiconductor substrate, conductive posts disposed on the conductive pads, and at least one alignment mark located on the semiconductor substrate. The insulating encapsulant is encapsulating the plurality of semiconductor dies. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the plurality of semiconductor dies.Type: ApplicationFiled: May 17, 2023Publication date: September 14, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jhih-Yu Wang, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Yung-Chi Chu
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Publication number: 20230290734Abstract: Provided is a semiconductor architecture including a carrier substrate, alignment marks provided in the carrier substrate, the alignment marks being provided from a first surface of the carrier substrate to a second surface of the carrier substrate, a first semiconductor device provided on the first surface of the carrier substrate based on the alignment marks, a second semiconductor device provided on the second surface of the carrier substrate based on the alignment marks and aligned with the first semiconductor device.Type: ApplicationFiled: May 18, 2023Publication date: September 14, 2023Applicant: SMSUNG ELECTRONICS CO., LTD.Inventors: Seok Won CHO, Ki-Il Kim, Kang Ill Seo
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Publication number: 20230290735Abstract: An Integrated Circuit (IC) package has a ferrite-dielectric shield between a planar inductor coil and a semiconductor chip. The shield blocks Electro-Magnetic Interference (EMI) generated by currents in the inductor coil from reaching the semiconductor chip. The shield has a ferrite layer surrounded by upper and lower dielectric laminate layers to prevent electrical shorts. The center end of the inductor coil connects to the semiconductor chip through a center post that fits through an opening in the shield that is over the air core center of the inductor coil. The center post can connect to a die attach pad that the semiconductor chip is mounted to. Bonding wires connect pads on the semiconductor chip to lead-frame pads on lead-frame risers that end at external package connectors. The outer end of the inductor coil connects to lead-frame outer risers also having external package connectors such as pins or bonding balls.Type: ApplicationFiled: March 14, 2022Publication date: September 14, 2023Inventors: Chik Wai (David) NG, Kwun Yuan (Godwin) HO, Ki Hin (Gary) CHOI, Tin Ho (Andy) WU, Wai Kit (Victor) SO
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Publication number: 20230290736Abstract: An Integrated Circuit (IC) package has a ferrite-dielectric shield between planar transformer coils and a semiconductor chip. The shield blocks Electro-Magnetic Interference (EMI) generated by currents in transformer coils from reaching the semiconductor chip. Multiple layers of planar transformer coils serve as primary or secondary coils and can be connected together in series or parallel using center posts and coil extensions from outer coil windings to lead-frame risers that also have external package connectors such as pins or bonding balls. The center winding of an upper transformer coil connects to the semiconductor chip on a die attach pad through a center post that fits through an opening in the shield that is over the air core center of the transformer coil. Bonding wires connect pads on the semiconductor chip to lead-frame pads on lead-frame risers that end at external package connectors.Type: ApplicationFiled: March 14, 2022Publication date: September 14, 2023Inventors: Chik Wai (David) NG, Kwun Yuan (Godwin) HO, Ki Hin (Gary) CHOI, Tin Ho (Andy) WU, Wai Kit (Victor) SO
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Publication number: 20230290737Abstract: A flip chip device includes a substrate, an integrated circuit device, a mold compound, and a via. The substrate has a top side and a bottom side. The integrated circuit device is affixed to the bottom side of the substrate. The mold compound is affixed to the bottom side of the substrate. The via is affixed to the bottom side of the substrate. The via passes through the mold compound and is exposed at a bottom side of the mold compound. The via is coupled to a terminal of the integrated circuit device.Type: ApplicationFiled: March 14, 2022Publication date: September 14, 2023Inventors: Antonius Hendrikus Jozef Kamphuis, Mustafa Acar, Philipp Franz Freidl, Rajesh Mandamparambil, Jan Willem Bergman
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Publication number: 20230290738Abstract: Semiconductor systems having anti-warpage frames (and associated systems, devices, and methods) are described herein. In one embodiment, a semiconductor system includes (a) a printed circuit board (PCB) having a first side and a second side opposite the first side, and (b) at least one memory device attached to the PCB at the first side of the PCB. The semiconductor system further includes a frame structure attached to the PCB at the first side of the PCB and proximate the at least one memory device. The frame structure can be configured to resist warpage of the PCB, for example, when the semiconductor system is heated to attach the at least one memory device to the PCB.Type: ApplicationFiled: March 9, 2022Publication date: September 14, 2023Inventors: Quang Nguyen, Christopher Glancey, Koustav Sinha
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Publication number: 20230290739Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers located one over another, the tiers including respective memory cells and control gates for the memory cells; a first pillar extending through the tiers and separated from the control gates, the first pillar including a first dielectric liner portion and a first core portion adjacent the first dielectric liner portion, the first dielectric liner portion and the first core portion extending along a length of the first pillar; and a second pillar extending through the tiers and separated from the control gates, the second pillar including a second dielectric liner portion and a second core portion adjacent the second dielectric liner portion, the second dielectric portion and the second core portion extending along a length of the second pillar, wherein the first core portion and the second core portion have different materials.Type: ApplicationFiled: March 14, 2022Publication date: September 14, 2023Inventors: Shuangqiang Luo, John Hopkins
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Publication number: 20230290740Abstract: The present invention relates to an anodized film substrate base made of an anodized oxide film, an anodized film substrate part including a vertical conductive part provided inside the anodized film substrate base, an anodized film-based interposer having same, and a semiconductor package having same.Type: ApplicationFiled: July 27, 2021Publication date: September 14, 2023Applicant: POINT ENGINEERING CO., LTD.Inventors: Bum Mo AHN, Seung Ho PARK, Sung Hyun BYUN
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Publication number: 20230290741Abstract: A semiconductor module includes: a wiring board including a ceramic substrate and conductor patterns on a first surface of the ceramic substrate; a semiconductor element arranged on at least one of the conductor patterns on the first surface of the ceramic substrate; a sealing insulator that seals the wiring board and the semiconductor element; and an insulating member disposed on the first surface of the ceramic substrate in a gap between the conductor patterns that are adjacent to each other, the insulating member extending in an extending direction of the gap and dividing an area in the gap where the sealing insulator fills the gap so that the insulating member is separate from respective edges of the conductor patterns adjacent to each other.Type: ApplicationFiled: February 2, 2023Publication date: September 14, 2023Applicant: Fuji Electric Co., Ltd.Inventor: Tomoyuki WAKIYAMA
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Publication number: 20230290742Abstract: A nitride epitaxial structure is provided, including: a substrate; a nucleation layer, formed on the substrate, where the nucleation layer is an aluminum nitride layer or a gallium nitride layer; a buffer layer, formed on the nucleation layer, including K stacked group-III nitride double-layer structures, K ? 3, each double-layer structure includes an upper layer and a lower layer that are stacked, a band gap difference of each double-layer structure is a difference between a band gap of a material of the upper layer and a band gap of a material of the lower layer, and band gap differences of the K double-layer structures generally present a gradient trend along a thickness direction of the buffer layer; and an epitaxial layer, formed on the buffer layer, where a material of the epitaxial layer includes group-III nitride. A semiconductor device is further provided, including the nitride epitaxial structure.Type: ApplicationFiled: March 24, 2023Publication date: September 14, 2023Applicant: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Zhibin Chen, Ruihong Luo
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Publication number: 20230290743Abstract: This application relates to the field of chip technologies, and provides a reinforcement structure and an electronic device. The reinforcement structure includes a support frame, an accommodation chamber, and an electromagnetic radiation suppression structure. The accommodation chamber is provided on the support frame and runs through a first surface and a second surface of the support frame that are opposite to each other. The accommodation chamber is used for accommodating a chip package structure disposed on a printed circuit board. A wall surface that is of the support frame and that defines the accommodation chamber is an inner surface, and a wall surface of the support frame opposite to the inner surface is an outer surface. The electromagnetic radiation suppression structure is disposed on at least one of the first surface, the second surface, the inner surface, and the outer surface.Type: ApplicationFiled: May 15, 2023Publication date: September 14, 2023Inventors: Zhenxing Xiong, Wangliang Liu, Zengqi Lan, Caijun Zhao, Xiang Xu
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Publication number: 20230290744Abstract: An electronic package is provided, including a package substrate in which a circuit layer and a surface treatment layer are embedded in an insulating portion, and the surface treatment layer is coupled to a top surface of the circuit layer, but is not formed on a side surface of the circuit layer. Therefore, the circuit layer can maintain the original predetermined line spacing so that it is beneficial to be designed with fine line spacing/line width.Type: ApplicationFiled: March 7, 2023Publication date: September 14, 2023Inventors: Min-Yao CHEN, Andrew C. CHANG
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Publication number: 20230290745Abstract: A semiconductor device includes a substrate and a metallization layer. The substrate has an active region that includes opposite first and second edges. The metallization layer is disposed above the substrate, and includes a pair of metal lines and a metal plate. The metal lines extend from an outer periphery of the active region into the active region and toward the second edge of the active region. The metal plate interconnects the metal lines and at least a portion of which is disposed at the outer periphery of the active region.Type: ApplicationFiled: May 18, 2023Publication date: September 14, 2023Inventor: Yi-Feng Chang
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Publication number: 20230290746Abstract: In one aspect, a capacitor or network of capacitors is/are provided for vertical power delivery in a package where the capacitor(s) is/are embedded in or forms the entirety of the package substrate core. In a second aspect, a plurality of thin-film capacitor structures are provided for implementing vertical power delivery in a package. In a third aspect a method is provided for fabricating hermetically sealed thin-film capacitors.Type: ApplicationFiled: March 11, 2022Publication date: September 14, 2023Inventors: Michael SU, Michael ALFANO, Siddharth RAVICHANDRAN
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Publication number: 20230290747Abstract: Embodiments provide metal features which dissipate heat generated from a laser drilling process for exposing dummy pads through a dielectric layer. Because the dummy pads are coupled to the metal features, the metal features act as a heat dissipation feature to pull heat from the dummy pad. As a result, reduction in heat is achieved at the dummy pad during the laser drilling process.Type: ApplicationFiled: May 27, 2022Publication date: September 14, 2023Inventors: Chien-Hung Chen, Cheng-Pu Chiu, Chien-Chen Li, Chien-Li Kuo, Ting-Ting Kuo, Li-Hsien Huang, Yao-Chun Chuang, Jun He
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Publication number: 20230290748Abstract: A semiconductor package includes a first wafer comprising a first substrate, a first device structure, and a first bonding layer having a pattern of first bonding pads. The first bonding layer is disposed over the first substrate and the first device structure. The semiconductor package includes a second wafer comprising a second substrate, a second device structure, and a second bonding layer having a pattern of second bonding pads. The second bonding layer is disposed over the first bonding layer. The second device structure is disposed over the second bonding layer. The second substrate is disposed over the second device structure. The first bonding pads are each aligned with a corresponding one of the second bonding pads. The first device structure is electrically coupled to the second device structure, through at least one of the first bonding pads and at least one of the second bonding pads.Type: ApplicationFiled: June 15, 2022Publication date: September 14, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Wen-Tuo Huang, Yu-Ling Hsu, Pai Chi Chou, Ya-Chi Hung
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Publication number: 20230290749Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip including a substrate having an upper surface vertically below a top surface. A dielectric structure contacts the top surface of the substrate. A conductive structure is disposed in the substrate. The conductive structure includes an upper conductive body and conductive protrusions directly underlying the upper conductive body. The upper conductive body overlies the upper surface of the substrate. A bottom surface of the dielectric structure is disposed between a top surface and a bottom surface of the upper conductive body. An isolation structure is disposed in the substrate on opposing sides of the upper conductive body.Type: ApplicationFiled: May 17, 2023Publication date: September 14, 2023Inventors: Sin-Yao Huang, Jeng-Shyan Lin, Shih-Pei Chou, Tzu-Hsuan Hsu
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Publication number: 20230290750Abstract: A method of manufacturing a high-frequency device includes mounting a first chip having a first pillar on an upper surface thereof on a metal base, forming an insulator layer covering the first chip on the metal base, exposing an upper surface of the first pillar from the insulator layer, and forming a first wiring connected to the first pillar on the insulator layer and transmitting a high-frequency signal.Type: ApplicationFiled: January 11, 2023Publication date: September 14, 2023Applicant: Sumitomo Electric Industries, Ltd.Inventor: Tatsuya HASHINAGA
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Publication number: 20230290751Abstract: The disclosure relates to a display device and an anisotropic conductive film. An anisotropic conductive film disposed between a display panel and a printed circuit board, the anisotropic conductive film including a base resin, a plurality of first conductive balls dispersed in the base resin, each of the plurality of first conductive balls including a core made of a polymer material and at least one metal layer surrounding the core, and a plurality of second conductive balls dispersed in the base resin, each of the plurality of second conductive balls being made of a meltable material, and the anisotropic conductive film having a first area in which the anisotropic conductive film overlaps the first pad electrode and the first lead electrode in a thickness direction of the display device, and a second area as an area disposed between the first lead electrode and the second lead electrode.Type: ApplicationFiled: February 1, 2023Publication date: September 14, 2023Applicant: Samsung Display Co., LTD.Inventor: Joo Nyung JANG
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Publication number: 20230290752Abstract: A semiconductor device includes a metal plate having a base portion and a terminal portion separated from the base portion, a resin layer provided between the base portion and the terminal portion and so as to surround the metal plate in a planar direction, and at which an upper and a lower surface of each of the base portion and the terminal portion are exposed, a semiconductor chip mounted on the base portion, a first electrically insulating layer provided on the metal plate and the resin layer so as to cover the semiconductor chip, and one or more wires provided on the first electrically insulating layer and including at least one wire configured to electrically connect the semiconductor chip and the terminal portion to each other.Type: ApplicationFiled: February 7, 2023Publication date: September 14, 2023Applicant: Sumitomo Electric Industries, Ltd.Inventors: Yutaka MORIYAMA, Tatsuya HASHINAGA
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Publication number: 20230290753Abstract: A distance between outermost parts of alignment chips in a direction normal to a surface of a substrate is different between a first direction and a second direction along terminal placement surfaces. The plurality of alignment chips include a first alignment chip fixed to a first metal pad, and a second alignment chip fixed to a second metal pad. The first alignment chip and the second alignment chip are oriented in different directions on the surface of the substrate. A semiconductor module includes a first side surface part extending in the second direction and facing the first alignment chip, and a groove part formed in a portion of the first side surface part. A portion of the second alignment chip is positioned in the groove part.Type: ApplicationFiled: August 23, 2022Publication date: September 14, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hideto FURUYAMA
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Publication number: 20230290754Abstract: Disclosed is a semiconductor package comprising a logic die mounted on an interposer substrate, and a memory stack structure disposed side-by-side with the logic die. The memory stack structure includes a buffer die mounted on the interposer substrate, and a plurality of memory dies stacked on the buffer die. The buffer die has a first surface that faces the interposer substrate and a second surface that faces the plurality of memory dies. The number of data terminals on the second surface is greater the number of connection terminals on the first surface.Type: ApplicationFiled: May 17, 2023Publication date: September 14, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sangkil LEE, So-young Kim, Soo-woong Ahn
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Publication number: 20230290755Abstract: In some embodiments, the present disclosure relates to method of forming an integrated circuit, including forming a semiconductor device on a frontside of a semiconductor substrate; depositing a dielectric layer over a backside of the semiconductor substrate; patterning the dielectric layer to form a first opening in the dielectric layer so that the first opening exposes a surface of the backside of the semiconductor substrate; depositing a glue layer having a first thickness over the first opening; filling the first opening with a first material to form a backside contact that is separated from the semiconductor substrate by the glue layer; and depositing more dielectric layers, bonding contacts, and bonding wire layers over the dielectric layer to form a second bonding structure on the backside of the semiconductor substrate, so that the backside contact is coupled to the bonding contacts and the bonding wire layers.Type: ApplicationFiled: May 17, 2023Publication date: September 14, 2023Inventors: Ping-Tzu Chen, Hsing-Chih Lin, Min-Feng Kao
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Publication number: 20230290756Abstract: A package structure of an embedded power module includes a top insulation layer, a top metal pattern layer, a solder layer, a device layer, a bottom metal pattern layer and a bottom insulation layer sequentially arranged from top to bottom. The device layer includes at least two MOSFET bare dies and several metal connection blocks, and is filled with insulation filler to isolate the MOSFET bare dies and the metal connection blocks from each other. The drain electrodes of the bare dies are connected with the top metal pattern layer through the solder layer, and the source electrodes and the gate electrodes of the bare dies are electrically connected to the bottom metal pattern layer, respectively. The upper and lower surfaces of the metal connection blocks are electrically connected to the top metal pattern layer and the bottom metal pattern layer, respectively.Type: ApplicationFiled: May 24, 2022Publication date: September 14, 2023Inventors: Xinnan Sun, Min Chen, Bodong Li, Xiaoqing Wang, Dongbo Zhang
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Publication number: 20230290757Abstract: A semiconductor device includes a substrate, a first chip, a second chip, a first connector, and a second connector. The substrate has a second thickness. The first chip includes a first surface facing the substrate, a second surface positioned at a side opposite to the first surface, a first electrode located at the first surface and electrically connected to the substrate, and a second electrode located at the second surface. The second connector includes a first part positioned above the second chip. A difference between the second thickness and a first thickness of the first part is not more than 20% of the greater of the first thickness or the second thickness.Type: ApplicationFiled: August 11, 2022Publication date: September 14, 2023Inventor: Tatsuya OHGURO
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Publication number: 20230290758Abstract: A light-emitting assembly with higher connection tolerances in manufacture includes a substrate, a light-emitting diode on the substrate, a transparent electrode, and a wire connected to the transparent electrode. The substrate includes a driving circuit connected to the light-emitting diode. The light-emitting diode includes a first electrode, a second electrode, and a light-emitting layer between the first electrode and the second electrode, the first electrode receiving the first driving signal. transparent electrode is connected to the second electrode. An orthographic projection area of the transparent electrode on the substrate is larger than an orthographic projection area of the second electrode on the substrate allowing less criticality in the alignment of signal wires for receiving the second driving signal. The light-emitting diode is configured to emit source light according to the first driving signal and the second driving signal.Type: ApplicationFiled: May 10, 2022Publication date: September 14, 2023Inventor: KUANG-HUA LIU
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Publication number: 20230290759Abstract: There is provided a full spectrum white light emitting device comprising: a broadband LED flip chip that generates broadband light of dominant wavelength from about 420 nm to about 480 nm and a FWHM from 25 nm to 50 nm; and at least one photoluminescence layer covering a light emitting face of the broadband LED flip chip; wherein the broadband LED flip chip comprises a broadband InGaN/GaN multiple quantum wells LED chip comprising multiple different wavelength quantum wells in its active region that generate multiple narrowband light emissions of multiple different wavelengths and wherein broadband light generated by the broadband LED flip chip is composed of a combination of the multiple narrowband light emissions, and wherein the at least one photoluminescence material layer comprises a first photoluminescence material which generates light with a peak emission wavelength from 490 nm to 550 nm; and a second photoluminescence material which generates light with a peak emission wavelength from 600 nm to 680 nType: ApplicationFiled: February 6, 2023Publication date: September 14, 2023Inventors: Yi-Qun Li, Xianglong Yuan, Jun-Gang Zhao
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Publication number: 20230290760Abstract: An electronic device includes a substrate, a spacer, a first element and a second element. A spacer is disposed on the substrate and has a first opening, a second opening and a third opening arranged in a first direction. The second opening is located between the first opening and the third opening. A distance between the first opening and the second opening is less than a distance between the second opening and the third opening in the first direction. A first element is located in at least one of the first opening and the second opening. A second element is located in the third opening.Type: ApplicationFiled: May 22, 2023Publication date: September 14, 2023Applicant: Innolux CorporationInventors: Jian-Jung Shih, Tsau-Hua Hsieh, Fang-Ying Lin, Kai Cheng
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Publication number: 20230290761Abstract: Some embodiments relate to a package. The package includes a first substrate, a second substrate, and an interposer frame between the first and second substrates. The first substrate has a first connection pad disposed on a first face thereof, and the second substrate has a second connection pad disposed on a second face thereof. The interposer frame is arranged between the first and second faces and generally separates the first substrate from the second substrate. The interposer frame includes a plurality of through substrate holes (TSHs) which pass entirely through the interposer frame. A TSH is aligned with the first and second connection pads, and solder extends through the TSH to electrically connect the first connection pad to the second connection pad.Type: ApplicationFiled: May 22, 2023Publication date: September 14, 2023Inventor: Jiun Yi Wu
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Publication number: 20230290762Abstract: This invention relates to non-interfering cartridge patterning for RGB pads. This disclosure is further related to arranging microdevices in the donor substrate by either patterning or population so that there is no interfering with non-receiving pads and the non-interfering area in the donor substrate is maximized. This enables the transfer of microdevices to a receiver substrate with fewer steps.Type: ApplicationFiled: April 14, 2021Publication date: September 14, 2023Applicant: VueReal Inc.Inventor: Gholamreza CHAJI
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Publication number: 20230290763Abstract: A hybrid-control pixel includes a TFT substrate, a TFT circuit formed on the TFT substrate, a micro-device having an integrated-circuit substrate separate and independent from the TFT substrate disposed on or over the TFT substrate, a micro-circuit electrically connected to the TFT circuit, and an LED or other device disposed on the integrated circuit or the TFT substrate. The LED can be electrically connected to the micro-circuit and the TFT circuit and the micro-circuit together control the LED.Type: ApplicationFiled: June 23, 2022Publication date: September 14, 2023Inventors: Matthew Alexander Meitl, Christopher Andrew Bower, Ronald S. Cok, Murat Ozbas
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Publication number: 20230290764Abstract: An electronic device is provided. The electronic device includes a circuit structure layer, a package structure, and an electronic element. The circuit structure layer includes a circuit layer and a plurality of first conductive pads. The package structure is disposed on the circuit structure layer. The electronic element is embedded in the package structure. The electronic element is electrically connected to the circuit layer through the plurality of first conductive pads. A thickness of the package structure is greater than or equal to 1.5 times a thickness of the electronic element.Type: ApplicationFiled: May 17, 2023Publication date: September 14, 2023Applicant: Innolux CorporationInventor: Yeong-E Chen
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Publication number: 20230290765Abstract: An apparatus having a substrate having first and second substrate contacts; a chip having a front-side chip contact and first and second back-side chip contacts, the front-side chip contact electrically connected to the first substrate contact; a chiplet having a chiplet contact electrically connected the first back-side chip contact; and a lead electrically connected to the second back-side chip contact and electrically connected to the second substrate contact.Type: ApplicationFiled: December 13, 2022Publication date: September 14, 2023Applicant: Microchip Technology IncorporatedInventors: Justin Sato, Bomy Chen, Julius Kovats, Anu Ramamurthy
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Publication number: 20230290766Abstract: An integrated circuit includes a first and second active region extending in a first direction, and a floating gate, a first dummy gate, a first conductor and a second conductor extending in the second direction. The floating gate is electrically floating. The first dummy gate is separated from the floating gate in the second direction. The dummy gate and the floating gate separate a first cell that corresponds to a first transistor from a second cell that corresponds to a second transistor. The first and second conductors are separated from each other in the first direction, and overlap the second active region. The first and second conductors are electrically coupled to a corresponding source/drain of the second active region, and are configured to supply a same signal/voltage to the corresponding source/drain of the second active region. The floating gate is between the first and second conductors.Type: ApplicationFiled: July 5, 2022Publication date: September 14, 2023Inventors: Chia Chun WU, Chih-Liang CHEN, Hui-Zhong ZHUANG, Jerry Chang Jui KAO, Yung-Chen CHIEN
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Publication number: 20230290767Abstract: A semiconductor device including a standard cell including active patterns extending in a first direction, gate patterns extending in a second direction perpendicular to the first direction, and contact patterns being on the active patterns at opposite sides of the gate patterns, and interconnection line patterns extending in the first direction and spaced apart from each other in the second direction, on the stand cell may be provided. The standard cell may include first and second standard cells that partially overlap each other. A first special boundary may be defined on a cell boundary of the second standard cell in the first standard cell, and a second special boundary may be defined on a cell boundary of the first standard cell in the second standard cell. At least one of the interconnection line patterns of the first standard cell may be spaced apart from the first special boundary.Type: ApplicationFiled: November 2, 2022Publication date: September 14, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Jaeha LEE, Hyeongkyu Kim
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Publication number: 20230290768Abstract: An integrated circuit device includes a substrate having a first intellectual property (IP) core including a cell region and a first edge dummy region, fin-type active regions protruding from the cell region, dummy fin-type active regions protruding from the first edge dummy region, gate lines extending, over the cell region of the substrate, the gate lines including two adjacent gate lines spaced apart from each other with a first pitch and two adjacent gate lines spaced apart with a second pitch greater than the first pitch, dummy gate lines over the first edge dummy region of the substrate and equally spaced apart from each other with the first pitch.Type: ApplicationFiled: May 9, 2023Publication date: September 14, 2023Inventors: Jina Lee, Hyungjoo Youn
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Publication number: 20230290769Abstract: A semiconductor device includes: a core region of core circuitry over a substrate; an input/output (I/O) region of interfacing circuitry over a substrate and coupled to the core region; a sealing ring having first, second and third sides, the sealing ring surrounding, and being isolated from, the core region and the I/O region; an intra-communication (intra-com) stack including intra-com segments in corresponding metallization layers which are stacked, the intra-com segments correspondingly extending between, and thereby coupling, the core region and the I/O region; and a first parapet on the intra-com stack and which extends from the first side to the third side of the sealing ring the first parapet being between, and isolated from each of, the core region and the I/O region.Type: ApplicationFiled: May 17, 2023Publication date: September 14, 2023Inventor: Liang-Chen LIN
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Publication number: 20230290770Abstract: An ESD protection circuit includes a terminal connected to the cathode of a first diode and to the anode of a second diode, where the cathode of the second diode is not made of epitaxial silicon.Type: ApplicationFiled: November 2, 2022Publication date: September 14, 2023Applicants: STMicroelectronics (Tours) SAS, STMicroelectronics S.r.l.Inventors: Aurelie Arnaud, Andrea Brischetto