Abstract: Encoding/decoding an audio signal having one or more audio components, wherein each audio component is associated with a spatial location. A first audio signal presentation (z) of the audio components, a first set of transform parameters (w(f)), and signal level data (?2) are encoded and transmitted to the decoder. The decoder uses the first set of transform parameters (w(f)) to form a reconstructed simulation input signal intended for an acoustic environment simulation, and applies a signal level modification (?) to the reconstructed simulation input signal. The signal level modification is based on the signal level data (?2) and data (p2) related to the acoustic environment simulation. The attenuated reconstructed simulation input signal is then processed in an acoustic environment simulator. With this process, the decoder does not need to determine the signal level of the simulation input signal, thereby reducing processing load.

Abstract: A method for applying a watermark signal to a speech signal to prevent unauthorized use of speech signals, the method may include receiving an original speech signal; determining a corresponding spectrogram of the original speech signal; selecting a phase sequence of fixed frame length and uniform distribution; and generating an encoded watermark signal based on the corresponding spectrogram and phase sequence.

Abstract: The present invention relates to a method of triggering an event. The method includes receiving a signal stream, detecting a trigger point within the signal stream using a fingerprint associated with the trigger point and triggering an event associated with the detected trigger point.

Abstract: An audio data processing method is provided. The method includes: obtaining human voice audio data to be adjusted and reference human voice audio data; performing framing on the human voice audio data to be adjusted and the reference human voice audio data respectively so as to obtain a first audio frame set and a second audio frame set respectively; recognizing a pronunciation unit corresponding to each audio frame respectively; determining, based on a timestamp of each audio frame, a timestamp of each pronunciation unit in the human voice audio data to be adjusted and the reference human voice audio data respectively; and adjusting the timestamp of at least one pronunciation unit to make the timestamp of the pronunciation unit in the human voice audio data to be adjusted to be consistent with the timestamp of the corresponding pronunciation unit in the reference human voice audio data.

Abstract: A sound signal processing method, an electronic device, and computer-readable medium are provided. The method includes: importing first frequency spectrum data corresponding to first audio data into a pre-trained sound processing model to obtain a processing result; and generating, based on the processing result, pure audio data corresponding to the first audio data. The sound processing model includes at least one preset convolution layer, and operations performed by using the preset convolution layer includes: performing, based on a first convolution kernel group, a convolution operation on a first sound spectrum feature map inputted into the preset convolution layer, to obtain a second sound spectrum feature map; and combining, based on a second convolution kernel group, the obtained second sound spectrum feature map, to obtain a third sound spectrum feature map corresponding to the second convolution kernel group.

Abstract: A sound source signal generation technology based on an optimization algorithm that enables high-speed processing of sound source extraction is provided. A sound source signal generation device includes an optimization unit that optimizes a separation matrix W(f)=[w1(f), . . . , wK(f), WZ(f)] using an observed signal x(f, t), the optimization unit includes an auxiliary function calculation unit that calculates an auxiliary function Vi(f) (i=1, . . . , K) according to a predetermined equation, a first separation filter calculation unit that calculates a separation filters wi(f) (i=1, . . . , K) using auxiliary functions Vi(f) (i=1, . . . , K) and Vz(f), and a second separation filter calculation unit that calculates a separation filter WZ(f) according to a predetermined equation when a convergence condition is satisfied.

Abstract: A signal processing device includes processing circuitry configured to receive an input of extraction target information indicating which audio class of an audio signal is to be extracted from a mixture audio signal constituted by a mixture of audio signals of a plurality of audio classes, and output a result of extracting the audio signal of the audio class indicated by the extraction target information from the mixture audio signal, with a neural network by using a feature value of the mixture audio signal and the extraction target information.

Abstract: A speaker vector extraction unit (15b) extracts a speaker vector representing a speaker feature of each frame using a sequence of acoustic features for each frame of a latest acoustic signal. A learning unit (15d) generates an online EEND model (14a) for estimating a speaker label of the speaker vector of each frame through learning using the speaker vector and a speaker label representing a speaker of the estimated speaker vector.

Abstract: Some implementations of the disclosure relate to a non-transitory computer-readable medium having executable instructions stored thereon that, when executed by a processor, cause a system to perform operations comprising: obtaining a first energy-based target for audio; obtaining a first version of a sound mix including one or more audio components; computing, for each audio frame of multiple audio frames of each of the one or more audio components, a first audio feature measurement value; optimizing, based at least on the first energy-based target and the first audio feature measurement values, gain values of the audio frames; and after optimizing the gain values, applying the gain values to the first version of sound mix to obtain a second version of the sound mix.

Abstract: A voice activity detection method and system and a voice enhancement method and system are provided. A voice presence probability of a target voice signal present in microphone signals may be determined by calculating a linear correlation between a signal subspace where the microphone signals are located and a target subspace where the target voice signal is located. The voice enhancement method and system may be used to calculate filter coefficients based on the voice presence probability, so as to perform voice enhancement on the microphone signals. The calculation accuracy of the voice presence probability is improved, and the voice enhancement effect is also improved.

Abstract: A method of audio content identification includes using a two-stage classifier. The first stage includes previously-existing classifiers and the second stage includes a new classifier. The outputs of the first and second stages calculated over different time periods are combined to generate a steering signal. The final classification results from a combination of the steering signal and the outputs of the first and second stages. In this manner, a new classifier may be added without disrupting existing classifiers.

Abstract: In at least one embodiment, a record or vinyl playback device includes a spindle clamp at a central region of the playback device and a peripheral clamp at a peripheral region of the playback device. In operation, the spindle clamp is inserted into an opening at a center of a record to be played utilizing the playback device. Once the record is present on the playback device, the spindle clamp is actuated to mechanically engage one or more spindle clamp arms with a central region or surface of the record, and the peripheral clamp is actuated to mechanically engage one or more clamp structures with a peripheral region or surface of the record. The spindle clamp arms may rotate inward and outward from a shaft of the spindle clamp, and the clamp structures may translate inward and outward from a center of the record.

Abstract: Various illustrative aspects are directed to a data storage device comprising a disk; a read/write head having read and write portions configured to read data from and write data to the disk; read and write heaters configured to thermally adjust read and write spacings of the read and write portions from the disk surface; and a controller configured to control power applied to the read and write heaters based on a dual heater power ratio (DHR) of the respective power applied to each heater. The DHR is set based on a point during touchdown at which a reader shield and a writer shield have maximum contact with the surface of the disk (DHRmax).

Abstract: The present disclosure discloses a magnetic head, a head gimbal assembly, a hard disk drive, and a method for processing a magnetic head. The method comprises irradiating at a fixed point proximal to the read/write part with a laser irradiation device until the read head and the write head are thermally expanded; orientating air bearing surfaces of a plurality of magnetic heads forming a magnetic strip toward a lapping surface of a lapping device after laser irradiation, holding the air bearing surfaces in place, lapping with the lapping device until the air bearing surfaces are coplanar; and disassembling the magnetic strip to obtain a lapped magnetic head. Through laser heating induced compensation, the heights of lapped read head and write head of the magnetic head meet their respective target values, ensuring the normal reading and writing of the storage medium of the magnetic disk.

Abstract: A multi-actuator hard disk drive includes a lower actuator with a corresponding voice coil motor assembly (VCMA) including a magnet coupled with a first magnet housing plate, a coaxial upper actuator with a corresponding VCMA including a magnet coupled with a second magnet housing plate, and a central support plate mechanically fastened to an enclosure base, at one or more locations, and positioned between the first magnet housing plate of the first VCMA and the second magnet housing plate of the second VCMA. Thereby, the pivot and VCM tilt and the coil torsion modes of the direct plant transfer function are minimized and the peak-to-peak gain in the coil torsion mode of the coupled plant transfer function is reduced.

Abstract: An embodiment method includes rectifying a back electromotive force of a spindle motor in a hard disk drive and energizing a voice coil motor in the hard disk drive using the rectified back electromotive force of the spindle motor via a voice coil motor power stage to retract a head of the hard disk drive to a park position. The head is retracted by moving the head towards the park position during a first retract phase and retaining the head in the park position during a second retract phase by applying a bias voltage to the voice coil motor power stage during a bias interval of the second retract phase. The method also includes producing a saturation signal indicative of onset of saturation in the voice coil motor power stage and controlling the bias voltage during the second retract phase.

Abstract: An optical memory includes a support and nanoparticles, each of which changes between a crystal phase and an amorphous phase when irradiated with light. The nanoparticles are supported by the support and spaced apart from each other in one or both of an in-plane direction of a face of the support and a direction normal to the face of the support.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a lower electrode disposed within a dielectric structure over a substrate. A ferroelectric data storage structure is disposed over the lower electrode and an upper electrode is disposed over the ferroelectric data storage structure. One or more stressed sidewall spacers are arranged on opposing sides of the upper electrode. The ferroelectric data storage structure has an orthorhombic phase concentration that varies from directly below the one or more stressed sidewall spacers to laterally outside of the one or more stressed sidewall spacers.

Abstract: A device and method are presently disclosed. The computer implemented method, includes at an electronic device with a touch-sensitive display, displaying a still image on the touch-sensitive display, while displaying the still image, detecting user's finger contact with the touch-sensitive display, and in response to detecting the user's finger contact, video recording the still image.

Abstract: According to one embodiment, a magnetic disk device including a disk, a head which writes data to the disk and reads data from the disk, and a controller which sets a first DOL for a first sector group and a second DOL for a second sector group to different values, the first sector group including one or more first sectors and a first parity sector, the first sectors which allow an error correction process to be performed for each track based on the first parity sector, and are continuously arranged in a circumferential direction of the disk from the first parity sector, the second sector group including one or more second sectors which allow no error correction process to be performed for each track, and are continuously arranged in the circumferential direction.

Abstract: A circuit includes a set of input nodes configured to be coupled to respective ones of the windings of a spindle motor in a hard disk drive to sense the voltages applied to the windings. A set of output nodes is configured to provide output signals indicative of direction of flow of the currents through the windings. Level shifters are coupled to respective input nodes in the set of input nodes and have level-shifted output nodes configured to provide down-shifted replicas of the voltages at the respective input nodes in the set of input nodes. Flip-flops have inputs coupled to respective ones of the level-shifted output nodes of the level shifters and outputs configured to provide the output signals coupled to respective output nodes.

Abstract: A magnetic tape cartridge includes a magnetic tape wound around a reel, in which the magnetic tape has a first region, which is a predetermined region influenced by a width change of the magnetic tape accompanied by deformation of the reel due to winding of the magnetic tape, and a second region, which is a region on an outer peripheral side of the reel with respect to the first region, and regarding a degree of elongation in a longitudinal direction of the magnetic tape, the degree of the first region is equal to or larger than the degree of the second region.

Abstract: A video search apparatus 100 according to the present disclosure includes a search unit 121 configured to use scene information including event information including a plurality of events constituting a video scene and time information indicating a time set for the video scene to set a search range of an event in a target video image based on the time information and also search for the event included in the event information from the target video image within the set search range, and a determination unit 122 configured to determine a video section in the target video image that corresponds to the scene information targeted for the search based on a result of the search for the event.

Abstract: One or more computing devices, systems, and/or methods for generating a video in a target language are provided. In an example, a first video, in which a first speaker speaks in a first language, is identified. A translated transcript in a second language is determined. The translated transcript is indicative of a translation of speech spoken by the first speaker in the first video. Based upon the translated transcript and a speaker profile associated with a second speaker, first audio, including an auditory representation of the translated transcript being spoken in a voice of the second speaker, is generated. Based upon the first video and the first audio, a second video, in which mouth movements of the first speaker are aligned with speech of the auditory representation of the first audio, is generated.

Abstract: In some aspects, techniques may include receiving media streams from one or more client devices. The media streams can be received by a virtual conference provider. Also, the techniques may include selecting a subset of the media streams based on one or more characteristics of the media streams. The streams may be selected using a machine learning (ML) model. In addition, the techniques may include identifying one or more segments of the subset of media streams satisfying an inclusion criteria. Moreover, the techniques may include generating a recording of the virtual conference including the one or more identified segments.

Abstract: Provided are a video generation method and apparatus, an electronic device and a storage medium. The method includes: receiving a triggering operation acting on a video capturing interface and capturing an original video in response to the triggering operation; determining a video segment of interest in the original video; and performing video synthesis processing based on the video segment of interest and the original video to obtain a target video.

Abstract: A method for processing media content includes aggregating, by at least one hardware processor, a plurality of three-dimensional (3D) images to obtain a 3D volume representation of a plurality of two-dimensional (2D) images of media content. A 3D void space associated with the plurality of 2D images is segmented based on the 3D volume representation into a plurality of 3D void segments. A media element is inserted into at least one 3D void segment of the plurality of 3D void segments. At least one 2D image of the plurality of 2D images is modified to include the at least one 3D void segment.

Abstract: At a high level, embodiments of the invention relate to augmenting video data with presence data derived from one or more proximity tags. More specifically, embodiments of the invention generate forensically authenticated recordings linking video imagery to the presence of specific objects in or near the recording. One embodiment of the invention includes video recording system comprising a camera, a wireless proximity tag reader, a storage memory and control circuitry operable to receive image data from the camera receive a proximity tag identifier identifying a proximity tag from the proximity tag reader, and store an encoded frame containing the image data and the proximity tag identity in the storage memory.

Abstract: A video may have a video progress length. The video progress length of the video may be represented within a graphical user interface. One or more segments of the video progress length may be used to generate a video edit having a video edit progress length. The graphical user interface may be modified to represent the video edit progress length. The graphical user interface may simultaneously present elements that represent the video progress length of the video and the video edit progress length of the video edit.

Abstract: A plurality of video clips comprising audio of a song are identified from a pool of videos. A portion of the song corresponding to the audio in each video clip is then determined. Using the determined portion, each video clip is mapped to a timeline of the song. A subset of video clips comprising different sections of the song are then selected. Video clips comprising audio from different sections of the song are selected to be included in the personalized video, which is then generated from the selected subset of video clips. The personalized video is then generated for display to the user.

Abstract: A method and device for timing alignment of audio signals. The method includes: generating frequency domain images respectively for an audio signal to be aligned and a template audio signal (S110); inputting the frequency domain images into a twin neural network of a timing offset prediction model respectively, to obtain two frequency domain features output by the twin neural network (S120); fusing the two frequency domain features to obtain a fused feature (S130); inputting the fused features into a prediction network of the timing offset prediction model to obtain a timing offset output by the prediction network (S140); and performing timing alignment processing on the audio signal to be aligned according to the timing offset (S150). The technical solution is more robust, and especially in a noisy environment, features extracted by a deep neural network are more intrinsic and more stable. An end-to-end timing offset prediction model is more accurate and faster.

Abstract: According to one embodiment, in a semiconductor memory device, multiple first memory cells are connected in parallel between a first local bit line and a local source line. Multiple second memory cells are connected in parallel between a second local bit line and the local source line. Each of the multiple first memory cells includes a first cell transistor and a first resistance change element connected in series. Each of the multiple second memory cells includes a second cell transistor and a second resistance change element connected in series. A first selection gate line extends in a second direction across multiple cell blocks arranged in the second direction. A second selection gate line is placed on the opposite side of the first selection gate line with the local source line interposed therebetween. The second selection gate line extends in the second direction across multiple cell blocks arranged in the second direction.

Abstract: A semiconductor memory device comprises: memory layers arranged in a first direction; and a first wiring extending in the first direction. The memory layers each comprise: a memory portion; a transistor; and a second wiring. The transistor comprises: a semiconductor layer electrically connected between the memory portion and the first wiring; a gate electrode facing the semiconductor layer and electrically connected to the second wiring; and a gate insulating film provided between the semiconductor layer and the gate electrode. The semiconductor layer faces surfaces of the gate electrode on one side and the other side in the first direction. In a cross section perpendicular to the first direction and including a part of the transistor corresponding to one of the memory layers, the first wiring comprises: a first surface in contact with the transistor; and a second surface not in contact with the transistor.

Abstract: A sense amplifier including a first input transistor having a first input gate and a first drain/source terminal, a second input transistor having a second input gate and a second drain/source terminal, a latch circuit, and a first capacitor. The latch circuit includes a first latch transistor having a third drain/source terminal connected to the first drain/source terminal and a second latch transistor having a fourth drain/source terminal connected to the second drain/source terminal. The first capacitor is connected on one side to the first input gate and on another side to the fourth drain/source terminal to reduce a coupling effect in the sense amplifier.

Abstract: A pulse generator, an Error Check and Scrub (ECS) circuit and a memory are provided. The pulse generator includes: a delay circuit configured to receive an ECS command signal, perform delay processing on the ECS command signal, and output a delay command signal, the delay between the ECS command signal and the delay command signal being a first preset value; and a latch circuit configured to receive the ECS command signal and the delay command signal, perform latch processing based on the ECS command signal and the delay command signal, and output an ECS pulse signal. The pulse width of the ECS command signal is provided with a plurality of values, and the pulse width of the ECS pulse signal is the first preset value.

Abstract: Embodiments of the disclosure provide a circuit structure and related method to compensate for sense amplifier leakage. A circuit structure according to the disclosure includes a reference voltage generator coupling a supply voltage and a reference line to a sense amplifier. A multiplexer within the reference voltage generator is coupled to the reference line. The multiplexer includes a plurality of transistors each having a gate terminal coupled to ground.

Abstract: Methods, systems, and devices for memory row-hammer mitigation are described. A memory device may operate based on a scheme that is continuous across power cycles. For example, the memory device may access a region if a value of a counter does not satisfy a threshold value and may access the region if a value of the counter satisfies the threshold value. Upon transitioning power states, the value of the counter may be stored to a non-volatile memory such that it may be accessed when transitioning back to the original power state (e.g., an “ON” state). Accordingly, the value of the counter may be maintained across power cycles.

Abstract: A semiconductor device may include: a first substrate structure including: a first substrate; a first word line, a first bit line, a second bit line, a second word line, a third word line, a third bit line, a fourth bit line, and a fourth word line that are sequentially arranged over the first substrate in a vertical direction; and first, second, third, and fourth memory cells, the first memory cell being disposed between the first word line and the first bit line, the second memory cell being disposed between the second word line and the second bit line, the third memory cell being disposed between the third word line and the third bit line, and the fourth memory cell being disposed between the fourth word line and the fourth bit line; and a second substrate structure disposed over the first substrate structure and including a second substrate.

Abstract: A leakage current of a MOS transistor that performs writing is reduced. The resistance change memory includes a memory cell, a write drive unit, a write control unit, and a well potential adjustment unit. The memory cell includes a resistance change element. The write drive unit applies a write voltage to the memory cell to perform writing of data. The write control unit outputs a write control signal for controlling the writing to the write drive unit. The well potential adjustment unit adjusts a well potential of a well region in which an element constituting the write drive unit is arranged according to the write voltage at time of the writing.

Abstract: A metallic ferroelectric metal (MFM) field effect transistor (FET) is disclosed. The metallic ferroelectric metal (MFM) field effect transistor (FET) includes an MFM, a first FET and a second FET. The MFM has a first electrode. The first FET is electrically connected to the first electrode, and has a first gate electrode, wherein the first gate electrode has a first area. The second FET is electrically connected to the first electrode, and has a second gate electrode, wherein the second gate electrode has a second area, and the first area and the second area have a ratio therebetween ranging from 1:50 to 1:2.

Abstract: In a memory device, a control circuit detects determines an aggressor row address, indicating an aggressor row of a memory cell array, at a random time. The aggressor row address or a value derived from the aggressor row address is stored in a queue. The control circuit controls a refresh operation of one or more victim rows based on the aggressor row address in response to a targeted refresh command.

Abstract: A clock generator circuit may generate internal data clock signals, such as quadrature phase clock signals, based at least in part, on one clock signal responsive, at least in part, to another clock signal. In some examples, the internal data clock signals may be generated from a system clock signal responsive to a data clock signal. In some examples, the internal data clock signal may be generated by sampling the system clock signal. In some examples, the sampling may be performed responsive to the data clock signal. In some examples, a latch may latch a state of the system clock signal responsive to the data clock signal. The latch may output the internal data clock signal.

Abstract: Memory with partial array density security is disclosed herein. In one embodiment, an apparatus comprises a memory region including a plurality of memory rows, a plurality of memory columns, and a plurality of memory cells arranged at intersections of the plurality of memory rows and the plurality of memory columns. The plurality of memory rows includes a plurality of enabled memory rows and a plurality of disabled memory rows. Sets of one or more disabled memory rows are interleaved with enabled memory rows within the memory region. To write data to or read data from the memory region, the apparatus can be configured to access only the enabled memory rows of the memory region. The apparatus may further be configured to refresh disabled memory rows of the memory region according to a different refresh protocol from a refresh protocol used to refresh the enabled memory rows of the memory region.

Abstract: An apparatus can include a number of memory devices and a controller coupled to one or more of the number of memory devices. The controller can be configured to determine whether a quantity of row activations directed to a row of the memory devices exceeds a row hammer criterion. The controller can be configured to select, responsive to determining that the row hammer criterion is met, a row hammer mitigation response from a plurality of row hammer mitigation responses available for initiation. The controller can be configured to initiate the selected row hammer mitigation response.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a control logic circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data based on an active command applied to the control logic circuit at a first time point, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row in response to a precharge command applied at a second time point after a first command that is applied to the control logic circuit.

Abstract: Method and circuit for adaptive column-select line signal generation for a memory device are provided. The method comprises the following steps. A first signal is generated in response to a memory access command. A second signal is generated according to a candidate signal selected from a plurality of candidate signals including a first candidate signal and a second candidate signal, wherein after the first signal is asserted, the first candidate signal is asserted when a configurable time interval with respect to a parameter from a register set elapses and the second candidate signal is asserted when a specified time interval elapses, and the selected candidate signal is asserted before a remaining part of the candidate signals after the first signal is asserted. A column-select line signal is generated according to the first signal and the second signal.

Abstract: Disclosed herein are related to a memory device. In one aspect, the memory device includes a memory array including a set of memory cells. In one aspect, each of the set of memory cells includes a corresponding transistor and a corresponding capacitor connected in series between a bit line and a select line. In one aspect, the memory device includes a first transistor including a source/drain electrode coupled to a controller and another source/drain electrode coupled to the bit line. In one aspect, the memory device includes a second transistor including a gate electrode coupled to the bit line. In one aspect, the second transistor is configured to conduct current corresponding to data stored by a memory cell of the set of memory cells.

Abstract: A semiconductor package includes a memory die stack having a clock signal shared by lower and upper bytes. Each of a plurality of memory dies constituting the memory die stack of the semiconductor package includes a first clock circuit configured to generate a read clock signal for a lower byte and an upper byte constituting a data width of the memory die, and a plurality of first die bond pads corresponding to the number of ranks of a memory system including the memory die, and each of the plurality of first die bond pads is set for each rank. The first clock circuit is connected to, among the plurality of first die bond pads, a die bond pad corresponding to a rank to which the memory die belongs.

Abstract: A memory device is provided, including a first word line coupled to a first memory cell, a second word line coupled to a second memory cell, and a read assist circuit coupled between the first and second word lines, and in a first time period configured, in response to a first control signal, to adjust a voltage level of the first word line to a first voltage and to adjust a voltage level of the second word line to a second voltage. In some embodiments, the first voltage is smaller than a first supply voltage, and the second voltage is greater than a second supply voltage smaller than the first supply voltage.

Abstract: Various implementations described herein are related to a device having bitline drivers coupled to passgates of bitcells via bitlines and buried metal lines formed within a substrate including a buried enable signal line and a buried ground line coupled to ground connections of the bitline drivers. The buried enable signal line transfers a negative bias to a selected bitline of the bitlines via the buried ground line that is coupled to the ground connections of the bitline drivers so as to increase gate-source bias of the passgates of the selected bitcell to thereby enhance write capability of the selected bitcell.