Abstract: A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method of the semiconductor structure includes: providing a substrate; forming on an upper surface of the substrate first patterns each including a first main body and a first flank wall covering a sidewall of the first main body; forming a filling layer which covers the first flank wall and fills a gap between adjacent first patterns; and etching a top of each of the first patterns to obtain second main bodies, second flank walls and protrusions located on upper surfaces of the second flank walls, the second flank wall covering a sidewall of the second main body, and a top of the protrusion being at least higher than a top of the second main body.

Abstract: The present disclosure relates to a memory structure and a forming method thereof. The present disclosure can improve the integration density of the memory structure. The memory structure includes: a plurality of vertical transistors, where the vertical transistors include silicon pillars; a plurality of the silicon pillars are arranged in m rows and n columns; the rows extend in a first direction and the columns extend in a second direction; m bit lines extending in the first direction and electrically connected to drains of all the vertical transistors in the same row, where the drains are located below the silicon pillars; and n word lines extending in the second direction, located in the middle of the silicon pillars, and serving as gates of all the vertical transistors in the same column, where the first direction and the second direction form a non-right angle.

Abstract: A semiconductor device and a manufacturing method are provided. The semiconductor device includes an active region, a bit line, a capacitor contact, a conductive ring and a storage capacitor. The active region is formed in a substrate. The bit line and the capacitor contact are disposed over the substrate and electrically connected with the active region. The bit line is laterally separated from the capacitor contact, and a top surface of the bit line is lower than a top surface of the capacitor contact. An upper portion of the capacitor contact is surrounded by the conductive ring. The storage capacitor is disposed over and in electrical contact with the capacitor contact and the conductive ring.

Abstract: A programmable array including a plurality cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, wherein the transistor includes a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region. A method of forming an integrated circuit including forming transistor bodies in a plurality rows on a substrate; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material to define a width dimension of the transistor bodies; after etching the bodies, patterning each of the plurality of rows of the masking material into a plurality of individual masking units; and replacing each of the plurality of individual masking units with a programmable element.

Abstract: A semiconductor device includes an insulating base including a trench, a transistor including a gate electrode and vertical channel in the trench, and a source electrode in the insulating base outside the trench, an isolation layer on the gate electrode in the trench, and a capacitor including a trench capacitor portion that is on the isolation layer in the trench, and a stacked capacitor portion that is coupled to the source electrode of the transistor outside the trench.

Abstract: A method for preparing a semiconductor device structure includes forming a first fin structure and a second fin structure over a semiconductor substrate, forming an isolation structure over the semiconductor substrate, partially removing the first fin structure and the second fin structure to form a recessed portion of the first fin structure and a recessed portion of the second fin structure, epitaxially growing a first source/drain (S/D) structure over the recessed portion of the first fin structure and a second S/D structure over the recessed portion of the second fin structure, partially removing the isolation structure through the first opening to form a second opening, and forming a contact etch stop layer (CESL) over the first S/D structure and the second S/D structure such that an air gap is formed and sealed in the first opening and the second opening.

Abstract: A vertical-type nonvolatile memory device has a multi-stack structure with reduced susceptibility to mis-alignment of a vertical channel layer. This nonvolatile memory device includes: (i) a main chip area including a cell area and an extension area arranged to have a stepped structure, with the cell area and the extension area formed in a multi-stack structure, and (ii) an outer chip area, which surrounds the main chip area and includes a step key therein. The main chip area includes a first layer on a substrate and a second layer on the first layer. A lower vertical channel layer is arranged in the first layer. The step key includes an alignment vertical channel layer, and a top surface of the alignment vertical channel layer is lower than a top surface of the lower vertical channel layer.

Abstract: A semiconductor device and a method of fabricating the same are provided. According to the present invention, a semiconductor device comprises an active region formed in a substrate, and including flat surfaces and hole-shaped recess portions; upper-level plugs disposed over the flat surfaces; a spacer disposed between the upper-level plugs and providing a trench exposing the hole-shaped recess portions; a lower-level plug filling the hole-shaped recess portions; and a buried conductive line disposed over the lower-level plug and partially filling the trench.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a substrate; forming a bit line structure over the substrate; forming a spacer surrounding the bit line structure; forming a polysilicon layer covering the bit line structure and the spacer; performing a first etching operation on the polysilicon layer to obtain a first height of the polysilicon layer, wherein the first height is less than a height of the bit line structure or a height of the spacer; performing a second etching operation on a first portion of the spacer; and performing a third etching operation on the polysilicon layer to obtain a second height of the polysilicon layer, wherein the second height is less than the first height.

Abstract: The present disclosure provides a method for manufacturing a semiconductor device having a buried wordline. The method includes forming a first recessed portion in a first dielectric layer in a substrate; forming a second recessed portion spaced apart from the first recessed portion and in the substrate; disposing a protection layer on the substrate to cover the second recessed portion; and disposing a second dielectric layer on the first dielectric layer.

Abstract: A manufacturing method for memory includes: providing a substrate, and forming a first isolation layer and discrete bit lines on the substrate; removing part of the first isolation layer by a thickness to form discrete first trenches; forming word lines filling the first trenches, wherein the word lines each has a first side wall and a second side wall opposite to each other; forming discrete through holes each being between adjacent word lines; forming a first dielectric layer on surface of exposed first side wall, and forming a second dielectric layer on surface of exposed second side wall; and forming an active layer filling the through holes.

Abstract: A memory integrated circuit is provided. The memory integrated circuit includes a first memory array, a second memory array and a driving circuit. The first and second memory arrays are laterally spaced apart, and respectively include: memory cells, each including an access transistor and a storage capacitor coupled to the access transistor; bit lines, respectively coupled to a row of the memory cells; and word lines, respectively coupled to a column of the memory cells. The driving circuit is disposed below the first and second memory arrays, and includes sense amplifiers. Each of the bit lines in the first memory array and one of the bit lines in the second memory array are routed to input lines of one of the sense amplifiers.

Abstract: A semiconductor memory device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region, the boundary element isolation layer being in a boundary element isolation recess and including first and second boundary liner layers extending along a profile of the boundary element isolation recess and a first gate structure on the core region and at least a part of the boundary element isolation layer, wherein the first gate structure includes a first high dielectric layer, and a first gate insulating pattern below the first high dielectric layer, with a top surface of the substrate being a base reference level, the first gate insulating pattern does not overlap a top surface of the first boundary liner layer, and wherein the first gate insulating pattern includes a first_1 gate insulating pattern between a top surface of the second boundary liner layer and a bottom surface of the first high

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are between immediately-laterally-adjacent of the memory blocks. Conductor material is in and extends elevationally along sidewalls of the trenches laterally-over the conductive tiers and the insulative tiers and directly electrically couples together conducting material of individual of the conductive tiers. The conductor material is exposed to oxidizing conditions to form an insulative oxide laterally-through the conductor material laterally-over individual of the insulative tiers to separate the conducting material of the individual conductive tiers from being directly electrically coupled together by the conductor material. Additional embodiments are disclosed.

Abstract: Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an tipper portion and a lower portion. The upper portion comprises vertically alternating first tiers and second insulating tiers that are of different composition relative one another. The lower portion comprises an upper polysilicon-comprising layer, a lower polysilicon-comprising layer, an intervening-material layer vertically between the tipper and lower polysilicon-comprising layers.

Abstract: Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate having a peripheral region and a memory cell region separated by an isolation structure. The isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material. A logic device is arranged on the peripheral region. A memory device is arranged on the memory region. The memory device includes a gate electrode and a memory hardmask over the gate electrode. An anti-dishing structure is disposed on the isolation structure. An upper surface of the anti-dishing structure and an upper surface of the memory hardmask have equal heights as measured from the top surface of the semiconductor substrate.

Abstract: A semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes stacked on the substrate, a channel structure penetrating the plurality of gate electrodes and including a channel layer extending in a vertical direction perpendicular to an upper surface of the substrate in the memory cell region, a dummy channel structure penetrating the plurality of gate electrodes and including a dummy channel layer extending in the vertical direction in the connection region, a first semiconductor layer disposed between the substrate and a lowermost one of the plurality of gate electrodes and surrounding the channel structure in the memory cell region, and an insulating separation structure disposed between the substrate and the lowermost one of the plurality of gate electrodes and surrounding the dummy channel layer.

Abstract: A vertical memory device includes a first gate structure on a substrate, the first gate structure including first gate electrodes spaced from each other in a first direction and stacked in a staircase shape, a second gate structure on the first gate structure and including second gate electrodes spaced from each other in the first direction and stacked in the staircase shape, a channel extending through the first and second gate structures, and a contact plug extending in the first direction through the first and second gate structures, wherein second steps at end portions of the second gate electrodes overlap first steps at end portions of the first gate electrodes, and wherein the contact plug extends through at least one of the first steps and through at least one of the second steps, while being electrically connected only to the first steps or to the second steps.

Abstract: A semiconductor storage device includes a stack, a channel layer, a first charge storage portion, and a second charge storage portion. The stack includes a plurality of conductive layers and a plurality of insulating layers, and the plurality of conductive layers and the plurality of insulating layers are alternately stacked one by one in a first direction. The channel layer extends in the first direction in the stack. The first charge storage portion is provided between the channel layer and each of the plurality of conductive layers in a second direction intersecting with the first direction. The second charge storage portion includes a portion interposed between two adjacent conductive layers in the plurality of conductive layers in the first direction.

Abstract: A memory device includes a lower structure and a plurality of upper structures stacked on the lower structure. The lower structure includes a peripheral circuit, and an upper bonding pad disposed on a top surface of the lower structure. Each of the plurality of upper structures includes a bit line, a through via, and a lower bonding pad disposed on a bottom surface of the upper structures and connected to the through via. Each of upper structures, other than an uppermost upper structure, further includes an upper bonding pad disposed on a top surface thereof and connected to the through via. The bit line includes a gap separating a first portion of the bit line from a second portion thereof in the horizontal direction, and the through via overlaps the gap of the bit line in a plan view.

Abstract: A memory structure and a manufacturing method for the same are provided. The memory structure includes a charge trapping layer, a first silicon oxynitride tunneling film and a second silicon oxynitride tunneling film. The first silicon oxynitride tunneling film is between the charge trapping layer and the second silicon oxynitride tunneling film. A first atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the first silicon oxynitride tunneling film is 10% to 50%. A second atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the second silicon oxynitride tunneling film is 1% to 15%. The concentration of the nitrogen atom of the second silicon oxynitride tunneling film is lower than that of the first silicon oxynitride tunneling film.

Abstract: A nonvolatile memory device having a cell over periphery (COP) structure includes a first sub memory plane and a second sub memory plane disposed adjacent to the first sub memory plane a row direction. A first vertical contact region is disposed in the cell region of the first sub memory plane and a second vertical contact region is disposed in the cell region of the second sub memory plane. A first overhead region is disposed in the cell region of the first sub memory plane and adjacent to the second vertical region in the row direction, and a second overhead region is disposed in the cell region of the second sub memory plane and adjacent to the first vertical region in the row direction. Cell channel structures are disposed in a main region of the cell region.

Abstract: A semiconductor memory device according to an embodiment includes a substrate including block areas, members, conductive layers, and pillars. Each of the members is respectively disposed at a boundary portion between the block areas. At least one member of the members includes first portions and a second portion. The first portions are arranged in a first direction. The second portion is disposed between any two adjacent ones of the first portions. Either one of one of the first portions and the second portion of the member is referred to as a third portion. The other one of the one of the first portions and the second portion of the member is referred to as a fourth portion. The third portion has a width in a second direction greater than a width of the fourth portion in the second direction.

Abstract: A memory device and a method for manufacturing the same, and an electronic apparatus including the memory device are provided. The memory device may include: a substrate (1001); an electrode structure on the substrate (1001), in which the electrode structure includes a plurality of first electrode layers and a plurality of second electrode layers that are alternately stacked; a plurality of vertical active regions penetrating the electrode structure; a first gate dielectric layer and a second gate dielectric layer, in which the first gate dielectric layer is between the vertical active region and each first electrode layer of the electrode structure, and the second gate dielectric layer is between the vertical active region and each second electrode layer of the electrode structure, each of the first gate dielectric layer and the second gate dielectric layer constitutes a data memory structure.

Abstract: A ferroelectric field-effect transistor (FeFET) includes first and second gate electrodes, source and drain regions, a semiconductor region between and physically connecting the source and drain regions, a first gate dielectric between the semiconductor region and the first gate electrode, and a second gate dielectric between the semiconductor region and the second gate electrode. The first gate dielectric includes a ferroelectric dielectric. In an embodiment, a memory cell includes this FeFET, with the first gate electrode being electrically connected to a wordline and the drain region being electrically connected to a bitline. In another embodiment, a memory array includes wordlines extending in a first direction, bitlines extending in a second direction, and a plurality of such memory cells at crossing regions of the wordlines and the bitlines. In each memory cell, the wordline is a corresponding one of the wordlines and the bitline is a corresponding one of the bitlines.

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle and a top view of the first metal interconnection includes an ellipse overlapping the circle.

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.

Abstract: A memory device and method of forming the same are provided. The memory device includes a first memory cell disposed over a substrate. The first memory cell includes a transistor and a data storage structure coupled to the transistor. The transistor includes a gate pillar structure, a channel layer laterally wrapping around the gate pillar structure, a source electrode surrounding the channel layer, and a drain electrode surrounding the channel layer. The drain electrode is separated from the source electrode a dielectric layer therebetween. The data storage structure includes a data storage layer surrounding the channel layer and sandwiched between a first electrode and a second electrode. The drain electrode of the transistor and the first electrode of the data storage structure share a common conductive layer.

Abstract: A variable resistance memory device includes memory cell structures on a substrate and spaced apart from each other in first and second directions, the first and second directions being parallel to a top surface of the substrate and intersecting each other, and a dummy cell structure surrounding each of the memory cell structures, as viewed in a plan view, the dummy cell structure being a single body structure extending continuously between all the memory cell structures, wherein each of the memory cell structures includes first conductive line on and intersecting second conductive lines, and memory cells between the first and second conductive lines, and wherein the dummy cell structure includes first dummy conductive lines on and intersecting second dummy conductive lines, and dummy memory cells between the first and second dummy conductive lines.

Abstract: Methods, systems, and devices for cross point array architecture for multiple decks are described. A memory array may include multiple decks, such as six or eight decks. The memory array may also include sockets for coupling access lines with associated decoders. The sockets may be included in sub-blocks of the array. A sub-block may be configured to include sockets for multiple access lines. A socket may intersect an access line in the middle of the access line, or at an end of the access line. Sub-blocks containing sockets for an access line may be separated by a period based on the access line.

Abstract: A method for forming a semiconductor structure includes: providing a substrate, a sacrificial layer and active layer on sacrificial layer being formed on the substrate; etching the active layer and sacrificial layer up to a surface of the substrate to form a plurality of active lines arranged in parallel and extending along first direction; filling an opening located between two adjacent ones of active lines to form a first isolating layer; etching an end of active lines to form an opening hole; removing sacrificial layer along opening hole, to form a gap between a bottom of the active lines and substrate; filling a conductive material in the gap to form a bit line extending along first direction; patterning the active lines to form a plurality of separate active pillars arrayed along first direction and second direction; and forming semiconductor pillars on top surfaces of respective ones of the active pillars.

Abstract: Organic photovoltaic cells (OPVs) and their compositions are described herein. In one or more embodiments, the OPV or solar cell includes a first electrode (e.g., cathode); a second electrode (e.g., anode); an active layer positioned between the first electrode and the second electrode; and a channel layer positioned between the first electrode and the active layer, wherein the channel layer is configured to laterally disperse a charge across the channel layer. In certain examples, the first electrode is arranged in a grid structure having a plurality of electrode segments and a respective opening between adjacent segments of the first electrode.

Abstract: An imaging device includes at least one first pixel electrode, at least one second pixel electrode, a photoelectric converter continuously covering upper surfaces of the at least one first pixel electrode and the at least one second pixel electrode, a first counter electrode facing the at least one first pixel electrode, a second counter electrode facing the at least one second pixel electrode, and a sealing layer continuously covering upper surfaces of the first and second counter electrodes. In a plan view, a first portion of an upper surface of the photoelectric converter in an interelectrode region between the first counter electrode and the second counter electrode is more depressed than a second portion of the upper surface of the photoelectric converter in an overlap region overlapping the first counter electrode or the second counter electrode. The sealing layer is in contact with the photoelectric converter in the interelectrode region.

Abstract: A light-emitting device comprising: a first electrode, a second electrode facing the first electrode; an emission layer disposed between the first electrode and the second electrode; and a first charge transport layer disposed between the first electrode and the emission layer, wherein a band gap energy of the emission layer and a band gap energy of the first charge transport layer are different from each other, the emission layer comprises a first perovskite compound, and the first charge transport layer consists of a second perovskite compound.

Abstract: A quantum dot composition includes a quantum dot, a ligand to bind to a surface of the quantum dot, an additive having an amine group, and a precursor comprising an organometallic compound, the composition forming a modified quantum dot having a reformed surface characteristic. A light emitting element including the modified quantum dot may have improved lifespan, luminous efficiency, and material stability.

Abstract: An organic light emitting element includes a first electrode, a hole transport region disposed on the first electrode, an emission layer disposed on the hole transport region, an electron transport region disposed on the emission layer and including an electron transport layer, and a second electrode disposed on the electron transport region. The hole transport region may include a first hole transport layer having a first refractive index, a second hole transport layer disposed on the first hole transport layer and having a second refractive index less than the first refractive index, and a third hole transport layer disposed below the first hole transport layer and having a third refractive index less than the first refractive index. A difference between the first refractive index and the second refractive index, and a difference between the first refractive index and the third refractive index may each be about 0.1 to about 1.0.

Abstract: A display device includes: light-emitting regions different in luminescent colors and including luminescent layers separated for each of the luminescent colors; a low-threshold layer lower in threshold voltage than any one of the luminescent layers included in a pair of different-color light-emitting regions included in the light-emitting regions, different in the luminescent colors, and adjacent to each other; a continuous layer under the luminescent layers and the low-threshold layer, including first areas and a second area continuously, the first areas being in contact with the respective light-emitting regions, the second area being in contact with the low-threshold layer; pixel electrodes under the continuous layer, overlapping with the respective light-emitting regions; and a counter electrode over the luminescent layers and the low-threshold layer, being opposed to the pixel electrodes. The low-threshold layer is between the pair of different-color light-emitting regions.

Abstract: A transparent display panel, including a substrate, a first electrode layer disposed on the substrate, a light-emitting structure layer disposed on the first electrode layer, and a second electrode layer disposed on the light-emitting structure layer; the first electrode layer includes a plurality of first electrode groups arranged along a first direction; each of the first electrode groups includes at least one first electrode extending along a second direction, the second direction intersects with the first direction; each of the at least one first electrode includes at least two first electrode blocks and at least one connecting part, and two adjacent first electrode blocks are electrically connected with each other by a corresponding connecting part.

Abstract: A computing device is disclosed that includes an organic light-emitting diode (OLED) display. The OLED display has a front surface and a back surface. The computing device includes a moveable display support connected to the back surface of the display. In some implementations, the moveable display support is configured to limit bending in one direction to a first bend radius and to limit bending in another direction to a second bend radius. In some implementations, the moveable display support is formed by a plurality of unit cells.

Abstract: A display device includes a base; a light emitting element on the base; a capping layer on the light emitting element; a thin-film encapsulation layer including a first inorganic layer on the capping layer, an organic layer on the first inorganic layer, and a second inorganic layer on the organic layer; and a wavelength conversion pattern on the thin-film encapsulation layer and overlapping the light emitting element, wherein the first inorganic layer includes two sub-inorganic layers having different refractive indices.

Abstract: A display panel including a corner includes: a substrate including a display area including a front display area, and a peripheral area outside the display area; an insulating layer on the substrate in the display area and the peripheral area, where an outer groove or an outer through hole is defined in the insulating layer in the peripheral area; an upper inorganic pattern layer on the insulating layer, where the upper inorganic pattern layer includes a protruding tip protruding toward a center of the outer groove or a center of the outer through hole; and a front display element on the insulating layer and overlapping the front display area. The upper inorganic pattern layer is apart from the front display element.

Abstract: A display panel, a manufacturing method and a display device are provided. The display panel includes a substrate having a display area and a non-display area; a planarization layer covering the display area and the non-display area of the substrate; an organic light emitting element located in the display area and located at a side of the planarization layer away from the substrate; an encapsulation structure including a first inorganic layer, an organic layer and a second inorganic layer which are sequentially stacked, where the first inorganic layer and the second inorganic layer extend into a non-display area, and the first inorganic layer is arranged close to the planarization layer; and/or, a part of the planarization layer located in the non-display area is provided with a groove, and the groove is filled with a flexible water-oxidation resistant material.

Abstract: A display device according to embodiments includes: a display panel that includes a display area that includes a partition layer that includes a first opening through which light is emitted from an organic light emitting diode and a peripheral area around the display area; a touch electrode disposed on the display panel; a touch electrode passivation layer that covers the touch electrode and includes a second opening that corresponds to the first opening; and a high refractive index layer that covers the touch electrode passivation layer and the second opening. The touch electrode passivation layer includes an open region formed in a portion that corresponds to the peripheral area, and the touch electrode passivation layer is not formed in the open region.

Abstract: A light emitting photonic crystal having an organic light emitting diode and methods of making the same are disclosed. An organic light emitting diode disposed within a photonic structure having a band-gap, or stop-band, allows the photonic structure to emit light at wavelengths occurring at the edges of the band-gap. Photonic crystal structures that provide this function may include materials having a refractive index that varies.

Abstract: A light emitting element includes a first electrode, an organic layer formed on the first electrode and including a luminescent layer composed of an organic luminescent material and a second electrode formed on the organic layer, and further includes a light reflecting layer provided below the first electrode. Light emitted in the luminescent layer is resonated between the light reflecting layer and an interface of the second electrode and the organic layer, and a portion of the light is output from the second electrode.

Abstract: A method of reducing color breakup of reflection of ambient light in a display panel having a color breakup-prevention structure is provided. The color breakup-prevention structure includes a high refractive index lens layer on a side of a plurality of light emitting elements away from a base substrate; a low refractive index modulation layer on a side of the high refractive index lens layer away from the base substrate; a first color filter layer in a plurality of subpixel regions, and spaced apart from the high refractive index lens layer by the low refractive index modulation layer; and a first black matrix layer in an inter-subpixel region, and spaced apart from the high refractive index lens layer by the low refractive index modulation layer. The high refractive index lens layer includes a plurality of lens portions spaced apart from each other and respectively in the plurality of subpixels.

Abstract: An organic light emitting diode (OLED) display may include: an OLED configured to emit light of wavelength ?; an encapsulation layer encapsulating the OLED, the encapsulation layer including: a first inorganic layer disposed on the OLED, the first inorganic layer including: one or more first layers having a first refractive index (n1) and a first thickness substantially equal to ?/(4*n1); and one or more second layers having a second refractive index (n2) and a second thickness substantially equal to ?/(4*n2), wherein the second refractive index is smaller than the first refractive index, and wherein the one or more first layers and the one or more second layers are alternatingly stacked on one another.

Abstract: Disclosed is a display panel and a display device capable of reducing the reflection of external light. The display panel includes a touch sensor, disposed on an encapsulation unit, and an antireflective film disposed in a non-emission area of the touch sensor so as to overlap each other, whereby it is possible to reduce external light from being incident on the touch sensor and a routing line, and therefore it is possible to reduce the reflectance of external light without using an expensive polarizing plate.

Abstract: The present invention provides a display panel and a display device. A first gate electrode and a first polar plate of a first thin film transistor are used to constitute a storage capacitor. At a same time, the first polar plate and a second gate electrode of a second thin film transistor are disposed in a same layer. Therefore, a gate insulation layer used to separate the first polar plate from the first gate electrode and the second gate electrode in layers can be omitted, so as to reduce a number of film layers in the display panel and a thickness of a film laminated structure, thereby reducing a complexity of a process flow of the display panel, and improving bending ability of the display panel.

Abstract: A light emitting device includes a transistor, a light reflection layer, a first insulation layer that includes a first layer thickness part, a second layer thickness part, and a third layer thickness part, a pixel electrode that is provided on the first insulation layer, a second insulation layer that covers a peripheral section of the pixel electrode, a light emission functional layer, a facing electrode, and a conductive layer that is provided on the first layer thickness part. The pixel electrode includes a first pixel electrode which is provided in the first layer thickness part, a second pixel electrode which is provided in the second layer thickness part, and a third pixel electrode which is provided in the third layer thickness part. The first pixel electrode, the second pixel electrode, and the third pixel electrode are connected to the transistor through the conductive layer.