Abstract: A lead-free piezoelectric ceramic sensor material and a preparation method thereof and relates to the technical field of piezoelectric ceramic processing. The main raw materials of the lead-free piezoelectric ceramic sensor material disclosed in the present disclosure are a barium carbonate, a calcium carbonate, a zirconia, a titanium dioxide, a strontium carbonate, an erbium oxide, and a bismuth oxide. The preparation method is prepared through the steps of preparing ingredients, ball milling, granulating and tableting, debinding, and sintering, and the lead-free piezoelectric ceramic sensor material can be made into a lead-free piezoelectric sensor through applying an electrode and electrode polarizing. The present disclosure has an excellent compactness and a good chemical stability. And the piezoelectric sensor made of the lead-free piezoelectric ceramic sensor material has a high sensitivity, a strong working stability, an excellent piezoelectric and has a high Curie temperature.

Abstract: In an exemplary embodiment, a piezoelectric ceramic composition is an alkali niobate-based piezoelectric ceramic composition whose primary component is a compound expressed by the general formula LixNayK1-x-yNbO3 (where 0<x<1, 0<y<1, and x+y<1), and which contains 100 ppm or more but less than 1000 ppm of fluorine by mass. The alkali niobate-based piezoelectric ceramic composition demonstrates good properties even when sintered at low temperature.

Abstract: According to one embodiment, a magnetic memory device includes first and second wirings, and memory cells between the first and second wirings, and each including a switching element and a magnetoresistance effect element, the switching element being connected to a first wiring, and the magnetoresistance effect element being connected to a second wiring. The switching element includes a bottom electrode, a top electrode, and a switching material layer between the bottom and top electrodes, and the bottom electrode included in each of the memory cells adjacent to each other in a first direction is continuously provided on the first wiring connecting the memory cells adjacent to each other in the first direction.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.

Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.

Abstract: A three terminal spin-orbit-torque (SOT) device is disclosed wherein a free layer (FL) with a switchable magnetization is formed on a Spin Hall Effect (SHE) layer comprising a Spin Hall Angle (SHA) material. The SHE layer has a first side contacting a first bottom electrode (BE) and an opposite side contacting a second BE where the first and second BE are separated by a dielectric spacer. A first current is applied between the two BE, and the SHE layer generates SOT on the FL thereby switching the FL magnetization to an opposite perpendicular-to-plane direction. The SHE layer is a positive or negative SHA material, and may be a topological insulator such as Bi2Sb3. A top electrode is formed on an uppermost hard mask in each SOT device. A single etch through the FL and SHE layer ensures a reliable first current pathway that is separate from a read current pathway.

Abstract: Provided is a Hall element that detects a magnetic field. The Hall element includes a substrate including a semiconductor region, a first drive electrode arranged on the substrate, a first ground electrode arranged on the substrate separately from the first drive electrode in a first direction, a second ground electrode arranged on the substrate separately from the first drive electrode in a second direction different from the first direction, and a detection electrode group including a first electrode group that detects a Hall voltage generated by a current of components perpendicular to a surface of the substrate, the current flowing from the first drive electrode to the first ground electrode and the second ground electrode.

Abstract: A current sensor package, comprises a current path and a sensing device. The sensing device is spaced from the current path, and the sensing device is configured for sensing a magnetic field generated by a current flowing through the current path. Further, the sensing device comprises a sensor element. The sensing device is electrically connected to a conductive trace. An encapsulant extends continuously between the current path and the sensing device.

Abstract: The invention includes methods, and the structures formed, for multi-qubit chips. The methods may include annealing a Josephson junction of a qubit to either increase or decrease the frequency of the qubit. The conditions of the anneal may be based on historical conditions, and may be chosen to tune each qubit to a desired frequency.

Abstract: Techniques regarding selectively tuning the operating frequency of superconducting Josephson junction resonators are provided. For example, one or more embodiments described herein can comprise a method that can include chemically altering a Josephson junction of a Josephson junction resonator via a plasma treatment. The method can also comprise selectively tuning an operating frequency of the Josephson junction resonator based on a property of the plasma treatment.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, the method includes forming a bottom electrode over a substrate. A first switching layer is formed on the bottom electrode. The first switching layer comprises a dielectric material doped with a first dopant. A second switching layer is formed over the first switching layer. An atomic percentage of the first dopant in the second switching layer is less than an atomic percentage of the first dopant in the first switching layer. A top electrode is formed over the second switching layer.

Abstract: A phase change memory (PCM) structure including a bottom electrode, a first dielectric spacer disposed above and in contact with the bottom electrode, the first dielectric spacer comprising a vertical seam, a PCM layer disposed above the first dielectric spacer, and a heater element disposed in the seam and in contact with the bottom electrode.