Patents Issued in March 12, 2024
  • Patent number: 11930719
    Abstract: Magnetic memory devices are provided. The devices comprise a first ferromagnetic layer, a second ferromagnetic layer, and a tunnel barrier layer composed of a doped semiconductor (instead of an insulator or a dielectric) between the first and second ferromagnetic layers and forming at least one ferromagnetic-doped semiconductor interface.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: March 12, 2024
    Assignee: Northwestern University
    Inventors: Pedram Khalili Amiri, Manijeh Razeghi
  • Patent number: 11930720
    Abstract: The present disclosure provides a storage unit, a data writing method and a data reading method thereof, a memory and an electronic device. The storage unit includes a semiconductor substrate, a first insulating medium layer, a ferroelectric thin film layer, a bottom electrode, a tunnel junction, a first metal interconnection portion, a second metal interconnection portion, a third metal interconnection portion and a fourth metal interconnection portion. The first insulating medium layer is formed on the semiconductor substrate, the ferroelectric thin film layer is disposed on the first insulating medium layer, the bottom electrode is formed on the ferroelectric thin film layer, and the tunnel junction is formed on the bottom electrode. The first metal interconnection portion is connected to a first end of the bottom electrode, and the third metal interconnection portion is connected to a second end of the bottom electrode.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: March 12, 2024
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Meiyin Yang, Jun Luo, Yan Cui, Jing Xu
  • Patent number: 11930721
    Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: March 12, 2024
    Assignee: 1372934 B.C. LTD.
    Inventors: Eric Ladizinsky, Jeremy P. Hilton, Byong Hyop Oh, Paul I. Bunyk
  • Patent number: 11930722
    Abstract: Operational characteristics of an high temperature superconducting (“HTS”) film comprised of an HTS material may be improved by depositing a modifying material onto appropriate surfaces of the HTS film to create a modified HTS film. In some implementations of the invention, the HTS film may be in the form of a “c-film.” In some implementations of the invention, the HTS film may be in the form of an “a-b film,” an “a-film” or a “b-film.” The modified HTS film has improved operational characteristics over the HTS film alone or without the modifying material. Such operational characteristics may include operating in a superconducting state at increased temperatures, carrying additional electrical charge, operating with improved magnetic properties, operating with improved mechanic properties or other improved operational characteristics. In some implementations of the invention, the HTS material is a mixed-valence copper-oxide perovskite, such as, but not limited to YBCO.
    Type: Grant
    Filed: April 24, 2022
    Date of Patent: March 12, 2024
    Assignee: Ambature, Inc.
    Inventors: Douglas J. Gilbert, Timothy S. Cale
  • Patent number: 11930723
    Abstract: An ionic redox transistor comprises a solid channel, a solid reservoir layer, and a solid electrolyte layer disposed between the channel and the reservoir layer. The channel exhibits a substantially linear current-voltage relationship in a first range of voltages, and a nonlinear current-voltage relationship in a second range of voltages that is greater than the first range of voltages. One or both of the substantially linear current-voltage relationship or the nonlinear current-voltage relationship of the channel is varied by changing the concentration of ions such as oxygen vacancies in the channel. Ion or vacancy transport between the channel and the reservoir layer across the electrolyte layer occurs in response to applying a voltage between the channel and the reservoir layer. Subject to the first range of voltages, the channel can function as a synapse device. Subject to the second range of voltages, the channel can function as a neuron device.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: March 12, 2024
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Albert Alec Talin, Elliot James Fuller, Christopher Bennett, Tianyao Xiao, Matthew Marinella, Suhas Kumar
  • Patent number: 11930724
    Abstract: A phase change memory (PCM) cell includes an electrode, a heater electrically connected to the electrode, a PCM material electrically connected to the heater, a second electrode electrically connected to the PCM material, an electrical insulator surrounding the PCM material, and a shield positioned between the PCM material and the electrical insulator, the shield comprising a reactive-ion-etching-resistant material.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: March 12, 2024
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Nicole Saulnier, Muthumanickam Sankarapandian, Andrew Herbert Simon, Steven Michael McDermott, Iqbal Rashid Saraf