Abstract: A thermal component has a shield portion and a heat exchanger portion. The shield portion includes a plurality of cells adapted to inhibit radio radiation (RF) having a frequency within a target frequency range, while the heat exchanger portion includes a plurality of elongated channels, each one of the elongated channels being physically connected to and in fluid communication with at least one corresponding cell of the plurality of cells.

Abstract: Information handling system (IHS) component immersion cooling systems and methods employ an apparatus having an IHS component immersion cooling flow passage housing disposed at (a) IHS component(s) of an IHS disposed in an immersion cooling tank. The IHS component immersion cooling flow passage housing has an immersion fluid inlet open to immersion fluid within tank and an immersion fluid outlet connected to a return line of an immersion fluid pump. The IHS component cooling apparatus flow passage housing may be a cold plate or a ducted heatsink disposed on, or about, the IHS component(s) of the IHS disposed in the immersion cooling tank. The immersion fluid pump may be the pump that also circulates the immersion fluid within the tank. The tank may include a manifold in fluid flow communication with the pump. This manifold may receive a plurality of return lines, each from an IHS component cooling apparatus.

Abstract: A liquid cooling head includes a bottom plate, a heat dissipation plate, a partition plate and an upper cover plate. The bottom plate includes an opening, and the heat dissipation plate, the partition plate and the upper cover plate are fixed to the bottom plate. The partition plate divides the opening into a plurality of cooling chambers, and each cooling chamber is equipped with a cooling liquid inlet, a cooling liquid outlet, a pump and an electric control device. The cooling liquid inlet and the cooling liquid outlet are formed in the upper cover plate, the pump is fluid-connected to the cooling liquid outlet, and the electric control device drives the pump to rotate, so that the cooling liquid flows through the cooling chamber to cool one heat source below the heat dissipation plate. In addition, a liquid cooling device with the liquid cooling head is also disclosed therein.

Abstract: A plug-in pump installation structure of a cooling distribution unit is disclosed. A pump seat is disposed in a machine case and has a fixed joint. A plug-in pump has a pump main body and a moveable joint. The plug-in pump is plugged or removed relative to the pump seat through the moveable joint and the fixed joint being connected or released. One distal end of each rotary arm of a handgrip has a latching hook. The rotary arms are pivotally connected at opposite sides of the pump main body. When the handgrip is folded on the machine case, the latching hook abuts against a protrusion disposed on a block piece of the machine case, when the handgrip is rotated to be away from the machine case, the latching hooks of the rotary arm is released from the abutted protrusion.

Abstract: There is disclosed in one example a heat dissipator for an electronic apparatus, including: a planar vapor chamber having a substantially rectangular form factor, wherein a second dimension d2 of the rectangular form factor is at least approximately twice a first dimension d1 of the rectangular form factor; a first fan and second fan; and a first heat pipe and second heat pipe discrete from the planar vapor chamber and disposed along first and second d1 edges of the planar vapor chamber, further disposed to conduct heat from the first and second d1 edges to the first and second fan respectively.

Abstract: Some embodiments include a thermal ground plane comprising a first and second casing with folding and non-folding regions. The thermal ground plane may also include a vapor structure and a mesh. The mesh may be disposed on an interior surface of the second casing and the mesh include a plurality of arteries extending substantially parallel with a length of the thermal ground plane. The folding region of the first casing may have an out-of-plane wavy structure. The valleys and peaks of the out-of-plane wavy structure, for example, may extend across a width of the first active region substantially parallel with a width of the thermal ground plane.

Abstract: An information handling system with a cooling system may include a processor; a memory; a power management unit (PMU); a cooling system including: a fan; and a cooling system heat pipe; a detachable thermal module including: a first heat conductive element to be operatively coupled to a heat producing components such as a processor, a radio module, or other component; a second heat conductive element to be operatively coupled to the cooling system heat pipe of the cooling system; and a detachable thermal module heat pipe formed between the first heat conductive element and the second heat conductive element.

Abstract: A board structure includes: a board with a heat generating element; a heat sink including a plate-shaped base member with one face contacting the heat generating element, and plural fins side by side on another face of the base member, the fins extending in a cooling air flow direction, the fins having distal ends downstream in the flow direction; a first resisting member on a downstream side with respect to the heat sink and acting as a resistor for exhaust of the cooling air; and a second resisting member on the downstream side and on a first side that the fins are arranged respective to the heat sink and acting as a resistor for the cooling air. Distal ends of the fins on a second side that the fins are arranged are upstream of the distal ends of the fins on the first side.

Abstract: An electronic device protecting casing with heating function includes: a casing; a battery box within the casing; an interior of the battery box being arranged with a battery, a back side of the battery box being formed with an opening for receiving the battery; an outer cover serving to seal the opening; an inner side of the outer cover being formed with a heat isolation sheet; a heating unit being installed within the casing for heating the tablet computer; the heating unit including an electric heating plate. When power of the battery is transferred to the electric heating plate, the electric heating plate generates heat power and then transfers the power to the tablet computer for heating it; and a control circuit is installed within the casing; the electric heating plate is connected to the battery through a control switch; and the control circuit is connected to the control switch.

Abstract: According to one embodiment, a thermal management system includes a thermoelectric cooling (TEC) element mounted on an information technology (IT) component, wherein the element draws a first power to cool the component; a load sensor to sense a second power that is drawn by the component to perform a first set of operations; a temperature sensor to sense a temperature of the component; and a controller to determine whether the second power drawn has changed based on the load sensor, wherein the component performs a second set of operations while drawing the second power, and in response to the changed second power, adjust the power supplied to the element and component based on the temperature and the power supplied to the component, such that the component continues to perform the second set of operations while drawing the adjusted power that is less than the power drawn before the adjustment.

Abstract: An inverter and a heat radiation structure thereof are provided. The heat radiation structure of the inverter includes a heat radiator for radiating heat from a heating element of the inverter, and a heat radiation fan for air-cooling the heat radiator. The heat radiator includes multiple heat radiation fins able to be air-cooled. The number of the heat radiator is at least two, and two adjacent heat radiators are a first heat radiator and a second heat radiator respectively. The heat radiation fan is provided between the first heat radiator and the second heat radiator, and the heat radiation fan is located on the tops of the heat radiation fins. In the heat radiation structure of the inverter, the heat radiation fan is capable of cooling the first heat radiator and the second heat radiator at the same time.

Abstract: Electronic equipment allowed to endure repetitive severe environmental change in a sterilizing treatment using an autoclave is provided. A tablet terminal (electronic equipment) 106 includes: an enclosure 10; a substrate 30 arranged in an internal space of the enclosure 10; an electronic circuit component 40 mounted on the substrate 30; a (first) heat insulating layer 50 formed along the enclosure 10; and a (first) heat release mechanism 70 allowed to discharge heat from an internal space of the heat insulating layer 50 to outside of the enclosure 10.

Abstract: A device includes a substrate, a pull-down transistor over the substrate, a pass-gate transistor over the substrate, and a pull-up transistor over the substrate. The pull-up transistor includes a first gate structure and first source/drain epitaxy structures on opposite sides of the first gate structure, in which each of the first source/drain epitaxy structures comprises a first epitaxy layer and a second epitaxy layer over the first epitaxy layer, wherein a germanium concentration of the first epitaxy layer is higher than a germanium concentration of the second epitaxy layer.

Abstract: Disclosed is a semiconductor memory device comprising a plurality of memory cells each including an access transistor, a pull-up transistor, and a pull-down transistor on a substrate, a first line layer on the memory cells and including a first lower landing pad and a second lower landing pad, a second line layer on the first line layer and including a ground line having an opening and an upper landing pad in the opening, and a third line layer including a word line on the second line layer. The ground line is electrically connected through the first lower landing pad to a terminal of the pull-down transistor. The word line is electrically connected through the upper landing pad and the second lower landing pad to a terminal of the access transistor.

Abstract: A Dynamic Random Access Memory (DRAM) capacitor and a preparation method therefor are provided. The DRAM capacitor includes a dielectric layer, and the dielectric layer includes a high dielectric material layer, and low dielectric loss material layers provided on both side surfaces of the high dielectric material layer.

Abstract: The present disclosure relates to a semiconductor memory device and a fabricating method thereof, and the semiconductor memory device includes a substrate, bit lines, plugs and a spacer structure. The bit lines are separately disposed on the substrate, and the plugs are also disposed on the substrate to alternately arrange with the bit lines. The spacer structure is disposed on the substrate, between each of the bit lines and each of the plugs. The spacer structure includes a first air gap layer, a first spacer and a second air gap layer, and the first air gap layer, the first spacer and the second air gap layer are sequentially stacked between sidewalls of the bit lines and the plugs. Therefore, two air gap layers may be formed between the bit lines and the storage node contacts to improve the delay between the resistor and the capacitor.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. According to embodiments of the present disclosure, a height of the work function layer, especially a height of the second portion of the work function layer, is significantly increased, and a height of the first gate material layer is significantly reduced, so that the height ratio of the second portion of the work function layer to the first gate material layer to the second gate material layer is maintained at 3 to 8:1 to 1.5:1; therefore, it can be ensured that the work function of the WL groove filling material layer of the recessed gate structure with a small WL width will be significantly increased, thereby greatly weakening the row hammer effect at the bottom of the WL groove and obviously reducing the GIDL effect at the upper part of the WL groove.

Abstract: A method for preparing a semiconductor device, including providing a substrate, where a word line structure is formed in the substrate; a bit line supporting layer includes a first oxide layer and a first nitride layer. A bit line structure is formed in the first nitride layer, and the first oxide layer is formed on both sides of the bit line structure and located in the first nitride layer; patterning the supporting structure to form a first via corresponding to the bit line structure; and etching the bit line supporting layer to a preset height along the first via, adjusting an etching parameter and a selective etching ratio of etching gas for an oxide layer to a nitride layer, and continuing to etch the bit line supporting layer until the bit line structure is exposed, to form a polymer layer above the bit line structure.

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising memory cells, digit lines, word lines, and at least one isolation material covering and surrounding the memory cells, the digit lines, and the word lines. An additional microelectronic device structure comprising control logic devices and at least one additional isolation material covering and surrounding the control logic devices is formed. The additional microelectronic device structure is attached to the microelectronic device structure. Contact structures are formed to extend through the at least one isolation material and the at least one additional isolation material. Some of the contact structures are coupled to some of the digit lines and some of the control logic devices. Some other of the contact structures are coupled to some of the word lines and some other of the control logic devices. Microelectronic devices, electronic systems, and additional methods are also described.

Abstract: The present application relates to a semiconductor structure and a method of manufacturing the same. The method includes: providing a substrate; forming a bitline contact hole located in the substrate, and a non-metal conductive layer with which a surface of the substrate is covered and the bitline contact hole is filled, the non-metal conductive layer provided with a first opening therein, the first opening aligned with the bitline contact hole; forming a metal conductive layer, with which a surface of the non-metal conductive layer is covered; forming an insulation layer, with which a surface of the metal conductive layer surface is covered; and etching the insulation layer, the metal conductive layer, and the non-metal conductive layer to form a bitline structure.

Abstract: Transistor antifuses are disclosed. An apparatus may include an antifuse that may be configurable either as a short between a first node and a second node or as an open between the first node and the second node. The antifuse may include a selection transistor and an antifuse transistor. A source or drain of the selection transistor may be electrically coupled to the first node. A gate of the selection transistor may be configured to receive a selection voltage. A gate of the antifuse transistor may be electrically coupled the other of the source or drain of the selection transistor. A source or drain of the antifuse transistor may be electrically coupled to the second node. Associated devices, systems, and methods are also disclosed.

Abstract: Described is selective deposition of a silicon nitride (SiN) trap layer to form a memory device. A sacrificial layer is used for selective deposition in order to permit selective trap deposition. The trap layer is formed by deposition of a mold including a sacrificial layer, memory hole (MH) patterning, sacrificial layer recess from MH side, forming a deposition-enabling layer (DEL) on a side of the recess, and selective deposition of trap layer. After removing the sacrificial layer from a slit pattern opening, the deposition-enabling layer (DEL) is converted into an oxide to be used as blocking oxide.

Abstract: A nonvolatile memory device includes a first structure and a second structure bonded to the first structure. The second structure includes a low-resistance conductive layer, a common source line layer on the low-resistance conductive layer, a stack structure above the common source line layer, a plurality of channel structures passing through a cell region of the stack structure and contacting the common source line layer, a dummy channel structure passing through a step region of the stack structure and contacting the common source line layer, a second insulating structure on the stack structure, a plurality of second bonding pads on the second insulating structure, and a second interconnect structure in the second insulating structure.

Abstract: A three-dimensional semiconductor memory device may include horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other, memory structures provided on the horizontal patterns, respectively, each of the memory structures including a three-dimensional arrangement of memory cells. Penetrating insulating patterns and separation structures may isolate the horizontal patterns from one another. Through vias may extend through the penetrating insulating patterns to connect logic circuits of the peripheral circuit structure to the memory structure.

Abstract: The semiconductor device includes a substrate having a cell area and a via area; a transistor and a logic interconnection disposed over the substrate; a lower insulating layer covering the transistor and the logic interconnection; a lower conductive layer on the lower insulating layer in the cell area; a support pattern disposed on the lower insulating layer in the via area; a lower via plug having a side surface in contact with the support pattern and a bottom surface in contact with the logic interconnection; a word line stack disposed on the lower conductive layer in the cell area; an dielectric layer stack disposed on the support pattern in the via area; a vertical channel pillar penetrating the word line stack to be connected to the lower conductive layer; and an upper via plug penetrating the dielectric layer stack to be vertically aligned with the lower via plug.

Abstract: A semiconductor device includes circuit elements on a first substrate; gate electrodes on a second substrate and stacked to be apart from each other in a first direction; sacrificial insulating layers on a lower through-insulating layer penetrating the second substrate, stacked to be spaced apart from each other in the first direction, and having side surfaces opposing the gate electrodes; channel structures penetrating the gate electrodes, extending vertically on the second substrate, and including a channel layer; a first separation pattern penetrating the gate electrodes and including a first barrier pattern and a first pattern portion extending from the first barrier pattern in a second direction; and a second separation pattern penetrating the gate electrodes, disposed to be parallel to the first separation pattern, and extending in the second direction. Some of the side surfaces of the sacrificial insulating layers may overlap the first barrier pattern in a third direction.

Abstract: A semiconductor device includes a stacked structure including conductive layers and gaps respectively interposed between the conductive layers, a channel layer passing through the stacked structure, a ferroelectric layer surrounding a sidewall of the channel layer, and first dielectric patterns interposed between the ferroelectric layer and the conductive layers, respectively. The gaps extending between the first dielectric patterns.

Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

Abstract: The present disclosure provides a semiconductor structure and a storage circuit that implements the storage structure of a magnetoresistive random access memory (MRAM) based on a dynamic random access memory (DRAM) fabrication platform.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a transistor region, a first and a second contact plug, a first metal via, a magnetic tunneling junction (MTJ) structure, and a metal interconnect. The transistor region includes a gate over the substrate, and a first and a second doped regions at least partially in the substrate. The first and the second contact plug are over the transistor region. The first and the second contact plug include a coplanar upper surface. The first metal via and the MTJ structure are over the first and the second contact plug, respectively. The first metal via is leveled with the MTJ structure. The metal interconnect is over the first metal via and the MTJ structure, and the metal interconnect includes at least two second metal vias in contact with the first metal via and the MTJ structure, respectively.

Abstract: A resistive memory device includes a plurality of first conductive lines in a first area and a second area on a substrate, a plurality of second conductive lines in the first area and the second area, the plurality of second conductive lines being apart from the plurality of first conductive lines in a vertical direction, and a plurality of memory cells connected to the first and second conductive lines at a plurality of intersections between the plurality of first and second conductive lines in the first area and the second area. The plurality of memory cells include an active memory cell in the first area and a dummy memory cell in the second area. The active memory cell including a first resistive memory pattern having a first width and the dummy memory cell including a second resistive memory pattern having a second width greater than the first width.

Abstract: An electronic device includes a semiconductor memory including material layers each including one or more low-resistance areas and one or more high-resistance areas, insulating layers stacked alternately with the material layers and including protrusions extending more than the material layers, conductive pillars passing through the insulating layers and the low-resistance areas, conductive layers located between the protrusions, and variable resistance layers interposed between the low-resistance areas and the conductive layers.

Abstract: A semiconductor device including: a first level including first memory arrays, a plurality of first transistors, and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes second memory arrays; a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, where the second filled holes are aligned to the first filled holes with a more than 1 nm but less than 40 nm alignment error, and where the third level includes decoder circuits.

Abstract: A transparent top electrode composite film for organic optoelectronic devices includes a substrate, an MoOx film layer coated on the substrate, a doped Ag-based film layer coated on the MoOx film layer and an HfOx film layer coated on the doped Ag-based film layer. A preparation method of the transparent top electrode composite film, which is achieved under vacuum and low temperature, includes steps of (A) depositing an MoOx film layer on a substrate through thermal evaporation process or electron beam evaporation process without heating the substrate; (B) depositing a doped Ag-based film layer on the MoOx film layer through sputtering process or evaporation process; and (C) depositing an HfOx film layer on the doped Ag-based film layer through reactive sputtering process, thereby obtaining the transparent top electrode composite film. The composite film is able to be used as a top electrode material for organic optoelectronic devices.

Abstract: Organic luminescent material, includes: host material, TADF sensitizer, and fluorescent-luminescent material; wherein absolute value of difference between LUMO level of the host material and LUMO level of the TADF sensitizer is not more than 0.4 eV, and absolute-value of difference between HOMO level of the host material and HOMO level of the TADF sensitizer is not more than 0.4 eV; absolute-value of LUMO level of the fluorescent-luminescent material is not more than absolute-value of the LUMO level of the host material and the LUMO level of the TADF sensitizer, and/or absolute-value of HOMO level of the fluorescent-luminescent material is not less than an absolute-value of the HOMO level of the host material and absolute-value of the HOMO level of the TADF sensitizer; and emission-spectrum of the host material overlaps an absorption-spectrum of the TADF sensitizer, and emission-spectrum of the TADF sensitizer overlaps absorption-spectrum of the fluorescent-luminescent material.

Abstract: An organic light emitting display apparatus including a substrate including a plurality of pixel areas; a pixel electrode on the substrate; an opposite electrode on the pixel electrode, the opposite electrode transmitting light; an organic light emitting layer between the pixel electrode and the opposite electrode, the organic light emitting layer emitting a first light toward the opposite electrode; a light emitting layer on the opposite electrode, the light emitting layer absorbing a portion of the first light and emitting a second light; and a sealing layer on the light emitting layer, the sealing layer sealing the pixel electrode, the opposite electrode, the organic light emitting layer, and the light emitting layer.

Abstract: A light-emitting device with high emission efficiency and reliability is provided. The light-emitting device includes a fluorescent light-emitting layer and a phosphorescent light-emitting layer. A host material used in the fluorescent light-emitting layer has a function of converting triplet excitation energy into light emission and a guest material used in the fluorescent light-emitting layer emits fluorescence. The guest material has a molecular structure including a luminophore and a protecting group, and one molecule of the guest material includes five or more protecting groups. The introduction of the protecting groups into the molecule inhibits transfer of triplet excitation energy from the host material to the guest material by the Dexter mechanism. An alkyl group or a branched-chain alkyl group is used as the protecting group.

Abstract: An organic light-emitting device having a perovskite layer having a thickness of 50 nm or more has a low drive voltage and a high power efficiency, and can suppress interelectrode short-circuiting and current leakage.

Abstract: A display device is provided that includes a substrate including an active area and a non-active area, a planarization film disposed over the substrate, an anode electrode disposed on the planarization film and including a first hole in the non-active area, a bank disposed on the anode electrode, a cathode electrode disposed on the bank, an encapsulation layer disposed on the cathode electrode, and a touch sensor disposed on the encapsulation layer and including a touch line in the non-active area. Here, the first hole may be disposed not to overlap with the touch line.

Abstract: A foldable display device assembly includes a rigid film having first and second sections spaced apart from each other, the rigid film being foldable about a folding axis disposed between the first and second sections of the rigid film; an adhesion structure having first and second adhesion sections spaced apart from each other, the first and second adhesion sections being disposed on the first and second sections of the rigid film, respectively; a lower flexible module disposed on the adhesion structure; a flexible display module disposed on the lower flexible module; and an upper flexible module disposed on the flexible display module.

Abstract: The present disclosure discloses a display apparatus, including a substrate including a pixel area including a disconnected area which encloses a hole area, an organic light emitting diode formed in the pixel area and the disconnected area, a plurality of inorganic insulating layers disposed below the organic light emitting diode, a disconnection structure which is disposed in the disconnected area and encloses the hole area, and an internal dam which is disposed in the disconnected area and encloses the disconnection structure, and in which the disconnection structure includes an eave portion which is simultaneously formed with the internal dam and a trench which is formed by etching the plurality of inorganic insulating layers disposed below the eave portion, and the disconnection structure is configured to have a predetermined overhang and a predetermined depth by the eave portion and the trench structure.

Abstract: A display apparatus includes a substrate including a main display area and a component area. The component area includes an auxiliary display area and a transmission area. Main display elements are disposed in the main display area. Auxiliary display elements are disposed in the component area. A thin-film encapsulation layer covers the main display elements and the auxiliary display elements. An optical functional layer is disposed on the thin-film encapsulation layer and includes a polarization layer. The polarization layer includes a first portion disposed in the transmission area and a second portion disposed in the main display area and the auxiliary display area.

Abstract: A display panel includes: a substrate defining an opening therein; a plurality of light-emitting diodes in a display area surrounding the opening; an encapsulation layer on the plurality of light-emitting diodes, the encapsulation layer including at least one inorganic encapsulation layer and at least one organic encapsulation layer; a first partition wall and a second partition wall in a non-display area between the opening and the display area in a direction from the display area to the opening; and a plurality of grooves defined above the at least one inorganic insulating layer in the non-display area. The at least one inorganic insulating layer is on the substrate. At least one of the plurality of grooves is defined between the first partition wall and the second partition wall and is covered with the organic encapsulation layer.

Abstract: A display device, includes: a display panel including a first area, a second area spaced apart from the first area, and a bendable area between the first area and the second area; a window disposed on the display panel overlapping the first area; a protective layer disposed on the window including a first portion overlapping the bendable area; and an adhesive disposed between the window and the protective layer.

Abstract: A display apparatus includes a substrate on which a central area having a display area and a peripheral area disposed around the central area are defined. The display apparatus includes a display area inorganic layer on the display area and extending to a portion of the peripheral area; and an encapsulation inorganic layer covering the display area, on the display area inorganic layer, and having an edge that is in parallel with or extending over an edge of the display area inorganic layer.

Abstract: A light emitting device includes a transparent organic light emitting device and a quarter-wave plate. The transparent organic light emitting device includes a chiral complex emitter and produces circularly polarized light, and the quarter-wave plate converts the circularly polarized light into linearly polarized light. Generating linearly polarized light includes generating circularly polarized light via a transparent organic light emitting device including a chiral complex emitter, and passing the circularly polarized light through a quarter-wave plate to yield linearly polarized light.

Abstract: A display panel includes a first substrate, pixel structures, a first common pad, a second substrate, a second common electrode, a display medium and a conductive particle. The pixel structures are disposed on an active area of the first substrate. The first common pad is disposed on a peripheral area of the first substrate, and is electrically connected to first common electrodes of the pixel structures. The second common electrode is disposed on the second substrate. The conductive particle is disposed on the first common pad, and is electrically connected to the first common pad and the second common electrode. The conductive particle includes a core and a conductive film disposed on a surface of the core, where the conductive film has a main portion and raised portions, and a film thickness of each of the raised portions is greater than a film thickness of the main portion.

Abstract: A display device and a manufacturing method thereof are disclosed. The display device includes a base substrate and at least one pixel circuit provided on the base substrate. The pixel circuit includes a driving transistor, a first transistor, and a second transistor; the driving transistor includes a control electrode, a first electrode, and a second electrode; a direction from a first electrode of the first transistor to a second electrode of the first transistor is a first direction, a direction from a first electrode of the second transistor to a second electrode of the second transistor is a second direction, a direction from the first electrode of the driving transistor to the second electrode of the driving transistor is a fourth direction, and at least one of the first direction and the second direction intersects with the fourth direction.

Abstract: A display substrate has a display region and a peripheral region. The display substrate includes a substrate, a first dam, a second dam and a connection portion. The first dam and the second dam are located on a side of the substrate, and are located in the peripheral region. The second dam is farther from the display region than the first dam. A height of the second dam is greater than a height of the first dam. The connection portion is located between the first dam and the second dam. The connection portion connects the first dam and the second dam, and a height of the connection portion is less than the height of the first dam. At least a portion of the first dam, at least a portion of the connection portion and at least a portion of the second dam are of an integrative structure.

Abstract: A first electrode (110) has optical transparency, and a second electrode (130) has light reflectivity. An organic layer (120) is located between the first electrode (110) and the second electrode (130). Light-transmitting regions (a second region (104) and a third region (106)) are located between a plurality of light-emitting units (140). An insulating film (150) defines the light-emitting units (140) and includes tapers (152, 154). A sealing member (170) covers the light-emitting units (140) and the insulating film (150). A low reflection film (190) is located on the side opposite to a substrate (100) with the second electrode (130) therebetween. The low reflection film (190) covers at least one portion of the tapers (152 and 154).