Abstract: Provided is a semiconductor device including: a semiconductor substrate; an active portion provided on the semiconductor substrate; a first well region and a second well region arranged sandwiching the active portion in a top view, provided on the semiconductor substrate; an emitter electrode arranged above the active portion; and a pad arranged above the first well region, away from the emitter electrode, wherein the emitter electrode is provided above the second well region. The provided semiconductor device further includes a peripheral well region arranged enclosing the active portion in a top view, wherein the first well region and the second well region may protrude to the center side of the active portion rather than the peripheral well region.

Abstract: A method includes forming a semiconductor fin protruding above a substrate; forming a first 2D material layer across the semiconductor fin; depositing a gate material layer over the first 2D material layer; etching the gate material layer and the first 2D material layer to form a gate structure and a patterned first 2D material layer under the gate structure; laterally growing a second 2D material layer from the patterned first 2D material layer to beyond the gate structure; after laterally growing the second 2D material layer, forming gate spacers respectively on opposite sidewalls of the gate structure; and after forming the gate spacers, forming a third 2D material layer on the second 2D material layer until a combination of the third 2D material layer and the second 2D material layer comprises at least three or more monolayers of PtSe2.

Abstract: A High Electron Mobility Transistor (HEMT) includes a source, a drain, a channel layer extending between the source and the drain, a barrier layer formed in contact with the channel layer, and extending between the source and the drain, and a gate formed in contact with, and covering at least a portion of, the barrier layer. The gate has gate edge portions and a gate central portion, and dielectric spacers may be formed over the gate edge portions, with the dielectric spacers having a first width therebetween proximal to the gate, and a second width therebetween distal from the gate, where the second width is longer than the first width.

Abstract: A semiconductor device includes: a semiconductor substrate; a channel layer on the semiconductor substrate; a barrier layer on the channel layer; a gate electrode on the barrier layer via a gate insulating film; a source electrode and a drain electrode on the channel layer with the gate electrode interposed therebetween; a substrate opening that penetrates the channel layer and exposes the semiconductor substrate; an insulating film provided from upper parts of the gate electrode, the source electrode, and the drain electrode to an inner side of the substrate opening; and a wiring line layer on the insulating film, and electrically coupled to one of the gate electrode, the source electrode, and the drain electrode via an opening on the insulating film, in which at least a portion of the substrate opening is in an activation region in which the gate electrode, the source electrode, and the drain electrode are provided.

Abstract: In an embodiment, a HEMT is formed to have a main transistor having a main active area and a sense transistor having a sense active area. An embodiment may include that the main active area is isolated from the sense active area.

Abstract: Disclosed are a semiconductor structure and a manufacturing method therefor, solving the problem that it is difficult for an existing semiconductor structure to deplete a carrier concentration of a channel under a gate so as to achieve an enhancement-mode device. The semiconductor structure comprises: a channel layer and a barrier layer stacked in sequence. A gate region is defined on a surface of the barrier layer; a plurality of trenches formed in the gate region. The plurality of trenches are extended into the channel layer; and a stress applying material filled in the plurality of trenches. A lattice constant of the stress applying material is greater than that of the channel layer.

Abstract: A semiconductor power device includes a substrate; a buffer structure formed on the substrate; a barrier structure formed on the buffer structure; a channel layer formed on the barrier structure; and a barrier layer formed on the channel layer; wherein the barrier structure includes a first functional layer on the buffer structure, a second functional layer formed between the first functional layer and the buffer structure, a first back-barrier layer on the first functional layer, and an interlayer between the first back-barrier layer and the first functional layer; wherein a material of the first back-barrier layer includes Alx1Ga1-x1N, a material of the first functional layer includes Alx2Ga1-x2N, a material of the interlayer includes Alx3Ga1-x3N, a material of the second functional layer includes Alx4Ga1-x4N, wherein 0<x1?1, 0?x2?1, 0?x3?1, 0?x4<1, and x1?x2; and wherein the first functional layer includes a first thickness, the second functional layer includes a second thickness, and the second thic

Abstract: A semiconductor device includes: a substrate having a groove formed on a main surface; a drift region of a first conductivity type, the drift region having a portion disposed at a bottom part; a well region of a second conductivity type, the well region being disposed in one sidewall to be connected to the drift region; a first semiconductor region of the first conductivity type, the first semiconductor region being disposed on a surface of the well region in the sidewall to be away from the drift region; a second semiconductor region of the first conductivity type, the second semiconductor region being disposed to be opposed to the well region via the drift region; and a gate electrode opposed to the well region, the gate electrode being disposed in a gate trench that has an opening extending over the upper surfaces of the well region and the first semiconductor region.

Abstract: A power semiconductor device according to an aspect of the present disclosure includes a semiconductor layer of silicon carbide (SiC), a plurality of well regions that is disposed in the semiconductor layer, spaced from each other and has a second conductivity type, a plurality of source regions that are disposed in the semiconductor layer on the plurality of well regions respectively, spaced from each other, a drift region that has the first conductivity type and is disposed in the semiconductor layer, the drift region extending from a lower side of the plurality of well regions to a surface of the semiconductor layer through between the plurality of well regions, a plurality of trenches, a gate insulating layer, and a gate electrode layer that is disposed on the gate insulating layer.

Abstract: A compact vertical semiconductor device and a manufacturing method thereof, and an electronic apparatus including the semiconductor device are provided. According to the embodiments, the vertical semiconductor device may include: a plurality of vertical unit devices stacked on each other, in which the unit devices include respective gate stacks extending in a lateral direction, and each of the gate stacks includes a main body, an end portion, and a connection portion located between the main body and the end portion, and in a top view, a periphery of the connection portion is recessed relative to peripheries of the main body and the end portion; and a contact portion located on the end portion of each of the gate stacks, in which the contact portion is in contact with the end portion.

Abstract: A method for reducing stress induced defects in heterogeneous epitaxial interfaces of a semiconductor device is disclosed. The method includes forming a fin structure with a fin base, a superlattice structure on the fin base, forming a polysilicon gate structure on the fin structure, forming a source/drain (S/D) opening within a portion of the fin structure uncovered by the polysilicon gate structure, modifying the first surfaces of the first layers to curve a profile of the first surfaces, depositing first, second, and third passivation layers on the first, second, and third surfaces, respectively, forming an epitaxial S/D region within the S/D opening, and replacing the polysilicon gate structure with a metal gate structure. The superlattice structure includes first and second layers with first and second lattice constants, respectively, and the first and second lattice constants are different from each other.

Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.

Abstract: A thin film transistor and a manufacturing method thereof are provided. The thin film transistor includes a composite electrode including a barrier layer and an electrode layer. The barrier layer has a protruding part relative to the electrode layer, an orthographic projection of the protruding part on the composite electrode protrudes beyond an orthographic projection of the electrode layer on the composite electrode, and a length of the protruding part ranges from 0.3 um to 0.5 um. The thin film transistor and the manufacturing method thereof of the present disclosure can relieve light leakage, thereby improving a contrast ratio of products.

Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device in which first to third conductors are placed over a first oxide; first and second oxide insulators are placed respectively over the second and third conductors; a second oxide is placed in contact with a side surface of the first oxide insulator, a side surface of the second oxide insulator, and a top surface of the first oxide; a first insulator is placed between the first conductor and the second oxide; and the first oxide insulator and the second oxide insulator are not in contact with the first to third conductors, the first insulator, and the first oxide.

Abstract: An integrated circuit includes; a source region arranged in an upper portion of a substrate, a pair of split gate structures respectively on opposing sides of the source region, wherein each of the pair of split gate structures includes a floating gate electrode layer and a control gate electrode layer disposed on the floating gate electrode layer, an erase gate structure between the pair of split gate structures on the source region and including an erase gate electrode layer, a pair of selection gate structures respectively on outer sidewalls of the pair of split gate structures, and a pair of gate spacers, wherein each of the gate spacers is disposed between one of the pair of split gate structures and one of the pair of selection gate structures, includes a first gate spacer and a second gate spacer disposed on the first gate spacer, is further disposed on an outer side wall of the one of the pair of split gate structures, and a lowermost end of the second gate spacer is at a lower level than an upper sur

Abstract: A method of using a diode device including providing a diode that includes an active region including a 525 micron thick. 10 k?-cm, n-type, float zone wafer, and operating the diode as a silicon-avalanche semiconductor switch.

Abstract: A dielectric substrate has a first surface including a first terminal connector and a second terminal connector located along a first side surface. A recess is between the first terminal connector and the second terminal connector. The recess has a first inner surface continuous with the first terminal connector, a second inner surface continuous with the second terminal connector, and a bottom surface between the first inner surface and the second inner surface. The first terminal connector has first wettability with a bond on its surface, and a first region has second wettability with the bond on its surface lower than the first wettability.

Abstract: A light shielding structure of an optical circuit of the present invention uses a part of the structure of the light reception element itself to suppress stray light. A stepped electrode that covers an upper surface and side surface of a first semiconductor layer constituting a light absorption portion of the light reception element is formed at a height substantially equal to that of an optical waveguide in the optical circuit, and the light absorption portion of the light reception element is shielded from stray light by a wall-shaped or column-shaped wiring electrode extending substantially perpendicularly to a surface layer of the optical circuit. The light shielding structure of the present invention uses a part of the configuration of the light reception element, is formed integrally with the light reception element, and also has an aspect of the invention of the light reception element.

Abstract: In accordance with at least one aspect of this disclosure, a thermal management system for an electronics assembly includes, a reservoir housing a compressible fluid in a compressed state, a throttling orifice disposed in fluid communication with the reservoir and configured to expand the compressible fluid, cooling the compressible fluid, and a heat exchange volume in fluid communication with the throttling orifice to receive cooled compressible fluid from the throttling orifice.

Abstract: A detection device includes a photoelectric conversion portion in which a plurality of photodiodes are arranged in a planar shape, a light source configured to irradiate the photodiodes with light, and a heating electrode provided so as to face the photoelectric conversion portion, and configured to generate heat and conduct the heat to the photoelectric conversion portion.

Abstract: Provided is a thermally conductive and electrically insulating paint composition, and an exterior steel sheet for a solar cell, comprising same. Specifically, the thermally conductive and electrically insulating paint composition includes: a first mixture, which comprises a thermoplastic resin and a thermally conductive filler, a polymer dispersant, and a first hydrocarbon-based solvent; and an exterior steel sheet for a solar cell, comprising: a steel sheet on which a heat dissipation layer is formed on one surface thereof; and a thermally conductive and electrically insulating coating layer which comprises a thermoplastic resin, a thermally conductive filler and a polymer dispersant, and which is formed on the other surface of the steel sheet, wherein the thermally conductive filler is dispersed in the coating layer in a form of being encompassed by the polymer dispersant.

Abstract: The present disclosure relates to a photovoltaic (PV) device that includes a first junction constructed with a first alloy and having a bandgap between about 1.0 eV and about 1.5 eV, and a second junction constructed with a second alloy and having a bandgap between about 0.9 eV and about 1.3 eV, where the first alloy includes III-V elements, the second alloy includes III-V elements, and the PV device is configured to operate in a thermophotovoltaic system having an operating temperature between about 1500° C. and about 3000° C.

Abstract: Device structures, apparatuses, and methods are disclosed for photovoltaic cells that may be a single-junction or multijunction solar cells, with at least a first layer comprising a group-IV semiconductor in which part of the cell comprises a second layer comprising a III-V semiconductor or group-IV semiconductor having a different composition than the group-IV semiconductor of the first layer, such that a heterostructure is formed between the first and second layers.

Abstract: A package includes: a bottom portion having a mounting surface; and a lateral wall portion having a top surface and including: a lateral wall having a rectangular outer shape in a top view and surrounding the mounting surface, and a stepped portion formed along the lateral wall below the top surface. In the top view, the stepped portion includes a wide portion and a narrow portion that are two regions having different widths. The narrow portion is formed on a portion along a one side of an entire circumference of the lateral wall.

Abstract: A vertical current mode solid state device comprising a connection pad and side walls comprising a metal-insulator-semiconductor (MIS) structure, wherein leakage current effect of the vertical device is limited through the side walls by biasing the MIS structure.

Abstract: A method for manufacturing a light-emitting element, includes: introducing a gas comprising gallium, an ammonia gas, and a gas comprising a p-type impurity to a reactor and forming a first p-type nitride semiconductor layer on a first light-emitting layer in a state in which the reactor has been heated to a first temperature; introducing an ammonia gas at a first flow rate and a nitrogen gas to the reactor in a state in which the reactor is held at the first temperature; and subsequently introducing a gas comprising gallium, an ammonia gas at a second flow rate, and a gas comprising an n-type impurity to the reactor, and forming a second n-type nitride semiconductor layer on the first p-type nitride semiconductor layer. The first flow rate is less than the second flow rate.

Abstract: A method utilizes a target substrate has an array of chips on a carrier with a plurality of vacancies and a plurality of donor coupons are incompletely filled with functional chips. A bounding box is defined that encompasses the vacancies on the target substrate. Outcomes are simulated by overlapping a representation of the bounding box over a representation of each of a plurality of donor coupons at a plurality of translational offsets on a substrate plane to determine matches. An optimal one of the outcomes is found at a selected one or more of the donor coupons corresponding one or more offsets. A parallel transfer of the matching functional chips fills the vacancies on the target substrate using the one or more selected donor coupons and corresponding one or more offsets.

Abstract: A single-photon source includes a substrate of a wide-bandgap semiconductor provided with a light-emission region including only one target point detect, a cover mask arranged on a main surface of the substrate and having an opening to which the light-emission region in the substrate is exposed, and an excitation system configured to shift an electron in a defect-ground state to an excited state at the point defect in the light-emission region. A single photon released from the point defect in the light-emission region when the electron in the excited state is shifted to the ground state is output through the opening in the cover mask.

Abstract: Provided is a display device including a light emitting unit that can emit a plurality of types of light having different wavelengths to the outside at a desired ratio with high intensity without increasing manufacturing costs in proportion to a number of pixels even when the number of pixels increases. Provided is a display device including a light emitting unit in which a plurality of types of PiN junction-type light emitting diodes that emit light having different wavelengths are arranged on the same substrate, and at least one type among the plurality of types of light emitting diodes has an active layer containing a rare earth element. Provided is a display device in which a plurality of types of light emitting diodes are sequentially stacked on the surface of a substrate, and a light emitting layer for one color is formed to overlap at least a portion of a light emitting layer for another color.

Abstract: A light-emitting device includes: a substrate having a top surface, wherein the top surface comprises a first portion and a second portion; a first semiconductor stack on the first portion, comprising a first upper surface and a first side wall; and a second semiconductor stack on the first upper surface, comprising a second upper surface and a second side wall, and wherein the second side wall connects the first upper surface; wherein the first semiconductor stack comprises a dislocation stop layer; wherein the dislocation stop layer comprises AlGaN; and wherein the first side wall and the second portion of the top surface form an acute angle ? between thereof.

Abstract: A first semiconductor device of an embodiment of the present disclosure includes: a semiconductor substrate having one surface and another surface opposed to each other, and having a side length of 50 ?m or more and 500 ?m or less; a single or multiple bumps provided on the other surface; and a projection-and-depression structure formed in a side surface of the semiconductor substrate.

Abstract: A display device comprises a planarization layer disposed on a substrate, a first alignment electrode and a second alignment electrode that extend in a first direction and are spaced apart from each other on the planarization layer, a first insulating layer disposed on the first alignment electrode and the second alignment electrode and comprising a first opening exposing the planarization layer between the first alignment electrode and the second alignment electrode, a light-emitting element disposed on the planarization layer overlapping the first opening, a first contact electrode and a second contact electrode disposed on the first insulating layer, the first contact electrode electrically contacting a first end of the light-emitting element and the second contact electrode electrically contacting a second end of the light-emitting element, and a second insulating layer disposed on the light-emitting element.

Abstract: A light-emitting element includes: a semiconductor stack having a triangular shape in a top plan view, the semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer between the first and seconds semiconductor layers; a first electrode located on the first semiconductor layer and including a first connecting portion and a first extension extending from the first connecting portion; and a second electrode located on the second semiconductor layer and including a second connecting portion and a second extension extending from the second connecting portion. The first extension includes a first portion extending from the first connecting portion toward the second connecting portion. The second extension includes a second portion including a portion extending along a first side, a third portion including a portion extending along a second side, and fourth and fifth portions each including a portion extending along a third side.

Abstract: A light emitting element includes: a semiconductor structure; first and second electrodes formed above the semiconductor structure; and a protective film. In a plan view: the first electrode has a first connecting portion, a first extending portion, and two second extending portions, the second electrode has a second connecting portion, and two third extending portions, the first extending portion extends linearly in a direction from the first connecting portion toward the second connecting portion, the two second extending portions are located on opposite sides of the first extending portion, respectively, with each of the second extending portions having two bent portions and a linear portion extending parallel to the first extending portion and located between the two bent portions, and the two third extending portions are located between the first extending portion and the two second extending portions, respectively.

Abstract: A phosphor substrate having at least one light emitting element mounted on one surface, and includes an insulating substrate, an electrode layer disposed on one surface of the insulating substrate and bonded to the light emitting element, and a phosphor layer which is disposed on one surface of the insulating substrate and includes a phosphor in which a light emission peak wavelength, in a case where light emitted by the light emitting element is used as excitation light, is in a visible light region, in which a surface of the electrode layer facing an outer side in a thickness direction of the insulating substrate is a flat surface, and at least a part of the phosphor layer is disposed around a bonded portion of the electrode layer with the light emitting element.

Abstract: Provided are a wavelength conversion member, a light-emitting element, and a light-emitting device which have high heat dissipation capability and are capable of reducing the decrease in luminescence intensity caused by increased output of an excitation light source. A wavelength conversion member 10 includes a matrix 2 and an inorganic phosphor 1 contained in the matrix 2 and has a relative density of 90% or more, a thermal conductivity of 10 W/m·K or more, and a quantum efficiency of 50% or more.

Abstract: A method for manufacturing an image display device including providing a plurality of first subpixels and a second subpixel, where the plurality of first subpixels have a plurality of first light-emitting elements and are configured to emit red, green, and blue light, and the second subpixel has a second light-emitting element and being configured to emit blue light. A defective subpixel detection process includes turning on the plurality of first light-emitting elements, and acquiring data of position of at least one defective subpixel among the plurality of first subpixels, where the defective subpixel is supposed to emit predetermined light with a predetermined color. A wavelength conversion layer formation process includes providing a wavelength conversion layer over the second light-emitting element to convert emission light emitted from the second light-emitting element to the predetermined light with the predetermined color if the predetermined color is red or green.

Abstract: A light-emitting device according to one embodiment of the present disclosure includes: a reflective structure having a first surface and a second surface and having, on the first surface, an opening whose side surface is provided with a first reflective film; a semiconductor light-emitting element including a first conductivity-type layer, an active layer, and a second conductivity-type layer that are stacked, the opening of the reflective structure and the active layer being disposed to be opposed to each other; and a support member having a light-transmitting property and having a first surface and a second surface, the semiconductor light-emitting element being disposed on the first surface side, the reflective structure being disposed on the second surface side, the second surface being at least partially in contact with the first surface of the reflective structure.

Abstract: The present disclosure relates to an electronic component joining method and a joined structure. A solder layer made of a gold-tin alloy including 20 mass % or greater of tin is formed on a light-emitting element side, and a layer including gold as a main component is formed, as a joining layer for joining to the solder layer, on a submount side. The solder layer and the joining layer are heated at a temperature below the melting point of the gold-tin alloy of the solder layer to join the light-emitting element and the submount.

Abstract: Embodiments relate to forming an elastomeric interface layer (elayer) with a flap over multiple light emitting diode (LED) dies by forming materials across multiple LED dies and removing the materials between the LED dies. The formed flap of the elayer provides a large surface area for adhesion between each LED and a pick-up surface. For example, the flap may have a surface area that is larger than the light emitting surface of the LED die, or larger than the surface area of an elastomeric interface layer without the flap. As such, the elayer allows each LED to be picked up by a pick-up surface and placed onto a display substrate including control circuits for sub-pixels of an electronic display. In some embodiments, the LED dies are micro-LED (?LED) dies.

Abstract: Discussed are an apparatus and a method for manufacturing an electrode assembly. The apparatus for manufacturing the electrode assembly includes a heater unit configured to heat a laminate of an electrode and a separator when the laminate passes therethrough, a lamination device configured to laminate the laminate that is heated while passing through the heater unit, and a moving unit configured to allow the laminate to be spaced a predetermined distance from the heater unit so that heat transferred from the heater unit to the laminate is reduced or blocked when an operation of the lamination device is stopped.

Abstract: Electrochemical cells and methods of making electrochemical cells are described herein. In some embodiments, an apparatus includes a multi-layer sheet for encasing an electrode material for an electrochemical cell. The multi-layer sheet including an outer layer, an intermediate layer that includes a conductive substrate, and an inner layer disposed on a portion of the conductive substrate. The intermediate layer is disposed between the outer layer and the inner layer. The inner layer defines an opening through which a conductive region of the intermediate layer is exposed such that the electrode material can be electrically connected to the conductive region. Thus, the intermediate layer can serve as a current collector for the electrochemical cell.

Abstract: Disclosed is a battery cell, a battery, an electric apparatus, and a manufacturing method of the battery, belonging to the technical field of batteries. The battery includes an electrode assembly, an electrode terminal and a current collector, the current collector is configured to connect the electrode assembly and the electrode terminal; where the current collector and the electrode terminal are connected through a welding portion; and the welding portion is exposed at an external peripheral surface of the current collector and/or an external peripheral surface of the electrode terminal. The battery cell, the battery, the electric apparatus, and the manufacturing method of the battery are capable of ensuring the safety of the battery.

Abstract: The present invention relates to a lithium secondary battery which includes a non-aqueous electrolyte solution including lithium bis(fluorosulfonyl)imide (LiFSI) and a fluorobiphenyl compound, a positive electrode including a lithium-nickel-manganese-cobalt-based oxide as a positive electrode active material, a negative electrode, and a separator.

Abstract: A Li-ion battery cell includes cathode and anode materials, a separator, and an electrolyte including a mixture of a polyethylene oxide and an oxide of formula LivLasZnOn. A method of forming the cell includes the following successive cycling steps: (a) at least two successive charge and discharge cycles of the cell at a first cycling rate C/x, the charge/discharge steps being limited in time to x/2; (b) at least two successive charge and discharge cycles of the cell at a second charging rate C/y, different from the first cycling rate, where y is lower than x, the charge/discharge steps being limited in time to y/2; and (c) at least two successive charge and discharge cycles of the cell at a third cycling rate C/z different from the first and second charging rates, where z is lower than x and y, the charge/discharge steps being limited in time to z/2.

Abstract: The present invention provides a method for the fabrication of a LaZrGa(OH)x metal hydroxide precursor with a co-precipitation method in a continuous TFR. The present invention also provides a method for the fabrication of an ion-doped all-solid-state lithium-ion conductive material with lithium ionic conductivity, and mixing with the polymer-based material, then using a doctor-blade coating method to prepare free-standing double- or triple-layered organic-inorganic hybrid solid electrolyte membranes. Furthermore, the present invention provides an all-solid-state lithium battery using the aforementioned hybrid solid electrolyte membrane and the electrochemical performance of the all-solid-state lithium battery.

Abstract: A lithium-ion secondary battery includes: a single cell that includes a first electrode, a separator stacked on the first electrode, and a second electrode stacked on the separator. The first electrode includes a porous body that includes at least one LLZ-based solid electrolyte of a lithium lanthanum zirconate or the lithium lanthanum zirconate doped with an atom other than a Li atom, a La atom, and a Zr atom, and has a pore, and an active material held in the pore. The separator has a relative density of 80% or more, and includes the at least one LLZ-based solid electrolyte of the lithium lanthanum zirconate or the lithium lanthanum zirconate doped with the atom other than the Li atom, the La atom, and the Zr atom, and at least one of a B atom, a P atom, or a Si atom.

Abstract: To provide a solid-state battery module and a separator which can apply sufficient surface pressure to a solid-state battery cell and are excellent in durability and vibration resistance. A separator (120) disposed between adjacent solid-state battery cells (101) in a solid-state battery module (100) including a plurality of solid-state battery cells (101) to electrically insulate the adjacent solid-state battery cells (101) of the plurality of solid-state battery cells (101), from each other. The separator (120) includes elastically deformable elastic members (123a, 123b) which apply biasing force in the stacking directions of the plurality of solid-state battery cells (101). Durability and vibration resistance can be obtained by adequately fixing the solid-state battery cells (101) with the elastic members (123a, 123b).

Abstract: A solid electrolyte material according to the present disclosure consists essentially of Li, M, O, and X. M is at least one element selected from the group consisting of Nb and Ta, and X is at least one element selected from the group consisting of Cl, Br, and I.

Abstract: Provided is an electrolyte of a lithium-sulfur battery. The electrolyte of the lithium-sulfur battery may include: a base electrolyte including lithium salt and an organic solvent; and an electrolyte additive, in which the electrolyte additive includes a metal nitrate.