Abstract: This application provides an integrated circuit device and a preparation method thereof, and relates to the field of semiconductor technologies. An isolation section for suppressing a leakage current path of two adjacent transistors may be formed by using a simple process. The integrated circuit device includes a substrate and a fin protruding from the substrate. The integrated circuit device further includes two adjacent transistors. The two adjacent transistors use two spaced segments on the fin as respective channels of the two adjacent transistors. A part that is of the fin and that is located between the two spaced segments is processed to obtain an isolation section. The isolation section is used to suppress current transfer between the two channels of the two adjacent transistors.

Abstract: A method for manufacturing a semiconductor device structure including a doped region under an isolation feature. The method includes providing a substrate having a first surface and a second surface opposite to the first surface, wherein the substrate comprises a first well region with a first conductive type; forming an isolation feature extending from the second surface of the substrate; forming a first transistor and a second transistor adjacent to the second surface of the substrate; forming a first doped region under the isolation feature, wherein the first doped region has a second conductive type different from the first conductive type; and providing a circuit structure on the first surface of the substrate, wherein the circuit structure is configured to transmit or provide a voltage electrically coupled with the first doped region.

Abstract: A method of fabricating a fin-like field effect transistor (FinFET) device includes providing a semiconductor substrate having a region for forming p-type metal-oxide-semiconductor (PMOS) devices and a region for forming n-type metal-oxide-semiconductor (PMOS) devices, forming fin structures in both regions of the substrate separated by isolation features, first forming source/drain (S/D) features in the PMOS region, and subsequently forming S/D features in the NMOS region. First forming the PMOS S/D features and then forming the NMOS S/D features results in a greater extent of loss of isolation features in the PMOS region than in the NMOS region.

Abstract: Methods for the manufacture of three-dimensional (3D) semiconductor devices are disclosed. Aspects can include forming a patterned first conductive source/drain structure of a transistor structure, forming a gate patterned conductive structure of the transistor structure separated from the first conductive source/drain structure by at least one dielectric layer, forming a patterned second conductive source/drain structure of the transistor structure separated from the gate patterned conductive structure by at least one dielectric layer, forming a transistor body opening extending through the transistor structure, forming a gate dielectric in the transistor body opening, and forming a material in the transistor body opening extending from the patterned first conductive source/drain structure to the patterned second conductive source/drain structure.

Abstract: Embodiments of the present disclosure are based on extending a nanocomb transistor architecture to implement gate all around, meaning that a gate enclosure of at least a gate dielectric material, or both a gate dielectric material and a gate electrode material, is provided on all sides of each nanoribbon of a vertical stack of lateral nanoribbons of a nanocomb transistor arrangement. In particular, extension of a nanocomb transistor architecture to implement gate all around, proposed herein, involves use of two dielectric wall materials which are etch-selective with respect to one another, instead of using only a single dielectric wall material used to implement conventional nanocomb transistor arrangements. Nanocomb-based transistor arrangements implementing gate all around as described herein may provide improvements in terms of the short-channel effects of conventional nanocomb transistor arrangements.

Abstract: A method of qualifying semiconductor wafer processing includes: illuminating a semiconductor wafer simultaneously with source light having wavelengths in a plurality of wavebands, including at least a first waveband and a second waveband, the second waveband being different from the first waveband; separating light reflected from the semiconductor wafer as a result of said illuminating, the separating dividing the reflected light according to waveband; generating a first image of the semiconductor wafer based on reflected light separated into the first waveband; and, generating a second image of the semiconductor wafer base on reflected light separated into the second waveband.

Abstract: A method of controlling plasma includes providing a plasma processing apparatus that includes N microwave introducing radiators disposed in a circumferential direction of a ceiling plate of a processing container so as to introduce microwaves for generating plasma into the processing container, wherein N?2; and M sensors and configured to monitor at least one of electron density Ne and electron temperature Te of the plasma generated in the processing container, wherein M equals to N or a multiple of N. The method further includes controlling at least one of a power and a phase of the microwaves introduced from the microwave introducing radiators based on at least one of electron density Ne and electron temperature Te of the plasma monitored by the M sensors.

Abstract: A power module includes a housing having a carrier plate, housing walls and a housing cover. Semiconductor elements and a temperature sensor unit having a temperature sensor are disposed in the interior of the housing on the carrier plate. Partitions disposed in the interior of the housing separate the temperature sensor unit from the semiconductor elements and enclose the temperature sensor unit in a chamber.

Abstract: A package substrate that prevents breakage of a core substrate is provided. A package substrate includes a core substrate made of a brittle material, at least one insulating layer formed on one surface or both surfaces of the core substrate, and one or more wiring layers formed on the insulating layer and/or in the insulating layer, the core substrate being exposed from an outer peripheral portion of the insulating layer, and the insulating layer being chamfered.

Abstract: An electronic package is provided, in which an electronic component with a conductive layer on an outer surface thereof is embedded in an encapsulant, where at least one electrode pad is disposed on an active surface of the electronic component, and at least one wire electrically connected to the electrode pad is arranged inside the electronic component, so that the conductive layer is electrically connected to the wire, such that the electrode pad, the wire and the conductive layer are used as a power transmission structure which serves as a current path to reduce DC resistance and improve an impedance issue associated with the supply of power.

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, a conductive terminal, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The conductive terminal is connected to the redistribution layer. The through via extends through the encapsulant and the redistribution layer to contact the conductive terminal and the second RDL structure.

Abstract: A chip package including a semiconductor chip is provided. The chip package may include a packaging material at least partially around the semiconductor chip with an opening extending from a top surface of the packaging material to the semiconductor chip and/or to an electrical contact structure contacting the semiconductor chip, and a thermally conductive material in the opening, wherein the thermally conductive material is configured to transfer heat from the semiconductor chip to an outside, wherein the thermally conductive material extends laterally at least partially over the top surface of the packaging material.

Abstract: A display panel and a manufacturing method thereof are provided. In the manufacturing method of the display panel, a corner-cutting area of a to-be-cut display panel is provided with a cutting groove. The cutting groove penetrates a buffer layer and extends into a flexible substrate. Furthermore, the cutting groove is provided with an inorganic encapsulation layer and a sacrificial layer. Therefore, when cutting the to-be-cut display panel along the cutting groove, cracks generated during a process can be reduced, thereby alleviating a problem of micro-cracks affecting a packaging effect of conventional display panels during a secondary cutting process.

Abstract: Exemplary embodiments provide thermal wear spreading among a plurality of thermal die regions in an integrated circuit or among dies by using die region wear-out data that represents a cumulative amount of time each of a number of thermal die regions in one or more dies has spent at a particular temperature level. In one example, die region wear-out data is stored in persistent memory and is accrued over a life of each respective thermal region so that a long term monitoring of temperature levels in the various die regions is used to spread thermal wear among the thermal die regions. In one example, spreading thermal wear is done by controlling task execution such as thread execution among one or more processing cores, dies and/or data access operations for a memory.

Abstract: A multichannel transistor is provided. In the transistor, a plurality of gate fingers overlie a substrate and extend laterally across the substrate from a gate manifold. The gate manifold has a curved edge, and each of the gate fingers projects radially from the curved manifold edge.

Abstract: A semiconductor device includes a semiconductor module, an insulating resin layer, a frame member, and a heat sink. Insulating resin layer is bonded to semiconductor module and contains a first resin. Frame member is disposed to surround insulating resin layer, and includes a porous material. Heat sink and semiconductor module sandwich insulating resin layer and frame member. Frame member is compressed while being sandwiched between semiconductor module and heat sink. Insulating resin layer is filled in a region surrounded by semiconductor module, heat sink, and frame member. The first resin enters pores of the porous material.

Abstract: A package structure includes a semiconductor package, a thermal conductive gel, a thermal conductive film and a heat spreader. The thermal conductive gel is disposed over the semiconductor package. The thermal conductive film is disposed over the semiconductor package and the thermal conductive gel. A thermal conductivity of the thermal conductive film is different from a thermal conductivity of the thermal conductive gel. The thermal conductive film is surrounded by the heat spreader.

Abstract: A heat sink integrated insulating circuit substrate includes: a heat sink including a top plate part and a cooling fin; an insulating resin layer formed on the top plate part of the heat sink; and a circuit layer made of metal pieces arranged on a surface of the insulating resin layer opposite to the heat sink, wherein, when a maximum length of the top plate part is defined as L, an amount of warpage of the top plate part is defined as Z, and deformation of protruding toward a bonding surface side of the top plate part of the heat sink is defined as a positive amount of warpage, and a curvature of the heat sink is defined as C=|(8×Z)/L2|, a ratio P/Cmax between a maximum curvature Cmax(I/m) of the heat sink during heating from 25° C. to 300° C. and peel strength P (N/cm) of the insulating resin layer satisfies P/Cmax>60.

Abstract: An interface interconnect structure is provided for efficient heat dissipation of a power electronic device. The structure includes a first low temperature solder layer and a second low temperature solder layer, a metal-foam metal composite material is placed between the first low temperature solder layer and the second low temperature solder layer. The metal-foam metal composite material has designability in structure and performance. The thermal conductivity and coefficient of thermal expansion (CTE) of the thermal interface interconnect structure can be configured according to the selected encapsulating materials for a power electronic device, thereby achieving bisynchronous improvement in the heat dissipation efficiency and the CTE matching degree between the encapsulating materials.

Abstract: Described examples include a process that includes forming a diffusion barrier layer on a backside of a semiconductor wafer. The process also includes forming a seed copper layer on the diffusion barrier layer. The process also includes forming a copper layer on the seed copper layer. The process also includes immersion plating a silver layer on the copper layer.

Abstract: Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled to a surface thereof. A dummy die, adjacent to an IC die and coupled to a region of the substrate, comprises a polymer resin and a filler. A package mold structure of the packaged device adjoins respective sides of the IC die and the dummy die, and adjoins the surface of the substrate. In another embodiment, a first CTE of the dummy die is less than a second CTE of the package mold structure, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the package mold structure.

Abstract: A heatsink assembly comprising a substrate having an active circuitry, at least one cavity located adjacent to at least one heat producing element of the active circuitry, at least one vessel sealably coupled to said substrate in fluid communication with the at least one cavity, and a phase change material (PCM) contained inside the vessel. The vessel and at least one cavity configured to facilitate migration of the PCM from the vessel into the at least one cavity for absorbing heat produced by the at least one heat producing element of the active circuitry.

Abstract: A semiconductor package includes a semiconductor die, a thermal conductive through via and a conductive paste. The thermal conductive through via is electrically insulated from the semiconductor die. The conductive paste is disposed over the semiconductor die, wherein the thermal conductive through via is thermally coupled to the semiconductor die through the conductive paste.

Abstract: A device is provided that includes a heat conductive structure; a heat transfer structure for extracting heat from the heat conductive structure by means of a boundary layer; a motor for rotating the heat transfer structure relative to the heat conductive structure; and a vertical fixing mechanism for allowing the heat transfer structure to rotate above the heat transfer structure without making contact with the heat transfer structure so as to define a boundary layer between the heat conductive structure and heat transfer structure, wherein the heat transfer structure extracts heat from the heat conductive structure by means of the boundary layer, and wherein the heat conductive structure includes small geometric turbulators.

Abstract: A semiconductor device assembly includes a cooling system, a plurality of semiconductor packages, each including a semiconductor die and an encapsulant body, and a multi-device thermal interface interposed between the plurality of semiconductor packages and the cooling system, wherein the semiconductor packages are each configured as surface mount devices, and wherein the multi-device thermal interface thermally couples each of the semiconductor packages to the cooling system.

Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.

Abstract: A leadless semiconductor package includes a conductive base having a plurality of apertures formed around a perimeter of the conductive base and extending from a first surface to an opposing second surface of the conductive base. The semiconductor package further includes an IC die having a third surface facing the first surface of the conductive base and having a plurality of conductive pillars disposed thereon. Each conductive pillar extends from the third surface to the first surface via a corresponding aperture. A dielectric fill material is disposed in the apertures and insulates the conductive pillars from the conductive material of the conductive base. An opening of an aperture at the second surface, the bottom end of the conductive pillar disposed therein, and the dielectric fill material at the opening of the aperture at the second surface together form a surface mount pad for mounting the semiconductor package to a corresponding pad of a circuit board.

Abstract: A semiconductor device includes a first die pad, a second die pad, a first semiconductor element, a second semiconductor element, an insulating element, first terminals, second terminals, and a sealing resin. The sealing resin has a first side surface located on one side of a first direction, a second side surface located on the other side of the first direction, and third and fourth side surfaces that are separated from each other in a second direction orthogonal to both a thickness direction and the first direction and are connected to the first and second side surfaces. A first gate mark having a surface roughness larger than the other regions of the third side surface is formed on the third side surface. When viewed along the second direction, the first gate mark overlaps a pad gap provided between the first die pad and the second die pad in the first direction.

Abstract: A semiconductor module includes a conductive substrate, a semiconductor element, a control terminal, and a sealing resin. The conductive substrate has an obverse surface and a reverse surface that are spaced apart from each other in a thickness direction. The semiconductor element is electrically bonded to the obverse surface and has a switching function. The control terminal is configured to control the semiconductor element. The sealing resin has a resin obverse surface and a resin reverse surface, and covers the conductive substrate, the semiconductor element, and a part of the control terminal. The control terminal protrudes from the resin obverse surface, and extends along the thickness direction.

Abstract: Semiconductor packages are described which increase the density of electronic components within. The semiconductor package may incorporate interposers with cavities formed into the top and/or bottom. The cavities may then be used as locations for the electronic components. Alternatively, narrow spacer interposers may be used to space apart standard more laterally elongated interposers to form the indentations used to house the electronic components. The semiconductor package designs described herein may be used to reduce footprint, reduce profile and increase electronic component and transistor density for semiconductor products.

Abstract: An integrated circuit (IC) package includes a one or more die and an interposer. The interposer is coupled to the die and includes circuit traces. The circuit traces are provided in a serpentine configuration. A method can be used to fabricate an integrated circuit package. The method can use an interposer circuit traces having a configuration that allows the circuit traces to deform under stress, and return to an original state undamaged more readily than a straight conductive trace.

Abstract: Provided are an adapter board and a method for forming the same, a packaging method, and a package structure. One form of a method for forming an adapter board includes: providing a base, including an interconnect region and a capacitor region, the base including a front surface and a rear surface that are opposite each other; etching the front surface of the base, to form a first trench in the base of the interconnect region and form a second trench in the base of the capacitor region; forming a capacitor in the second trench; etching a partial thickness of the base under the first trench, to form a conductive via; forming a via interconnect structure in the conductive via; and thinning the rear surface of the base, to expose the via interconnect structure.

Abstract: A semiconductor structure includes an interposer substrate, an electronic device formed in a device region of the interposer substrate, a guard ring formed in the interposer substrate and surrounding the device region, a first redistribution layer on an upper surface of the interposer substrate and covering the device region and the guard ring, and a chip disposed on the first redistribution layer and overlapping the device region.

Abstract: Semiconductor device A1 includes: semiconductor element 1 turning on and off connection between drain electrode 11 and source electrode 12; semiconductor element 2 turning on and off connection between drain electrode 21 and source electrode 22; metal component 31 with semiconductor element 1 mounted; metal component 32 with semiconductor element 2 mounted; and conductive substrate 4 including wiring layers 411, 412 with insulating layer 421 between them. Wiring layer 411 includes power terminal section 401 connected to drain electrode 11. Wiring layer 412 includes power terminal section 402 connected to source electrode 22. Power terminal sections 401, 402 and insulating layer 421 overlap with each other as viewed in z direction. Conductive substrate 4 surrounds semiconductor elements 1, 2 as viewed in z direction, while overlapping with a portion between metal components 31, 32 as viewed in z direction.

Abstract: An electronic module includes a wiring board including a lower surface on which a second electrode pad including a bonding surface is located, a lead electrically connected to the second electrode pad with solder therebetween, and a sealer to seal the lead. The lead includes an exposed section exposed to outside the sealer and a main body section extending from the exposed section toward the wiring board and including a tip end portion near the wiring board. The tip end portion is connected to the second electrode pad with the solder therebetween. A thickness of the solder between a tip end surface of the tip end portion and the bonding surface of the second electrode pad in a direction orthogonal or substantially orthogonal to the bonding surface is non-uniform.

Abstract: An apparatus including; a substrate; an isolator that is formed over the substrate, the isolator including a silicon shield layer that is formed between a first buried oxide (BOX) layer and a second BOX layer; a silicon layer having an oxide trench structure formed therein, the oxide trench structure being arranged to define a first silicon island and a second silicon island; a first electronic circuit that is formed over the first silicon island; and a second electronic circuit that is formed over the second silicon island, the first electronic circuit being electrically coupled to the first electronic circuit.

Abstract: A metal oxide metal (MOM) capacitor and methods for fabricating the same are disclosed. The MOM capacitor includes a first metal layer having a first plurality of fingers, each of the first plurality of fingers configured to have alternating polarities. A high resistance (Hi-R) conductor layer is disposed adjacent the first metal layer in a plane parallel to the first metal layer.

Abstract: A semiconductor structure includes: a substrate and a dielectric layer arranged on the substrate; a conductive plug, a first portion of the conductive plug being arranged in the substrate, and a second portion of the conductive plug being arranged in the dielectric layer; and a capacitor array, the capacitor array at least surrounding the second portion of the conductive plug.

Abstract: Memory devices can be structured in a three-dimensional arrangement using a circuit under array (CUA) architecture. The memory array of such a memory device can include memory cells disposed in vertically arranged tiers. With the memory array extending over a substrate, the CUA region under the memory array can include control circuitry for the memory array. A space adjacent the memory array and disposed above the CUA region can include a dielectric material and conductive structures, with the conductive structures extending vertically in the dielectric material and alongside the memory array. The conductive structures separated by the dielectric material can be used as a capacitor coupled between nodes with the nodes configured to provide different voltages. This capacitor can be coupled to a circuit or a connection node below the level of the memory array.

Abstract: One or more embodiments of techniques or systems for forming a semiconductor structure are provided herein. A first metal region is formed within a first dielectric region. A cap region is formed on the first metal region. A second dielectric region is formed above the cap region and the first dielectric region. A trench opening is formed within the second dielectric region. A via opening is formed through the second dielectric region, the cap region, and within some of the first metal region by over etching. A barrier region is formed within the trench opening and the via opening. A via plug is formed within the via opening and a second metal region is formed within the trench opening. The via plug electrically connects the first metal region to the second metal region and has a tapered profile.

Abstract: A semiconductor device including a gate pattern on a substrate and including a gate dielectric layer, a gate electrode, and a gate capping pattern that are sequentially stacked; a gate spacer on a sidewall of the gate pattern; a source/drain pattern in the substrate; a contact pad on the source/drain pattern, a source/drain contact on the contact pad; and a buried dielectric pattern between the gate spacer and the source/drain contact, wherein the gate spacer includes a first segment between the gate electrode and the source/drain pattern; a second segment that extends from the first segment and between the gate electrode and the source/drain contact; and a third segment on the second segment, the buried dielectric pattern is between the third segment and the source/drain contact, and is absent between the first segment and the contact pad and is absent between the second segment and the source/drain contact.

Abstract: A semiconductor storage device includes a first wiring layer, a first insulating layer on the first wiring layer, a second wiring layer on the first insulating layer, a second insulating layer on the second wiring layer, a third wiring layer on the second insulating layer, and a first pillar that passes through the first, second, and third wiring layers and the first and second insulating layers along a first direction and includes a first semiconductor layer. A first distance between side surfaces of the first wiring layer and the first insulating layer facing the first pillar is greater than a second distance between side surfaces of the second wiring layer and the second insulating layer facing the first pillar and a third distance between the side surfaces of the second insulating layer and the third wiring layer facing the first pillar.

Abstract: A semiconductor device includes a substrate, a first stacked film and a second stacked film each including insulating layers and electrode layers alternately provided on the substrate, and columnar portions provided in the insulating layers and electrode layers of the first stacked film, and including charge storage layers and semiconductor layers. The second stacked film further includes an insulator including first and second lower faces, the first lower face is inclined by a first angle to an upper face of one of the electrode layers in the first stacked film, the second lower face is inclined by a second angle to the upper face of the one of the electrode layers in the first stacked film, and the second angle is less than the first angle. The insulating layers and electrode layers in the second stacked film are provided below the first and second lower faces of the insulator.

Abstract: A memory device includes a stacked structure including a plurality of memory cells, and first and second flights of steps. The first flights of steps are disposed at an end of the stacked structure along the first direction. The second flights of steps are adjacent to the first flights of steps disposed at the end of the stacked structure along the first direction. The first flights of steps and the second flights of steps comprise first portions and second portions alternately disposed along the first direction. The second portions are wider than the first portions along the second direction.

Abstract: Exemplary embodiments for redistribution layers of integrated circuit components are disclosed. The redistribution layers of integrated circuit components of the present disclosure include one or more arrays of conductive contacts that are configured and arranged to allow a bonding wave to displace air between the redistribution layers during bonding. This configuration and arrangement of the one or more arrays minimize discontinuities, such as pockets of air to provide an example, between the redistribution layers during the bonding.

Abstract: A method for manufacturing a semiconductor structure includes: a substrate is provided, the substrate is provided with memory cell array region and peripheral circuit region; a first insulating dielectric layer is formed in memory cell array region and a second insulating dielectric layer is formed in peripheral circuit region, bit line structures are formed in first insulating dielectric layer, conductive structures are formed in second insulating dielectric layer, each bit line structure includes a bit line conductive structure and an isolation structure covering a top and a side wall of bit line conductive structure; isolation structure is etched to form a first gap in memory cell array region and second insulating dielectric layer between conductive structures is etched to form a second gap in peripheral circuit region; and a third insulating dielectric layer is formed on a side wall of first gap and a side wall of second gap.

Abstract: An interconnect structure includes a dielectric layer, a conductive feature, a conductive layer, a capping layer, a support layer and an etch stop layer. The conductive feature is disposed in the dielectric layer. A first portion of the conductive layer is disposed over the first conductive feature, and a second portion of the conductive layer is disposed over the dielectric layer. A first portion of the capping layer is in contact with the first portion of the conductive layer, a second portion of the capping layer is in contact with the second portion of the conductive layer, and a third portion of the capping layer is in contact with the dielectric layer. An air gap is defined by the support layer and the capping layer. The etch stop layer is disposed over the second portion of the conductive layer, the second portion of the capping layer and the support layer.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack, a perforated dielectric moat structure including a dielectric fill material and vertically extending through the alternating stack. The perforated dielectric moat structure includes, at each level of the insulating layers, two rows of lengthwise dielectric pillar portions laterally extending along a first horizontal direction and two columns of widthwise dielectric pillar portions extending along a second horizontal directions that is perpendicular to the first horizontal direction. Each row of lengthwise dielectric pillar portions has a first center-to-center pitch. Each column of widthwise dielectric pillar portions has a second center-to-center pitch. A ratio of the second center-to-center pitch to the first center-to-center pitch is in a range from 1.50 to 2.0.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stack of word line layers and insulating layers that are stacked alternatingly over the substrate, and channel structures formed in a first array region and a second array region of the stack. The first array region and the second array region are positioned at opposing sides of the stack. A first staircase is formed in a connection region of the stack over the substrate, where the connection region is arranged between the first and second array regions. A second staircase is formed in the connection region of the stack over the substrate, and the connection region in the stack includes a separation region between the first and second staircases.

Abstract: A semiconductor device, a layout design method for the semiconductor device, and a method for fabricating the semiconductor device are provided. The semiconductor device includes a standard cell region.