Abstract: Imaging device comprising: a substrate; a pinned photodiode formed on the substrate, wherein the pinned photodiode generates charge that is representative of incident radiation, wherein the imaging device further comprises: circuitry defining a first path for measuring charge and configured to non-destructively produce a signal representative of the charge generated in the pinned photodiode; circuitry defining a subsequent second path for measuring charge and configured to produce a signal representative of the charge generated in the pinned photodiode, and wherein the first and second paths have different conversion gain.

Abstract: Provided is a photoelectric conversion device including: a photoelectric conversion unit including one microlens and a plurality of photoelectric conversion elements, a readout circuit unit configured to read out a first signal based on charges accumulated by a first photoelectric conversion element of the plurality of photoelectric conversion elements and a second signal based on charges accumulated by a second photoelectric conversion element of the plurality of photoelectric conversion elements, and a signal processing unit configured to, according to a determination result based on at least one of the first signal and the second signal, output a third signal obtained by adding the first signal and the second signal or output a fourth signal by replacing the third signal with the fourth signal different from the third signal.

Abstract: An array substrate includes a substrate, the array substrate includes a display region and a detection region. And the detection region includes a thin film transistor located on the substrate and a photodiode located on one side of the thin film transistor away from the substrate, and the array substrate further includes a first inorganic protective layer, an organic protective layer and a second inorganic protective layer located between the thin film transistor and the photodiode. And the first inorganic protective layer, the organic protective layer and the second inorganic protective layer are stacked in sequence in a direction away from the substrate, and an orthographic projection of the photodiode on the substrate is within the range of the orthographic projection of the organic protective layer on the substrate.

Abstract: A light emitting device may include a first electrode disposed on a substrate; a first insulating layer disposed on the substrate and overlapping at least a part of the first electrode; a second electrode disposed on the first insulating layer and spaced apart from the first electrode; and at least one light emitting diode electrically connected between the first electrode and the second electrode. The first electrode and the second electrode may be disposed on different layers on the substrate, the first insulating layer is disposed between the first electrode and the second electrode, and the first electrode and the second electrode are spaced apart from each other so as not to overlap each other in a plan view.

Abstract: Disclosed are a light emitting diode and a method for manufacturing a light emitting diode. The light emitting diode includes a first-type layer, a light emitting layer, a second-type layer and an electrode layer; the first-type layer includes a first-type gallium nitride; the light emitting layer is located on the first-type layer; the light emitting layer includes a quantum point; the second-type layer is located on the light emitting layer; the second-type layer includes a second-type gallium nitride; and the electrode layer is located on the second-type layer.

Abstract: A scan needle includes a substrate, a first color light emitting pixel array comprising a plurality of first color light emitting pixels formed on the substrate, a second color light emitting pixel array comprising a plurality of second color light emitting pixels formed on the substrate, and a third color light emitting pixel array comprising a plurality of third color light emitting pixels formed on the substrate.

Abstract: A semiconductor device may include: a substrate; a protective region provided over the substrate; and a core structure enclosed by the protective region. The core structure may include a core material etchable by a chemical solution. The protective region may include a protective material resistant to etching by the chemical solution. The core structure may have a first side and a second side opposite to the first side, the first side being closer to the substrate than the second side. The core structure may be narrowest at the first side of the core structure.

Abstract: A capacitor includes: a bottom electrode; a top electrode over the bottom electrode; a dielectric film between the bottom electrode and the top electrode; and a doped Al2O3 film between the top electrode and the dielectric film, wherein the doped Al2O3 film includes a first dopant, and an oxide including the same element as the first dopant has a higher dielectric constant than a dielectric constant of Al2O3.

Abstract: Provided are a semiconductor structure and a method for preparing the same. The method for preparing a semiconductor structure includes: a substrate is provided; a stacked structure is formed on the substrate; a first capacitor having a first bottom electrode, a first dielectric layer and a first top electrode is formed in the stacked structure, in which the first bottom electrode is of a columnar structure; and a second capacitor having a second bottom electrode, a second dielectric layer and a second top electrode is formed on the first capacitor, in which the second bottom electrode is of a concave structure. The second dielectric layer is formed between the second bottom electrode and the second top electrode, and the second dielectric layer is further formed between the second bottom electrodes of adjacent second capacitors.

Abstract: An electrode structure includes a pad of conductive material, and a conductive strip having a first end physically and electrically coupled to the pad. The pad includes an annular element internally defining a through opening. The first end of the conductive strip is physically and electrically coupled to the annular element by a transition region so that, when the conductive strip undergoes expansion by the thermal effect, a stress spreads from the conductive strip to the annular element by the transition region.

Abstract: A semiconductor device may include one or more low dielectric constant (low-?) layers on a substrate. The semiconductor device may include a dielectric layer on the one or more low-? layers. The semiconductor device may include a structure through the substrate, the one or more low-? layers, and the dielectric layer. The semiconductor device may include a liner layer between the structure and the substrate, between the structure and the one or more low-? layers, and between the structure and the dielectric layer. The semiconductor device may include a capping layer between the liner layer and the dielectric layer and between the liner layer and the one or more low-? layers.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a MIM dual capacitor structure with an increased capacitance per unit area in a semiconductor structure. Without using additional mask layers, a second parallel plate capacitor can be formed over a first parallel plate capacitor, and both capacitors share a common capacitor plate. The two parallel plate capacitors can be connected in parallel to increase the capacitance per unit area.

Abstract: A semiconductor device includes a substrate; a guard ring disposed on the substrate and adjacent to an edge of the substrate; an integrated circuit structure surrounded by the guard ring and disposed on the substrate; and an insulating material structure disposed on a side surface of the guard ring, and wherein the guard ring includes a plurality of guard active structures on the substrate, a plurality of guard contact structures disposed on each of the plurality of guard active structures, and a guard interconnection structure disposed on a pair of guard contact structures adjacent to each other, among the plurality of guard contact structures, wherein each of the plurality of guard active structures includes a plurality of guard active fins spaced apart from each other.

Abstract: A semiconductor device includes n-type drift layer, n-type current spreading layer having higher impurity concentration than the drift layer, p-type base region provided on top surface, p-type gate-bottom protection region located in the current spreading layer, having first bottom edge portion formed of curved surface, p-type base-bottom embedded region in contact with bottom surface of the base region, having second bottom edge portion formed of curved surface on side surface facing the gate-bottom protection region, being separated from the gate-bottom protection region, and insulated gate electrode structure provided in trench penetrating through the base region to reach the gate-bottom protection region. Bottom surface of the base-bottom embedded region is deeper than bottom surface of the gate-bottom protection region, and minimum value of curvature radius of the first bottom edge portion is larger than minimum value of curvature radius of the second bottom edge portion.

Abstract: A semiconductor device includes a substrate, a gate electrode disposed on an upper surface of the substrate, a source region disposed on a first side of the gate electrode, a drain region disposed on a second side of the gate electrode opposite to the first side of the gate electrode in a horizontal direction, and an insulating structure at least partially buried inside the substrate on the substrate. The insulating structure includes a first portion disposed between the substrate and the gate electrode, and a second portion in contact with the drain region. An uppermost surface of the second portion of the insulating structure is lower than an uppermost surface of the first portion of the insulating structure. At least a part of the gate electrode is disposed on the uppermost surface of the second portion of the insulating structure.

Abstract: A method of forming a semiconductor device includes forming a first semiconductor strip protruding above a first region of a substrate and a second semiconductor strip protruding above a second region of the substrate, forming an isolation region between the first semiconductor strip and the second semiconductor strip, forming a gate stack over and along sidewalls of the first semiconductor strip and the second semiconductor strip, etching a trench extending into the gate stack and isolation regions, the trench exposing the first region of the substrate and the second region of the substrate, forming a dielectric layer on sidewalls and a bottom surface of the trench and filling a conductive material over the dielectric layer and in the trench to form a contact, where the contact extends below a bottommost surface of the isolation region.

Abstract: A semiconductor device includes a device isolation layer on a substrate; pattern groups including fin patterns extending in a first direction; and gate structures extending in a second direction to intersect the fin patterns. A first pattern group, among the pattern groups, may include first fin patterns. At least a portion of the first fin patterns may be arranged with a first pitch in the second direction. The first pattern group may include a first planar portion extending from a first recess portion. A central axis of the first recess portion may be spaced apart from a central axis of one of the first fin patterns by a first distance in the second direction. The first planar portion may have a first width in the second direction and being greater than the first pitch. The first distance may be about 0.8 times to about 1.2 times the first pitch.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes first and second source/drain epitaxial features, a first gate electrode layer disposed between the first and second source/drain epitaxial features, third and fourth source/drain epitaxial features, a second gate electrode layer disposed between the third and fourth source/drain epitaxial features, fifth and sixth source/drain epitaxial features disposed over the first and second source/drain epitaxial features, and a third gate electrode layer disposed between the fifth and sixth source/drain epitaxial features. The third gate electrode layer is electrically connected to the second source/drain epitaxial feature. The structure further includes a seventh source/drain epitaxial feature disposed over the third source/drain epitaxial feature and an eighth source/drain epitaxial feature disposed over the fourth source/drain epitaxial feature.

Abstract: A semiconductor device includes a substrate; an isolation structure over the substrate; a fin over the substrate and the isolation structure; a gate structure engaging a first portion of the fin; first sidewall spacers over sidewalls of the gate structure and over a second portion of the fin; source/drain (S/D) features adjacent to the first sidewall spacers; and second sidewall spacers over the isolation structure and over sidewalls of a portion of the S/D features. The second sidewall spacers include silicon oxide, silicon nitride, or silicon oxynitride. The second sidewall spacers and the second portion of the fin include a same dopant, wherein the dopant includes phosphorus.

Abstract: A semiconductor device structure, along with methods of forming such, are described. In one embodiment, a semiconductor device structure is provided. The semiconductor device structure includes a substrate having a front side and a back side opposing the front side, a gate stack disposed on the front side of the substrate, and a first source/drain feature and a second source/drain feature disposed in opposing sides of the gate stack. Each first source/drain feature and second source/drain feature comprises a first side and a second side, and a portion of the back side of the substrate is exposed to an air gap.

Abstract: The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer on the substrate and a second nitride semiconductor layer on the first nitride semiconductor layer. The second nitride semiconductor layer has a first area and a second area, and the second nitride semiconductor layer has single crystals. The semiconductor device includes an electrode in contact with the first area. A first concentration of Aluminum (Al) of the first area is less than a second concentration of Al of the second area, and the single crystals in the first area take over a crystal structure of the first nitride semiconductor layer.

Abstract: A method of fabricating a device on a substrate includes doping a channel region of the device with dopants. The method further includes growing an undoped epitaxial layer over the channel region, wherein growing the undoped epitaxial layer comprises deactivating dopants in the channel region to form a deactivated region. The method further includes forming a gate structure over the deactivated region.

Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer; a first opening penetrating through the second nitride semiconductor layer to the first nitride semiconductor layer; a second opening penetrating through the second nitride semiconductor layer to the first nitride semiconductor layer; an electron transport layer and an electron supply layer provided along an inner face of each of the first opening and the second opening and above the second nitride semiconductor layer; a gate electrode; an anode electrode; a third opening penetrating through the electron supply layer and the electron transport layer to the second nitride semiconductor layer; a source electrode in the third opening; a drain electrode; and a cathode electrode. The anode electrode and the source electrode are electrically connected, and the cathode electrode and the drain electrode are electrically connected.

Abstract: Integrated semiconductor devices and method of making the integrated semiconductor are disclosed. The integrated semiconductor device may include a first transistor comprising a first gate and at least one first active region, a second transistor comprising a second gate and at least one second active region, wherein the second transistor is spaced a first distance from the first transistor, a dielectric sidewall spacer formed on a gate sidewall of the first transistor and a gate sidewall of the second transistor, a first dielectric layer formed over the first transistor and the second transistor, wherein a thickness of the first dielectric layer is greater than half the first distance, and a patterned metal layer formed on the first dielectric layer and partially covering the second gate.

Abstract: a transistor and an interconnect structure disposed over the transistor. The interconnect structure includes a first dielectric layer, a first conductive feature in the first dielectric layer, a first etch stop layer (ESL) disposed over the first dielectric layer and the first conductive feature, a dielectric feature disposed in the first ESL, an electrode disposed over the dielectric feature, and a second ESL disposed on the first ESL and the electrode.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure disposed over a channel region of an active region, a drain feature disposed over a drain region of the active region; a source feature disposed over a source region of the active region, a backside source contact disposed under the source feature, an isolation feature disposed on and in contact with the source feature, a drain contact disposed over and electrically coupled to the drain feature, and a gate contact via disposed over and electrically coupled to the gate structure. A distance between the gate contact via and the drain contact is greater than a distance between the gate contact via and the isolation feature. The exemplary semiconductor structure would have a reduced parasitic capacitance and an enlarged leakage window.

Abstract: In an embodiment, a semiconductor device is provided that includes a lateral transistor device having a source, a drain and a gate, and a monolithically integrated capacitor coupled between the gate and the drain.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure includes gate electrodes and first insulation patterns laterally disposed and alternately arranged on a substrate, a gate dielectric layer disposed on the gate electrodes and the first insulation patterns, at least one channel pattern disposed on the gate dielectric layer, source electrodes and drain electrodes laterally disposed and alternately arranged on the channel pattern, and second insulation patterns disposed on the channel pattern between the source and drain electrodes. Besides, from a top view, each of the drain electrodes is overlapped with one of the first insulation patterns.

Abstract: A transistor includes a substrate; a pair of constant current forming regions provided in the substrate; a pair of source/drain regions respectively provided on the pair of constant current forming regions in the substrate; and a gate structure provided between the pair of source/drain regions, wherein any one of the constant current forming regions immediately adjacent to any one of the pair of source/drain regions serving as a drain forms a constant current between the any one of the pair of source/drain region serving as the drain and the any one of the constant current forming regions.

Abstract: A semiconductor structure includes a substrate; a first structure over the substrate and having a first gate stack and two first gate spacers on two opposing sidewalls of the first gate stack; a second structure over the substrate and having a second gate stack and two second gate spacers on two opposing sidewalls of the second gate stack; a source/drain (S/D) feature over the substrate and adjacent to the first and the second gate stacks; an S/D contact over the S/D feature and between one of the first gate spacers and one of the second gate spacers; a conductive via disposed over and electrically connected to the S/D contact; and a dielectric liner layer. A first portion of the dielectric liner layer is disposed on a sidewall of the one of the first gate spacers and is directly above the S/D contact and spaced from the S/D contact.

Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.

Abstract: Gate fingers extending symmetrically from both sides of gate connecting portions, drain electrodes adjacent to both the gate fingers extending from both the sides of the gate connecting portions, and source electrodes respectively adjacent to the gate fingers extending from both the sides of the gate connecting portions are included. Gate air bridges connect the gate connecting portions and a gate routing line while straddling the source electrodes.

Abstract: In some implementations, fluorine is oxidized after dry etching an oxide layer above a source/drain contact and before cleaning. Accordingly, less hydrofluoric acid is formed during cleaning, which reduces unexpected wet etching of the source/drain contact. This allows for forming a recess in the source/drain contact with a depth to width ratio in a range from approximately 1.0 to approximately 1.4 and prevents damage to a layer of silicide below the source/drain that can be caused by excessive hydrofluoric acid. Additionally, or alternatively, the recess is formed using multiple wet etch processes, and any residual fluorine is oxidized between the wet etch processes. Accordingly, each wet etching process may be shorter and less corrosive, which allows for greater control over dimensions of the recess. Additionally, less hydrofluoric acid may be formed during cleaning processes between the wet etch processes, which reduces the etching of the source/drain contact between processes.

Abstract: In an embodiment, a device includes: a first channel region; a second channel region; and a gate structure around the first channel region and the second channel region, the gate structure including: a gate dielectric layer; a first p-type work function metal on the gate dielectric layer, the first p-type work function metal including fluorine and aluminum; a second p-type work function metal on the first p-type work function metal, the second p-type work function metal having a lower concentration of fluorine and a lower concentration of aluminum than the first p-type work function metal; and a fill layer on the second p-type work function metal.

Abstract: A semiconductor structure includes a common semiconductor substrate; a first field effect transistor (FET) gate formed on the substrate, which has a first threshold voltage and comprises a first work function metal and a first barrier layer, and a second FET gate formed on the substrate, which has a second threshold voltage and comprises the first work function metal, the first barrier layer, and a second work function metal.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are provided. In embodiments a passivation process is utilized in order to reduce dangling bonds and defects within work function layers within a gate stack. The passivation process introduces a passivating element which will react with the dangling bonds to passivate the dangling bonds. Additionally, in some embodiments the passivating elements will trap other elements and reduce or prevent them from diffusing into other portions of the structure.

Abstract: A semiconductor device including a gaseous spacer and a method for forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer over the first gate spacer; removing a portion of the second gate spacer, at least a portion of the second gate spacer remaining; removing the first gate spacer to form a first opening; and after removing the first gate spacer, removing the remaining portion of the second gate spacer through the first opening.

Abstract: A power semiconductor device includes a semiconductor substrate and a plurality of transistor cells formed in the semiconductor substrate and electrically connected in parallel to form a power transistor. Each transistor cell includes a gate structure including a gate electrode and a gate dielectric stack separating the gate electrode from the semiconductor substrate. The gate dielectric stack includes a ferroelectric insulator and a first dielectric insulator. The first dielectric insulator has a relative permittivity greater than that of silicon dioxide. A driver device for switching the power transistor and a corresponding method of operating the power transistor are also described.

Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a gate structure, a first spacer, a second spacer and a drain electrode. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The gate structure is disposed on the second nitride semiconductor layer. The first spacer is disposed adjacent to a first surface of the gate structure. The second spacer is disposed adjacent to a second surface of the gate structure. The drain electrode is disposed relatively adjacent to the second spacer than the first space. The first spacer has a first length, and the second spacer has a second length greater than the first length along the first direction.

Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.

Abstract: A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.

Abstract: A semiconductor device includes a substrate, a fin structure protruding from the substrate, a gate insulating layer covering a channel region formed of the fin structure, a gate electrode layer covering the gate insulating layer, and isolation layers disposed on opposite sides of the fin structure. The fin structure includes a bottom portion, a neck portion, and a top portion sequentially disposed on the substrate. A width of the neck portion is less than a width of the bottom portion and a width of a portion of the top portion.

Abstract: A method includes forming a semiconductor fin protruding higher than a top surface of an isolation region. The semiconductor fin overlaps a semiconductor strip, and the semiconductor strip contacts the isolation region. The method further includes forming a gate stack on a sidewall and a top surface of a first portion of the semiconductor fin, and etching the semiconductor fin and the semiconductor strip to form a trench. The trench has an upper portion in the semiconductor fin and a lower portion in the semiconductor strip. A semiconductor region is grown in the lower portion of the trench. Process gases used for growing the semiconductor region are free from both of n-type dopant-containing gases and p-type dopant-containing gases. A source/drain region is grown in the upper portion of the trench, wherein the source/drain region includes a p-type or an n-type dopant.

Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottom surface of the gate structure is closer to the substrate than a bottom surface of the source/drain contact.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate including a first region and a second region, a first gate structure over the first region, and first source-drain doped layers in the first region of the substrate on both sides of the first gate structure. The semiconductor structure also includes a second gate structure over the second region, and second source-drain doped layers in the second region of the substrate on both sides of the second gate structure. Further, the semiconductor structure includes a first protection layer over the second gate structure, a first conductive structure over a first source-drain doped layer, and an isolation layer over the first conductive structure. The first conductive structure is also formed on the first gate structure, and the first conductive structure has a top surface lower than the first protection layer.

Abstract: A method, for making a semiconductor device, includes forming a first fin over a substrate. The method includes forming a dummy gate stack on the first fin. The method includes forming a first gate spacer along a side of the dummy gate stack. The first gate spacer includes a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming a source/drain region in the first fin adjacent the second gate spacer. The method includes removing at least a portion of the second gate spacer to form a void extending between the first gate spacer and the source/drain region.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device, includes forming a first insulating film which covers a gate electrode, forming an island-shaped oxide semiconductor in contact with the first insulating film, forming a second insulating film which covers the oxide semiconductor, forming a source electrode in contact with the oxide semiconductor, forming a drain electrode in contact with the oxide semiconductor, forming a third insulating film which covers the source electrode and the drain electrode and forming a channel region between the source electrode and the drain electrode by supplying oxygen from the third insulating film to the oxide semiconductor via the second insulating film.

Abstract: A BJT and methods of forming the same are described. The BJT includes a collector region disposed in a substrate, a lower base structure disposed on the collector region, a first dielectric layer surrounding a bottom portion of the lower base structure, and a second dielectric layer surrounding a top portion of the lower base structure. The first dielectric layer includes a first oxide, the second dielectric layer includes a second oxide, and the first and second oxides have different densities. The BJT further includes an upper base structure disposed on the second dielectric layer and the lower base structure, an emitter region disposed on the lower base structure, a sidewall spacer structure disposed between the emitter region and the upper base structure, and the sidewall spacer structure includes a material different from materials of the first and second dielectric layers.

Abstract: Disclosed semiconductor structure embodiments include a bipolar junction device configured to have a high holding voltage. The device includes base, collector and emitter terminals. The high holding voltage is achieved because of a uniquely configured emitter terminal. Specifically, the device includes a base well region, which has a first-type conductivity. The emitter terminal includes, adjacent to the base well region (e.g., within and/or on the base well region), an emitter contact region, which has a second-type conductivity, and an ancillary emitter region, which abuts the emitter contact region and which has the first-type conductivity at a higher conductivity level than the base well region. Embodiments vary with regard to the shapes of the emitter contact region and ancillary emitter region. Embodiments also vary with regard to the structures used to isolate the collector terminal from the emitter terminal and with regard to the areas covered by silicide layers.

Abstract: The present disclosure generally relates to dopant profile control in a heterojunction bipolar transistor (HBT). In an example, a semiconductor device structure includes a semiconductor substrate and an HBT. The HBT includes a collector region, a base region, and an emitter region. The base region is disposed on or over the collector region. The emitter region is disposed on or over the base region. The base region is disposed on or over the semiconductor substrate and includes a heteroepitaxial sub-layer. The heteroepitaxial sub-layer is doped with a dopant. A concentration gradient of the dopant increases from a region in a layer adjoining and overlying the heteroepitaxial sub-layer to a peak concentration in the heteroepitaxial sub-layer without decreasing between the region and the peak concentration.