Abstract: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.

Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure comprises at least one two-dimensional (2D) conductive structure; a dielectric layer disposed on the 2D conductive structure; and at least one interconnect structure disposed in the dielectric layer and extending into the 2D conductive structure, wherein the interconnect structure laterally connects to at least one edge of the 2D conductive structure.

Abstract: An interconnection structure, along with methods of forming such, are described. The interconnection structure includes a first portion of a conductive layer, and the conductive layer includes one or more graphene layers. The first portion of the conductive layer includes a first interface portion and a second interface portion opposite the first interface portion, and each of the first and second interface portion includes a metal disposed between adjacent graphene layers. The structure further includes a second portion of the conductive layer disposed adjacent the first portion of the conductive layer, and the second portion of the conductive layer includes a third interface portion and a fourth interface portion opposite the third interface portion. Each of the third and fourth interface portion includes the metal disposed between adjacent graphene layers. The structure further includes a dielectric material disposed between the first and second portions of the conductive layer.

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conducting material that is in a lowest of the conductive tiers and that is directly against multiple of the channel-material strings. The channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. A wall in the lowest conductive tier is aside the conducting material. The wall is in a region that is edge-of-plane relative to the memory plane. The edge-of-plane region comprises a TAV region. The wall is horizontally-elongated relative to an edge of the TAV region that is in the edge-of-plane region.

Abstract: Provided is a semiconductor architecture including a carrier substrate, alignment marks provided in the carrier substrate, the alignment marks being provided from a first surface of the carrier substrate to a second surface of the carrier substrate, a first semiconductor device provided on the first surface of the carrier substrate based on the alignment marks, a second semiconductor device provided on the second surface of the carrier substrate based on the alignment marks and aligned with the first semiconductor device.

Abstract: Some examples described herein relate to protecting an integrated circuit (IC) structure from imaging or access. In an example, an IC structure includes a semiconductor substrate, an electromagnetic radiation blocking layer, and a support substrate. The semiconductor substrate has a circuit disposed on a front side of the semiconductor substrate. The electromagnetic radiation blocking layer is disposed on a backside of the semiconductor substrate opposite from the front side of the semiconductor substrate. The support substrate is bonded to the semiconductor substrate. The electromagnetic radiation blocking layer is disposed between the semiconductor substrate and the support substrate.

Abstract: An electronic assembly according to an embodiment includes: a circuit board including a first edge surface and a trace having an electrical conductivity; an electronic element including a lateral edge spatially spaced apart from the first edge surface, and mounted on the circuit board and electrically connected to the trace; a protection layer including a second edge surface and disposed on the electronic element to substantially cover the electronic element; a magnetic field shielding film including a third edge surface and disposed on the protection layer; and a first metal layer.

Abstract: A semiconductor device package includes a substrate having a surface, a conductive element disposed on the surface of the substrate, and an encapsulant disposed on the surface of the substrate and covering the conductive element. The conductive element has an upper surface facing away from the substrate and exposed from the encapsulant. Further, a roughness of the upper surface of the conductive element is greater than a roughness of a side surface of the conductive element.

Abstract: A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate and a semiconductor device disposed over the package substrate. A ring structure is disposed over the package substrate and laterally surrounds the semiconductor device. The ring structure includes a lower ring portion arranged around the periphery of the package substrate. Multiple notches are formed along the outer periphery of the lower ring portion. The ring structure also includes an upper ring portion integrally formed on the lower ring portion. The upper ring portion laterally extends toward the semiconductor device, so that the inner periphery of the upper ring portion is closer to the semiconductor device than the inner periphery of the lower ring portion. An adhesive layer is interposed between the lower ring portion and the package substrate.

Abstract: A semiconductor package includes a semiconductor die including a semiconductor substrate, a strain-sensitive component located within or over a metallization layer of the semiconductor die, wherein a parameter of the strain-sensitive component exhibits a longitudinal shift due to a longitudinal strain and a transverse shift due to a transverse strain, and a mold compound covering the semiconductor die and the strain-sensitive component. The semiconductor package, including the semiconductor die and the mold compound, defines an orthogonal package-induced strain ratio on the strain-sensitive component on the semiconductor die surface. The strain-sensitive component is located such that the longitudinal shift due to package-induced strains offsets the transverse shift due to the package-induced strains.

Abstract: A semiconductor package includes: a first die; a second die stacked on an upper surface of the first die, the second die including a second semiconductor substrate and a second seal ring structure that extends along a perimeter of the second semiconductor substrate; a third die stacked on the upper surface of the first die, the third die including a third semiconductor substrate and a third seal ring structure that extends along a perimeter of the third semiconductor substrate; and a connection circuit that extends through the second seal ring structure and the third seal ring structure, in a lateral direction perpendicular to the stacking direction of the first die and the second die, to electrically connect the second semiconductor substrate and the third semiconductor substrate.

Abstract: A method for fabricating memory devices includes forming a first portion of a memory device that includes a first device portion and one or more first interface portions. The first device portion includes a plurality of first memory strings, each of which includes a plurality of first memory cells vertically separated from one another. Each of the one or more first interface portions, laterally abutted to one side of the first device portion, includes a plurality of first word lines (WLs). The method further includes forming a plurality of first source lines (SLs) and a plurality of first bit lines (BLs) in the first device portion. The method further includes forming a first seal ring structure that laterally encloses both the first device portion and the first interface portion concurrently with forming the pluralities of SLs and BLs.

Abstract: A display panel includes a first substrate, a second substrate, a light emitting element, and a first conductor. The second substrate is arranged opposite to the first substrate. The light emitting element is located on a side of the first substrate facing towards the second substrate. The first conductor is located on a side of the first substrate facing towards the second substrate.

Abstract: A device that includes a metal submount; a first transistor die arranged on said metal submount; a second transistor die arranged on said metal submount; a set of primary interconnects; and a set of secondary interconnects. Additionally, the set of primary interconnects and the set of secondary interconnects are configured to provide RF signal coupling between the first transistor die and the second transistor die by electromagnetic coupling.

Abstract: An interconnect layer for an integrated circuit device includes a low radio frequency (RF) loss primary coating that forms a main portion of the interconnect layer, an opening formed in the primary coating, a high aspect ratio patternable secondary coating within the opening, and a via formed in the secondary coating. An aspect ratio of the via is greater than an aspect ratio of the opening.

Abstract: A method for manufacturing a semiconductor device is provided, including: preparing a first chip forming portion having a first semiconductor substrate, first metal pads provided at the substrate and a first circuit electrically connected to at least a part of the pads, and a second chip forming portion having a second semiconductor substrate, second metal pads provided at substrate and a second circuit electrically connected to at least a part of the pads; bonding the first and the second chip forming portions while joining the first and the second pads to form a bonding substrate having a non-bonded region between the first and the second chip forming portions at an outer peripheral portion thereof; and filling an insulating film into the non-bonded region, at least a part of the insulating film containing at least one selected from the group consisting of silicon nitride and nitrogen-containing silicon carbide.

Abstract: A semiconductor device includes first conductive films that are provided, above a semiconductor substrate, at least on both sides of a non-formation region in which the first conductive films are not provided; an interlayer dielectric film including a first portion that is provided on the non-formation region, second portions provided above the first conductive film on both sides of the non-formation region, and a step portion that connects the first portion and the second portions; a second conductive film provided above the interlayer dielectric film; through terminal portions that penetrate the second portions of the interlayer dielectric film; and a wire bonded with the second conductive film above the first portion, where the through terminal portions include one or more first through terminal portions and one or more second through terminal portions being provided at positions opposite to each other with a bonded portion of the wire being interposed therebetween.

Abstract: A method and a system for verifying an integrated circuit stack having a silicon photonic (SIPH) device is introduced. A single first dummy layer is added to at least one terminal of the SIPH device in a first layout of the first integrated circuit, wherein a shape of the single first dummy layer added to the at least one terminal of the SIPH device maps a shape of the at least one terminal of the SIPH device. A first layout versus schematic (LVS) check is performed on the first integrated circuit based on the single first dummy layer added to the at least one terminal of the SIPH device to verify a connection of the SIPH device in the first integrated circuit.

Abstract: A semiconductor package includes a redistribution substrate, and a semiconductor chip disposed on a top surface of the redistribution substrate. The redistribution substrate includes under bump patterns laterally spaced apart from each other, a dummy pattern disposed between the under bump patterns, a passivation pattern disposed on a bottom surface of the dummy pattern, an insulating layer covering top surfaces and sidewalls of the under bump patterns and a sidewall and a top surface of the dummy pattern, and a redistribution pattern disposed on one of the under bump patterns and electrically connected to the one under bump pattern. The passivation pattern includes a different material from that of the insulating layer.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.

Abstract: A microelectronic device comprises a first die and a second die attached to the first die. The first die comprises a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, vertically extending strings of memory cells within the stack structure, and first bond pad structures vertically neighboring the vertically extending strings of memory cells. The second die comprises a control logic region comprising control logic devices configured to effectuate at least a portion of control operations for the vertically extending string of memory cells, second bond pad structures in electrical communication with the first bond pad structures, and signal routing structures located at an interface between the first die and the second die. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: A package includes a die and a redistribution layer. A top surface of the die has a first area and a second area connected with the first area. The redistribution layer structure includes a first insulation layer, a redistribution layer, and a second insulation layer. The first insulation layer is overlapping with the second area. The redistribution layer is disposed above the die. The second insulation layer is disposed above the redistribution layer and overlapping with the second area and the first area. The second insulation layer covers a top surface of the first insulation layer and is in contact with a side surface of the first insulation layer and the top surface of the die.

Abstract: A semiconductor device includes a first carrier, a first external contact, a second external contact, and a first semiconductor die. The first semiconductor die has a first main face, a second main face opposite to the first main face, a first contact pad disposed on the first main face, a second contact pad disposed on the second main face, a third contact pad disposed on the second main face, and a vertical transistor. The first semiconductor die is disposed with the first main face on the first carrier. A clip connects the second contact pad and the second external contact. A first wire is connected with the first external contact. The first wire is disposed at least partially under the clip.

Abstract: A die bonding apparatus includes: a driven body; and a table for driving the driven body. The table includes: a base; a linear motor having a first mover that moves the driven body, and a stator; a first linear motion guide that is provided between the base and the stator and capable of freely moving the stator; a second linear motion guide that is provided between the base and the first mover and capable of freely moving the first mover; a second mover provided in the form of being fixed to the base; and a control device for controlling the first mover and the second mover. The control device is configured to move the stator along the first linear motion guide using the second mover.

Abstract: Disclosed herein is a method, including attaching a semiconductor chip to a chip mounting portion on at least one leadframe portion, and attaching a passive component on a passive component mounting portion of the at least one leadframe portion. The method further includes forming a laser direct structuring (LDS) activatable molding material over the semiconductor chip, passive component, and the at least one leadframe portion. Desired patterns of structured areas are formed within the LDS activatable molding material by activating the LDS activatable molding material. The desired patterns of structured areas are metallized to form conductive areas within the LDS activatable molding material to thereby form electrical connection between the semiconductor chip and the passive component. A passivation layer is formed on the LDS activatable molding material.

Abstract: A first semiconductor device and a second semiconductor device may be directly bonded using heterogeneous bonding layers. A first bonding layer may be formed on the first semiconductor device and the second bonding layer may be formed on the second semiconductor device. The first bonding layer may include a higher concentration of hydroxy-containing silicon relative to the second bonding layer. The second bonding layer may include silicon with a higher concentration of nitrogen relative to the first bonding layer. An anneal may be performed to cause a dehydration reaction that results in decomposition of the hydroxy components of the first bonding layer, which forms silicon oxide bonds between the first bonding layer and the second bonding layer. The nitrogen in the second bonding layer increases the effectiveness of the dehydration reaction and the effectiveness and strength of the bond between the first bonding layer and the second bonding layer.

Abstract: Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface.

Abstract: A dipole alignment device includes an electric field forming part including a stage, and a probe part which form an electric field on the stage; an inkjet printing apparatus including at least one inkjet head which sprays ink including dipoles and a solvent with the dipoles dispersed therein onto the stage; a transportation part comprising a first moving part which moves the electric field forming part in at least one direction; and a light irradiation apparatus including a light irradiation part which applies light to the ink sprayed onto the stage.

Abstract: There is provided a semiconductor device including a first electrode including a first plate portion, the first plate portion including a first surface and a second surface facing the first surface, a plurality of semiconductor chips provided above the second surface, and a second electrode including a second plate portion provided above the semiconductor chips, the second plate portion including a third surface facing the second surface and a fourth surface facing the third surface, the second plate portion including a plurality of protrusion portions provided between the semiconductor chips and the third surface, the protrusion portions being connected to the third surface, each of the protrusion portions including a top surface including the same shape as a shape of each of the semiconductor chips in a plane parallel to the second surface, the second plate portion including a second outer diameter larger than a first diameter of a smallest circle circumscribing the protrusion portions provided on an outerm

Abstract: In an embodiment, the semiconductor device is surface mountable and comprises a light emitting semiconductor chip which comprises electrical contact pads. An opaque base body laterally surrounds the semiconductor chip. An electrical fanning layer contains electrical conductor tracks. Electrical connection pads are used for external electrical contacting of the semiconductor device. The contact pads and the connection pads are located on different sides of the fanning layer. The contact pads are electrically connected to the associated connection pads by means of the fanning layer. The connection pads are expanded relative to the contact pads.

Abstract: A stacked semiconductor device having hybrid metallic structures and associated systems and methods are disclosed herein. The stacked semiconductor device can include a first semiconductor die and a second semiconductor die. The first semiconductor die can include a top surface, a first bond site at the top surface and a second bond site at the first surface spaced apart from the first bond site. The second semiconductor die can include a lower surface facing the top surface of the first semiconductor die, a third bond site at the lower surface, and a fourth bond site at the lower surface. The third bond site includes a conductive structure bonded to the first bond site by a metal-metal bond. The fourth bond site at the lower surface includes a solder ball bonded to the second bond site.

Abstract: An electronic assembly includes a plurality of electronic die arranged into shingles, each shingle having a multiple offset stacked die coupled by cascading connections. Each shingle is arranged in a stack of shingles with alternate shingles having die stacked in opposite directions and offset in a zigzag manner to facilitate vertical electrical connections from a top of the electronic assembly to a bottom die of each shingle.

Abstract: A 3D IC structure includes multiple dies, such as a top die and a bottom die. The top die and/or the bottom die can each include devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. One or more vertical interconnect structure (VIS) cells are formed adjacent one or more sides of the device. A VIS is formed in some or all of the VIS cells. One or more non-sensitive circuits, such as repeaters, diodes, and/or passive circuits (e.g., resistors, inductors, capacitors, transformers), are disposed in at least one VIS cell.

Abstract: A stacked die structure includes a base die, a top die and conductive terminals electrically connected to the top die. The base die includes a base semiconductor substrate, a base interconnection layer disposed on the base semiconductor substrate, and a base bonding layer disposed on the base interconnection layer. The top die is stacked on the base die and electrically connected to the base die, wherein the top die includes a top bonding layer, a top semiconductor substrate, a top interconnection layer, top conductive pads and top grounding vias. The top bonding layer is hybrid bonded to the base bonding layer. The top interconnection layer is disposed on the top semiconductor substrate and includes a dielectric layer, conductive layers embedded in the dielectric layer, and conductive vias joining the conductive layers. The conductive pads and top grounding vias are embedded in the dielectric layer and disposed on the conductive layers.

Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.

Abstract: A device comprises a first chip comprising a first connection pad embedded in a first dielectric layer and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad and a second chip comprising a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad.

Abstract: A semiconductor integrated circuit device includes first and second semiconductor chips stacked one on top of the other. First power supply lines in the first semiconductor chip are connected with second power supply lines in the second semiconductor chip through a plurality of first vias. The directions in which the first power supply lines and the second power supply lines extend are orthogonal to each other.

Abstract: A power module includes a mount layer, a control layer, and a drive layer that are formed on an electrically insulative substrate and multiple power semiconductor elements mounted on the mount layer in one direction and each including a first drive electrode connected to the mount layer, a second drive electrode connected to the drive layer, and a control electrode connected to the control layer. A control terminal is connected to the control layer and a detection terminal is connected to the drive layer. At least one of the control layer and the drive layer includes a detour portion that detours to reduce a difference between the power semiconductor elements in a sum of a length of a first conductive path between the control electrode and the control terminal and a length of a second conductive path between the second drive electrode and the detection terminal.

Abstract: A power semiconductor module includes a main substrate and power semiconductor chips. Each power semiconductor chip is bonded to the main conductive layer with the first power electrode. A first group of the power semiconductor chips is connected in parallel via the second power electrodes and a second group of the power semiconductor chips is connected in parallel via the second power electrodes. The module also includes a first insulation layer and a first conductive layer overlying the first insulation layer as well as a second insulation layer and a second conductive layer overlying the second insulation layer. The first conductive layer provides a first gate conductor area and a first auxiliary emitter conductor area for the first group. The second conductive layer provides a second gate conductor area and a second auxiliary emitter conductor area for the second group.

Abstract: The display panel includes a base substrate; and display areas arranged on the base substrate; each of the display areas includes pixel units; each of the pixel units includes sub-pixels; each of the sub-pixels includes a light-emitting chip; in any one of the display areas, a space between two adjacent columns of pixel units in a row direction has a first space size; and a space between two adjacent rows of pixel units in a column direction has a second space size; a space between two nearest display areas in the row direction has a third space size, and the third space size is approximately same as the first space size; and/or a space between two nearest display areas in the column direction has a fourth space size, and the fourth space size is approximately same as the second space size.

Abstract: An LED micro display device includes a circuit substrate, micro light-emitting elements, an insulating layer, and a common electrode layer. The circuit substrate has conductive patterns. The micro light-emitting elements are bonded to the circuit substrate and disposed corresponding to the conductive patterns. Each micro light-emitting element has a bottom surface, a top surface and a side wall. The bottom surface connects to the corresponding conductive pattern. The side wall has a first sidewall portion adjacent to the circuit substrate and a second sidewall portion connected to the first sidewall portion. The insulating layer is disposed on the circuit substrate, covers first sidewall portions, and exposes second sidewall portions. The common electrode layer covers the insulating layer and second sidewall portions. The common electrode layer is electrically connected to the micro light-emitting elements, contacts the second sidewall portions, and exposes the top surfaces.

Abstract: A display includes a plurality of blue, green and red light emitting micro-LEDs having respective blue, green and red emission spectra having respective emission peaks at respective wavelengths with respective full width at half maxima (FWHMs). A partial light transmitting layer is disposed on the plurality of blue, green and red light emitting micro-LEDs and includes substantially distinct blue, green and red transmission bands with respective blue, green and red FWHMs. For substantially normally incident light, the partial light transmitting layer has an optical transmittance of greater than about 50% at each of the blue, green and red peak wavelengths. The blue, green and red FWHMs of the partial light transmitting layer are less than the respective blue, green and red FWHMs of the blue, green and red light emitting micro-LEDs by at least 10%.

Abstract: A manufacturing method of a micro light emitting diode structure includes: providing a first transfer stamp carrying a plurality of micro light emitting elements; providing a second transfer stamp carrying a plurality of light blocking structures, wherein each of the light blocking structures includes a light blocking layer and a light shielding layer disposed on the light blocking layer; providing a temporary substrate; transferring the micro light emitting elements onto the temporary substrate by the first transfer stamp; and transferring the light blocking structures onto the temporary substrate by the second transfer stamp. The micro light emitting elements and the light blocking structures are arranged alternately and fixed to the temporary substrate by connection layer. A reflectivity of the light blocking layer is greater than a reflectivity of the connection layer, and a Young's modulus of the light blocking layer is greater than a Young's modulus of the connection layer.

Abstract: A method includes bonding a capacitor die to a device die. The device die includes a first semiconductor substrate, active devices at a surface of the first semiconductor substrate, a plurality of low-k dielectric layers, a first dielectric layer over and contacting a top low-k dielectric layer in the plurality of low-k dielectric layers, and a first plurality of bond pads in the first dielectric layer. The capacitor die includes a second dielectric layer bonding to the first dielectric layer, a second plurality of bond pads in the second dielectric layer and bonding to the first plurality of bond pads, and a capacitor electrically coupled to the second plurality of bond pads. After the capacitor die is bonded to the device die, an aluminum-containing pad is formed over the capacitor die and electrically coupled to the device die. A polymer layer is formed over the aluminum-containing pad.

Abstract: A method for wafer bonding includes: providing a semiconductor wafer having a first main face; fabricating at least one semiconductor device in the semiconductor wafer, wherein the semiconductor device is arranged at the first main face; generating trenches and a cavity in the semiconductor wafer such that the at least one semiconductor device is connected to the rest of the semiconductor wafer by no more than at least one connecting pillar; arranging the semiconductor wafer on a carrier wafer such that the first main face faces the carrier wafer; attaching the at least one semiconductor device to the carrier wafer; and removing the at least one semiconductor device from the semiconductor wafer by breaking the at least one connecting pillar.

Abstract: An embodiment device includes: a first dielectric layer; a first photonic die and a second photonic die disposed adjacent a first side of the first dielectric layer; a waveguide optically coupling the first photonic die to the second photonic die, the waveguide being disposed between the first dielectric layer and the first photonic die, and between the first dielectric layer and the second photonic die; a first integrated circuit die and a second integrated circuit die disposed adjacent the first side of the first dielectric layer; conductive features extending through the first dielectric layer and along a second side of the first dielectric layer, the conductive features electrically coupling the first photonic die to the first integrated circuit die, the conductive features electrically coupling the second photonic die to the second integrated circuit die; and a second dielectric layer disposed adjacent the second side of the first dielectric layer.

Abstract: We herein describe a semiconductor device sub-assembly comprising at least two power semiconductor devices and a contact of a first type. A first power semiconductor device is located on a first side of the contact of a first type, and a second power semiconductor device is located on a second side of the contact of a first type, where the second side is opposite to the first side.

Abstract: According to one embodiment, a semiconductor device includes a first substrate and a logic circuit provided on the first substrate. The device further includes a memory cell provided above the logic circuit and a second substrate provided above the memory cell. The device further includes a bonding pad provided above the second substrate and electrically connected to the logic circuit. The device further includes a wiring that is provided above the second substrate, is electrically connected to the memory cell, and includes at least one of a data signal line, a control voltage line, and a power supply line.

Abstract: A chip-on-wafer-on-substrate (CoWoS) semiconductor assembly is formed which includes a chip-on-wafer (CoW) sub-assembly of integrated circuit (IC) dies mounted on an interposer, which is in turn mounted on a package substrate with a top metallization stack and a bottom metallization stack using bonding bumps connecting the backside of the interposer and the front side of the package substrate. The bonding bumps provide electrical connections between the ends of through-vias exposed at the backside of the interposer and the top metallization stack of the package substrate. The likelihood of certain failure mechanisms that can adversely affect CoWoS yield are reduced or eliminated by ensuring a total metal thickness of the top metallization stack is greater than a total metal thickness of the bottom metallization stack, but not so much greater as to induce cracking of the underfill material during curing thereof.

Abstract: In one embodiment, a semiconductor device includes a first interconnection including a first extending portion extending in a first direction, and a first curved portion curved with respect to the first extending portion. The device further includes a second interconnection including a second extending portion extending in the first direction and adjacent to the first extending portion in a second direction, and a second curved portion curved with respect to the second extending portion. The device further includes a first plug provided on the first curved portion, or on a first non-opposite portion included in the first extending portion and not opposite to the second extending portion in the second direction. The device further includes a second plug provided on the second curved portion, or on a second non-opposite portion included in the second extending portion and not opposite to the first extending portion in the second direction.