Abstract: A control device is provided which controls an electric drive system, which has a motor that rotates a rotor blade and an inverter circuit that has a switching element and controls the motor and which is installed in a flying body. The control device includes an abnormality occurrence detection unit that detects occurrence of a predetermined abnormality accompanied with an abnormality of temperature of the switching element, and a switching element control unit that controls, when the occurrence of the predetermined abnormality is detected, the switching element so as to reduce loss in the switching element.

Abstract: An electrical propulsion system includes an electrical motor configured to drive one or more propellers of the aircraft, a capacitor configured to stabilize a direct current (DC) bus voltage, a first inverter circuit coupled to the capacitor and configured to convert the DC bus voltage to alternate current (AC) voltages to drive a first set of stator windings of the electrical motor, in response to a first pulse width modulation (PWM) vector, and a second inverter circuit coupled to the capacitor and configured to convert the DC bus voltage to AC voltages to drive a second set of stator windings of the electrical motor, in response to a second PWM vector. The first PWM vector and the second PWM vector are substantially equal and opposite vectors.

Abstract: An electric power tool includes: a motor; a driving circuit configured to drive the motor to output motive power; a control module configured to control the driving circuit; an energy storage element connected to the driving circuit; a current limiting element connected in series with the energy storage element and configured to charge the energy storage element with a first current; a switching element electrically connected in series with the energy storage element, connected in parallel with the current limiting element, and configured to charge or discharge the energy storage element with a second current. The electric power tool can avoid the occurrence of adverse situations such as generating electric sparks at the connection terminals of the electric power tool and of a battery pack when the battery pack is inserted into the electric power tool.

Abstract: An electrical circuit arrangement includes an inverter, a driver circuit and a protective circuit. The inverter includes a plurality of inverter switching elements each having a drive connection. The drive connection of at least one inverter switching element is connected to the driver circuit via a first switching element of the protective circuit (6). A drive connection of the first switching element is connected to a circuit node, which is connected to a first potential via a resistor and to a second potential via a second switching element.

Abstract: An abnormality diagnosis system configured to diagnose an abnormality of an electric drive system mounted on a mobile body to drive a motor for moving the mobile body, includes: an information acquisition unit configured to acquire a motor output information which is information related to an output state of the motor; an output state determination unit configured to determine whether the output state of the motor is in a low output state that does not contribute to a movement of the mobile body by using the motor output information; and a diagnosis execution unit configured to diagnose an abnormality of the electric drive system when it is determined that the motor is in the low output state.

Abstract: Methods, apparatuses and systems provide technology for a high frequency alternating-current (HFAC) distribution network for a vehicle that includes a plurality of HFAC zones coupled to a direct-current (DC) power source, the plurality of HFAC zones disbursed within the vehicle, where each HFAC zone includes a HFAC resonant inverter to convert DC power to HFAC power and a HFAC bus coupled to the HFAC resonant inverter, the HFAC bus to distribute the HFAC power to one or more loads. The technology includes a CLCL resonant tank circuit having two capacitors and two inductors, a push-pull circuit coupled to the CLCL resonant tank circuit, the push-pull circuit including a pair of switches, and a transformer to couple the inverter to the HFAC bus.

Abstract: A detection device includes: a sensor that outputs first and second sensor outputs behaving respectively differently according to a change in a rotation angle of an object; a target calculation unit that calculates first and second target angles hat are target values of first and second actual angles corresponding to the first and second sensor outputs; and a selection unit that selects, as a reference destination, one of the first and second sensor outputs for driving the object.

Abstract: A sensorless commutation error compensation system for a brushless motor, comprises: a brushless motor (200) and a commutation logic module circuit (100). The commutation logic module circuit (100) is connected to three virtual Hall signal output ends of the brushless motor (200), and used for receiving three virtual Hall signals output by the brushless motor (200), obtaining three error compensation angle signals on the basis of the three virtual Hall signals, respectively superimposing the three error compensation angle signals and the three virtual Hall signals to form superposition results, and controlling the brushless motor (200) to adjust commutation timing on the basis of the superposition results, so as to achieve commutation error compensation.

Abstract: A method and a circuit assembly are described with which, in a stepper motor, a mechanical load applied to the motor shaft of which can be detected without a sensor in a voltage-based operating mode in which a nominal coil current is generated by applying a predetermined coil voltage (Us) to the coil. The coil is connected in a bridge branch of a bridge circuit formed from a first to fourth semiconductor switch (S1, . . . S4), wherein the predetermined coil voltage (Us) is applied to the coil with a variable duty cycle (T) by switching the semiconductor switch in the form of at least one PWM voltage (U(A1), U(A2)).

Abstract: A mounting system including a base, a cavity with the base and open to a bottom portion of the base. A port extends from a top of the base into the cavity, and a vent is disposed in the top of the base and extends to the cavity. The port being configured to receive an injected sealant to fill the cavity with the injected sealant, thereby sealing around a penetration in a surface by a surface fastener. The injected sealant forcing air from inside the cavity out of the vent to ensure the injected sealant completely fills the cavity. A slide attached on the base protrudes above the top portion of the base and includes one or more guide rails for slidably receiving a bracket.

Abstract: An anti-torsion device of a solar tracker with a rotation axis, and solar tracker comprising the anti-torsion device, the device having a coupling part fixedly attached rotationally with respect to the rotation axis of the solar tracker; an extension element arranged mechanically and fixedly attached to the coupling part, further extending radially and externally with respect to the coupling part; and, an actuator and a counter-actuator arranged in a locked position, where they are in contact with the extension element, and a released position, where they are separated with respect to the extension element, when the anti-torsion device is fixedly arranged with respect to the rotation axis and in accordance with the locked position, the extension element is rotationally immobilized so that the rotation of the coupling part is further prevented.

Abstract: A photovoltaic array fault diagnosis method based on composite information is provided. The method includes: collecting and preprocessing composite information data of photovoltaic array working state, including image data and text data; using the image data of photovoltaic array working state to train a pre-established fault classification model of deep convolutional neural network, to thereby obtain an image fault classification model; using the text data of photovoltaic array working state to train a pre-established fault classification model based on a support vector machine, to thereby obtain a text fault classification model; fusing the image fault classification model and the text fault classification model by logistic regression algorithm to obtain a fusion model, and training the fusion model using the composite information data of photovoltaic array working state to thereby obtain the photovoltaic array fault diagnosis model.

Abstract: An intelligent detection system includes an image module, a target detection module, and a physical model processing module. The target detection module runs a scanning mode on the target object and controls the image module to capture target images of the target object with different physical properties under the scanning mode. The scanning mode is allowed to be based on luminescence or thermal radiation emitted by variation of time, voltage, current, or illumination. The physical model processing module receives the target images and carries out an image stacking process with each target image based on different physical properties, generating a detection result image through physical formula of electronic circuit in cooperation with a chromaticity coordinate diagram.

Abstract: A power management circuit operable with group delay is provided. The power management circuit includes a transceiver circuit configured to generate a digital target voltage and digitally delay the digital target voltage to generate multiple delayed digital target voltages. Accordingly, the transceiver circuit can generate a windowed digital target voltage in multiple delay tolerance windows based on the delayed digital target voltages. Since the windowed digital target voltage can tolerate a certain amount of group delay in each of the group delay tolerance windows, an envelope tracking (ET) voltage generated based on an analog version of the windowed digital target voltage can therefore tolerate the group delay in each of the group delay tolerance windows as well. As a result, it is possible to avoid distortion in the ET voltage to help improve performance of the power management circuit.

Abstract: A barely Doherty dual envelope tracking (BD2E) circuit has a transmitter chain that includes an envelope tracking (ET) circuit that controls a Doherty dual power amplifier array. The ET circuit provides two control signals (supply voltage signals) that are used to control or modulate a carrier amplifier and a peaking amplifier independently of one another. The BD2E circuit includes an improved impedance inverter that isolates the peaking amplifier from the carrier amplifier to allow this independent control. By providing independent control, greater linearity may be provided while preserving the efficiency of the circuit.

Abstract: Monolithic microwave integrated circuits (MMICs) tolerant to electrical overstress are provided. In certain embodiments, a MMIC includes a signal pad that receives a radio frequency (RF) signal, and an RF circuit coupled to the RF signal pad. The RF circuit includes a transistor layout, an input field-effect transistor (FET) implemented using a first portion of a plurality of gate fingers of the transistor layout, and an embedded protection device electrically connected between a gate and a source of the input FET and implemented using a second portion of the plurality of gate fingers. The MMIC is tolerant to electrical overstress events, such as field-induced charged-device model (FICDM) events.

Abstract: A power amplification circuit includes a first amplifier that amplifies a signal split from an input signal, a second amplifier that amplifies a signal having a different phase from the aforementioned signal, third and fourth amplifiers, and a matching network. The matching network includes a first wiring having a first end connected to an output terminal of the first amplifier and a second end connected to an input terminal of the third amplifier, a second wiring having a first end connected to the input terminal of the third amplifier, and electromagnetically coupled to the first wiring, a third wiring having a first end connected to an output terminal of the second amplifier and a second end connected to an input terminal of the fourth amplifier, and a fourth wiring having a first end connected to the input terminal of the fourth amplifier, and electromagnetically coupled to the third wiring.

Abstract: A differential transimpedance amplifier (DTIA) includes a first input, a second input, a first output, and a second output. The DTIA also includes a first inverter and a second inverter connected in series to the first input. The DTIA further includes a third inverter and a fourth inverter connected in series to the second input. The first inverter and the fourth inverter receive a first supply voltage from a first voltage regulator. The second inverter and the third inverter receive a second supply voltage from a second voltage regulator. The first supply voltage changes (i) based on a difference between voltages on the first output and the second output and (ii) while the second supply voltage remains fixed.

Abstract: Aspects of the disclosure relate to a radio frequency phase shifter. An example includes an amplification stage to produce an amplified voltage, the amplification stage having a first amplifier with a first input coupled to a first output of a hybrid coupler and a second amplifier with a complementary second input coupled to a complementary second output of the hybrid coupler. A vector modulation stage coupled to the amplification stage receives the amplified voltage and produces a modulated vector, the vector modulation stage has an in-phase section and a quadrature section to control the phase of the modulated vector in response to a phase control signal. A varactor coupled across the first input and the second input of the amplification stage adjusts the capacitance between the first input and the second input in response to a capacitance control signal.

Abstract: A switched capacitor modulator (SCM) includes a RF power amplifier. The RF power amplifier receives a rectified voltage and a RF drive signal and modulates an input signal in accordance with the rectified voltage to generate a RF output signal to an output terminal. A reactance in parallel with the output terminal is configured to vary in response to a control signal to vary an equivalent reactance in parallel with the output terminal. A controller generates the control signal and a commanded phase. The commanded phase controls the RF drive signal. The reactance is at least one of a capacitance or an inductance, and the capacitance or the inductance varies in accordance with the control signal.

Abstract: There is provided a monolithic microwave integrated circuit, MMIC, front-end module which may include: a gallium nitride structure supported by a silicon substrate, a silicon-based transmit/receive switch having a transmit mode and a receive mode, a transmit amplifier configured to amplify an outgoing signal to be transmitted by said MMIC front-end module, wherein said transmit amplifier is electrically connected to said transmit/receive switch, wherein said transmit amplifier comprises a gallium nitride high-electron-mobility transistor, HEMT, formed in said gallium nitride structure. The MMIC front-end module may further include a receive amplifier configured to amplify an incoming signal received by said MMIC front-end module, wherein said receive amplifier is electrically connected to said transmit/receive switch, wherein said receive amplifier may include a gallium nitride HEMT formed in said gallium nitride structure.

Abstract: A non-isolated power supply. A positive power and a negative power are respectively formed by charging a +VCC1 energy storage filter and a ?VCC2 energy storage filter connected in series and discharging the +VCC1 energy storage filter 102 and the ?VCC2 energy storage filter. The output positive and negative power may be differently combined by changing the capacities of the +VCC1 energy storage filter and the ?VCC2 energy storage filter and may be equal or unequal.

Abstract: The present invention provides monoclonal antibodies that bind to the Factor XII (FXII) protein, and methods of use thereof. In various embodiments of the invention, the antibodies are fully human antibodies that bind to FXII and to the activated form of FXII (FXIIa). In some embodiments, the antibodies of the invention are useful for inhibiting or neutralizing FXII activity, thus providing a means of treating or preventing a disease, disorder or condition associated with thrombosis in humans.

Abstract: Disclosed is a system comprising a plurality of operational amplifiers, each operational amplifier having individually adjustable operational parameters, and a trimming circuit. The trimming circuit includes successive approximation register (SAR) logic that determines associated memory values. The trimming circuit changes the adjustable operational parameters of each operation amplifier based on the associated memory values.

Abstract: An amplifier power attenuator utilizes an amplified audio feedback signal from an audio amplifier (which is driving a loudspeaker), along with a user-set impedance and a maximum voltage set-point reflective of the operational parameters of the loudspeaker, to attenuate an audio signal prior to amplification thereby preventing damage to the loudspeaker. The impedance of a variable impedance optocoupler is changed to adjust the attenuation of the audio signal to one of a plurality of predetermined attenuation levels responsive to an error between a voltage level of the feedback signal and the maximum voltage set-point. The error is reflected in a counter value having a linear or non-linear relationship with the error dependent upon a magnitude of the error; the counter value is assessed against a plurality of target values associated with respective ones of the predetermined attenuation levels to identify the attenuation to be applied to the audio signal.

Abstract: Various embodiments provide methods, apparatuses, systems, or computer program products for providing a signal to an electrode of a quantum computer. In an example embodiment, the system comprises noise mitigation circuitry comprising a signal generator, a gain stage, and a filter stage. The signal generator may be comprised of a plurality of voltage sources. The controller causes the signal generator to generate a signal, and the signal is provided to the electrode through the noise mitigation circuitry to cause at least a portion of the system to perform a function.

Abstract: A method for fabricating a film bulk acoustic resonator (FBAR) filter device is provided. The method includes: forming a first electrode of each one of a first resonator and a second resonator on a first surface of a piezoelectric layer, forming a first passivation layer of each one of the first resonator and the second resonator on a corresponding one of the first electrodes, forming a second electrode of each one of the first resonator and the second resonator on a second surface of the piezoelectric layer, conducting a radio frequency (RF) performance test on the FBAR filter device, adjusting a thickness of the second electrode of the first resonator based on a result of the RF performance test, and forming a second passivation layer of each one of the first resonator and the second resonator on a corresponding one of the second electrodes.

Abstract: A method for forming an aluminum nitride layer (310, 320) comprises the provision of a substrate (100) and the forming of a patterned metal nitride layer (110). A bottom electrode metal layer (210) is formed on the exposed portions (101) of the substrate. An aluminum nitride layer portion (320) grown above the exposed portion (101) of the substrate (100) exhibits piezoelectric properties. An aluminum nitride layer portion (310) grown above the patterned metal nitride layer (110) exhibits no piezoelectric properties (310). Both aluminum nitride layer portions (320, 310) are grown simultaneously.

Abstract: An acoustic wave device, includes piezoelectric layer having an upper piezoelectric surface and a lower piezoelectric surface; an upper electrode formed on the upper piezoelectric surface; a lower electrode; a support layer including a non-monocrystalline insulating material; and a lower cover, wherein the lower electrode and the support layer formed between the lower cover and the lower piezoelectric surface.

Abstract: Aspects of this disclosure relate to a bulk acoustic wave device with a floating raised frame structure. The bulk acoustic wave device includes a first electrode, a second electrode, a piezoelectric layer positioned between the first electrode and the second electrode, and a floating raised frame structure positioned on a same side of the piezoelectric layer as the first electrode and spaced apart from the first electrode. The floating raised frame structure is at a floating potential. The bulk acoustic wave device can suppress a raised frame mode. Related methods, filters, multiplexers, radio frequency front ends, radio frequency modules, and wireless communication devices are disclosed.

Abstract: A filter circuit comprises a main operating unit (MU) arranged in the series signal line providing most of the filter function of the filter circuit. A micro acoustic last series resonator (RLs) as a last element of the main operating unit in the series signal line is prone to excite a spurious mode that is damped with a final series capacitance (CEs) circuited between the last element and the antenna terminal (AT).

Abstract: A configurable micro-acoustic RF filter comprises first and second filter subsections (140, 150) and at least one switch (160) to selectively bypass or activate the second filter subsection (150). The filter sections include at least one serially connected and at least one shunt connected micro-acoustic resonator.

Abstract: A compound acoustic wave filter device comprises a support substrate having an including two or more circuit connection pads. An acoustic wave filter includes a piezoelectric filter element and two or more electrodes. The acoustic wave filter is micro-transfer printed onto the support substrate. An electrical conductor electrically connects one or more of the circuit connection pads to one or more of the electrodes.

Abstract: A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, and a second capacitor. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The second capacitor is coupled to a reference voltage through the third switch and the sixth switch, coupled to the input voltage through the fifth switch, and coupled to the control terminal of the first transistor through the fourth switch.

Abstract: A switching device 1 includes a SiC semiconductor chip 11 which has a gate pad 14, a source pad 13 and a drain pad 12 and in which on-off control is performed between the source and the drain by applying a drive voltage between the gate and the source in a state where a potential difference is applied between the source and the drain, a sense source terminal 4 electrically connected to the source pad 13 for applying the drive voltage, and an external resistance (source wire 16) that is interposed in a current path between the sense source terminal 4 and the source pad 13, is separated from sense source terminal 4, and has a predetermined size.

Abstract: A short-circuit protection circuitry is adapted for a power transistor. The short-circuit protection circuitry includes a first diode, a first resistor, a voltage dividing circuit, a gate voltage generator, a pull-down circuit, and a control signal generator. The first diode is coupled to a drain of the power transistor. The first resistor is coupled between the first diode and the power transistor. The voltage dividing circuit is coupled between a gate and a source of the power transistor to generate a dividing voltage. The gate voltage generator provides a gate voltage to the gate of the power transistor according to a first driving signal and a second driving signal. The pull-down circuit pulls down the gate voltage according to a control signal. The control signal generator generates the control signal according to the first driving signal, a voltage on the anode of the first diode and the dividing voltage.

Abstract: A semiconductor device includes: a first transistor having a first electrode, a second electrode, and a third electrode coupled to a load; a second semiconductor having a first electrode, a second electrode, and a third electrode configured to output a second current corresponding to a first current that flows through the load; and a third transistor coupled in series with the second transistor, to thereby receive the second current; an output circuit configured to output a second voltage by amplifying a difference between a first voltage at the third electrode of the first transistor and a reference voltage, and a fourth voltage by amplifying a difference between a third voltage at the third electrode of the second transistor and the reference voltage; and an operational amplifier configured to control the third transistor, based on the second and fourth voltages such that the first voltage and the third voltage match.

Abstract: A trigger assembly, for use with a power tool having an electric motor, includes a trigger, a conductor coupled for movement with the trigger, and a printed circuit board. The printed circuit board has an inductive sensor thereon responsive to relative movement between the conductor and the inductive sensor caused by movement of the trigger. An output of the inductive sensor is used to activate the electric motor.

Abstract: Various implementations described herein are directed to a device having a scan chain that receives a multi-bit input, provides a multi-bit output, and provides a multi-bit multiplexer output based on the multi-bit input and the multi-bit output. The device may have an error-bit generator that receives the multi-bit multiplexer output, receives a portion of the multi-bit input, receives a portion of the multi-bit output, and provides an error-bit output based on the multi-bit multiplexer output, the portion of the multi-bit input, and the portion of the multi-bit output.

Abstract: A magnetic logic device having two magnetic elements and a conductive element coupled to the two magnetic elements and arranged at least substantially perpendicular to the magnetic elements, wherein the device is configured, for each magnetic element, to have a magnetisation state with a perpendicular easy axis, and to switch the magnetisation state in response to a spin current generated in the magnetic element in response to a write current applied to the magnetic element, and configured to generate, as an output, a Hall voltage across the conductive element in response to a respective read current applied to each magnetic element, wherein a magnitude of the Hall voltage is variable, depending on a direction of the magnetisation state of each magnetic element and a direction of the respective read current applied to each magnetic element, for the device to provide outputs corresponding to one of a plurality of logical operations.

Abstract: A semiconductor device includes a temperature-independent current generator that generates a reference current substantially independent of temperature and a mirror current that is a substantial duplicate of the reference current, a pulse signal generator that samples the mirror current so as to generate a pulse signal, and a counter that obtains a number of pulse signals generated by the pulse signal generator, that permits the pulse signal generator to generate a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is less than a predetermined threshold value, and that inhibits the pulse signal generator from generating a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is equal to the predetermined threshold value. A method for monitoring a temperature of the semiconductor device is also disclosed.

Abstract: A device is provided that includes a counter circuit configured to count cycles of an input clock signal and to generate an output clock signal periodically based on a cycle count of the input clock signal; a multi-phase clock generator configured to generate a plurality of multi-phase clock signals from a system clock signal; a multiplexer circuit coupled to the multi-phase clock generator and configured to provide a multi-phase clock signal selected from the plurality of multi-phase clock signals to the counter circuit as the input clock signal; and a selection circuit configured to provide a selection signal to the multiplexer circuit periodically to switch the multi-phase clock signal provided to the counter circuit from a current multi-phase clock signal to a next multi-phase clock signal selected from the plurality of multi-phase clock signals.

Abstract: A bidirectional RF circuit, preferably including a plurality of terminals, a switch, a transistor, a coupler, and a feedback network. The circuit can optionally include a drain matching network, an input matching network, and/or one or more tuning inputs. In some variations, the circuit can optionally include one or more impedance networks, such as an impedance network used in place of the feedback network; in some such variations, the circuit may not include a coupler, switch, and/or input matching network. A method for circuit operation, preferably including operating in an amplifier mode, operating in a rectifier mode, and/or transitioning between operation modes.

Abstract: According to one embodiment, an electronic circuitry includes a clock generation circuit configured to generate a first clock signal; a first conversion circuit configured to convert an input signal into a first signal having a frequency corresponding to the first clock signal based on the first clock signal; a first electromagnetic field coupler configured to transmit the first signal by electromagnetic field coupling; a second electromagnetic field coupler configured to transmit the first clock signal by electromagnetic field coupling; and a second conversion circuit configured to convert the first signal transmitted by the first electromagnetic field coupler into a second signal having a frequency corresponding to the input signal, based on the first clock signal transmitted by the second electromagnetic field coupler.

Abstract: A device includes a clock input circuit that when in operation receives a clock signal and transmits an internal clock signal based on the clock signal. The device also includes an internal clock generator coupled to the clock input circuit to receive the internal clock signal, wherein the internal clock generator comprises clock adjustment circuitry that when in operation generates a phase controlled internal clock signal having subsequent clock edges based upon a single clock edge of the internal clock signal, wherein the phase controlled internal clock signal comprises a first frequency as a multiple of a second frequency of the internal clock signal.

Abstract: A clock data recovery circuit includes a bang bang phase detector receiving data and a clock signal and determining whether a phase of the clock signal leads or lags a phase of the data, a digital loop filter receiving an output of the bang bang phase detector and filtering input jitter, an accumulator accumulating an output from the digital loop filter, an encoder encoding an output of the accumulator to generate a phase interpolation code, and a phase interpolator configured to generate the clock signal with an output phase in accordance with the phase interpolation code. The digital loop filter comprises a first sigma delta modulation (SDM) arithmetic block circuit connected to the bang bang phase detector.

Abstract: The present invention discloses a signal gain tuning circuit having adaptive mechanism. An amplifier receives an analog signal to generate a tuned analog signal to an ADC circuit to further generate a digital signal. A gain control capacitor array and the amplifier together determine a gain of the tuned analog signal. The control circuit receives an actual level of the digital signal to determine an offset of the digital signal and an estimated level to generate a tuning control signal. Each of coarse-tuning capacitors of a coarse-tuning capacitor array corresponds to a first tuning amount relative to a maximal gain. Each of fine-tuning capacitors of a fine-tuning capacitor array corresponds to a second tuning amount relative to the maximal gain. A tuning capacitor enabling combination of the coarse-tuning and fine-tuning capacitor arrays are determined according to the tuning control signal to tune the gain and decrease the offset.

Abstract: An input stage for an analog/digital converter, an analog/digital converter and a method for testing analog/digital converters with successive approximation are disclosed. At an input stage, an input signal is supplied via a first transistor arrangement of a sampling capacitor arrangement. The sampling capacitor arrangement can be optionally connected to ground or to a reference voltage by way of a second transistor arrangement and a switch apparatus.

Abstract: A digital slope analog to digital converter includes a charge injection digital to analog converter (DAC) circuit, a comparator circuit, a detector circuit, and a control logic circuitry. The charge injection DAC circuit respectively samples input signals via first and second capacitors and generates a first signal via the first capacitor and a second signal via the second capacitor. The comparator circuit compares the first signal with the second signal to generate decision signals. The detector circuit generates a flag signal according to the decision signals. The control logic circuitry generates an enable signal according to the flag signal and generates a digital output when the comparator circuit detects a crossing point of the first and second signals. The charge injection DAC circuit gradually adjusts charges stored in the first and/or the second capacitor according to the enable signal until the crossing point is detected.

Abstract: A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.