Abstract: A solid state drive case includes a lower cover having a sidewall defining an internal space. The sidewall includes a protrusion disposed on an end portion of the sidewall. An upper cover has a first surface directly contacting the sidewall of the lower cover and a second surface opposite to the first surface. The upper cover has a hole overlapping the protrusion and configured to receive the protrusion. A sealing label is attached to the second surface of the upper cover. The sealing label has an area that is less than an area of an entirety of the second surface of the cover. At least a portion of the sealing label is attached to an end portion of the protrusion.

Abstract: A display device is provided. The display device includes a sliding module including a reel; and a display module. The display module is disposed on the sliding module and includes a flexible display panel and a support layer disposed under the flexible display panel, wherein the support layer is patterned to form a plurality of holes, the reel is provided with a plurality of protrusions, and each of the holes is configured to respectively engage to each of the protrusions.

Abstract: A rollable display device according to one aspect of the present invention comprises: a roller; a display unit which is rolled around the roller, and which comprises a display panel and a module cover that is laminated on the display panel so as to face same; a link assembly for moving the display unit upward and downward; and a motor assembly for driving the link assembly, wherein the module cover can comprise: a module cover having a yield strain of 0.5% or higher; and a film part which is laminated on the module cover and which has an elongation rate higher than that of the module cover.

Abstract: A display device includes a display panel sliding in a first direction. A panel storage compartment is configured to accommodate the display panel therein and to assist a sliding operation of the display panel in the first direction. A plurality of segments are attached to a lower surface of the display panel, each of the plurality of segments are extended in a second direction intersecting the first direction, and are spaced apart from one another in the first direction. Bearings are disposed inside the plurality of segments and are at least partially exposed by the plurality of segments. The panel storage compartment includes guide rails engaged with the bearings.

Abstract: A sliding display apparatus comprises a display panel including first to fourth side surfaces, a case configured to accommodate the display panel, a cover configured to cover an opened upper surface of the case and including a hole provided at one side thereof, a wire driving part connected to at least one wire connected to a lower surface of the display panel, and a sliding controlling part configured to control the wire driving part, and an upper portion of the display panel is exposed through the hole provided at the cover.

Abstract: A display apparatus including display panel, a rear case to cover a rear of the display panel and the rear case including a cable fixing hole to which a cable is fixed, a connector connected to the cable and fastened to the rear case so that the cable is connected to the rear case, a cable holder to surround a part of the cable and fixed to the cable fixing hole so that the cable is fixed to the rear case, and a clamp to fix the cable holder to the cable fixing hole, wherein the clamp includes a first hook to be fixed to the cable fixing hole, and a second hook having a different shape than a shape of the first hook and to be fixed to the cable fixing hole to have a greater fixing force than a fixing force of the first hook.

Abstract: The present application provides a folding display device. The folding display device comprises a bending mechanism and a front frame structure. The bending mechanism comprises a first support part and a second support part that are rotatably connected to one side of the bending part, and a third support part and a fourth support part that are rotatably connected to another side of the bending part. The front frame structure comprises a first front frame part connected to the first support part, a second front frame part connected to the second support part, a third front frame part connected to the third support part, and a fourth front frame part connected to the fourth support part.

Abstract: A flexible display panel and an electronic device are provided. The flexible display panel includes a flexible display panel body and a support layer disposed on a side of the flexible display panel body. The support layer includes a first bendable portion and a second bendable portion that are adjacent to each other. The first bendable portion includes a first bendable sub-portion and a second bendable sub-portion that are both provided with openings. The second bendable portion includes a third bendable sub-portion and a fourth bendable sub-portion that are both provided with openings.

Abstract: A hinge assembly for an electronic device, the hinge assembly being moveable between an unfolded position and at least a first folded end position, and comprising a row of interconnected and abutting hinge blades and at least one linear actuator. The hinge blades are aligned in a common plane when the hinge assembly is in the unfolded position, each hinge blade being rotated relative neighboring hinge blades around a first hinge assembly rotation axis, when the hinge assembly is moved to the first folded end position. The linear actuator comprises a rotation shaft and a plurality of linear drive arrangements having different lengths. The rotation shaft extends in parallel with the first hinge assembly rotation axis and comprises sections having different diameters.

Abstract: A window includes a base layer and a hard coating layer on the base layer. The hard coating layer includes a first layer on the base layer and of a first thickness, and a second layer on the first layer and of a second thickness. The second layer includes an antistatic agent. The hard coating layer has a hardness reduction rate of 50 percent (%) or less expressed as follows. H = ( 1 - D 1 D 2 ) × 100 In the equation above, H is a hardness reduction rate (%) of a target layer, D1 is a hardness reduction rate measured from the target layer at a temperature of 60 degrees Celsius (° C.) with a relative humidity of 93%, and D2 is a hardness reduction rate measured from the target layer at a room temperature with a relative humidity of 30%.

Abstract: A dual connect switch module may include a first set of pluggable panel connectors on a first side of a substrate of the switch and a second set of pluggable panel connectors on an opposing second side of the substrate. The switch module further includes a switch Integrated Circuit (IC) mounted between the first side and the second side, where the switch IC is connected to the first set of pluggable panel connectors and to the second set of pluggable panel connectors. A cable can be used to connect at least one pluggable panel connector of the first set of pluggable panel connectors and/or of the second set of pluggable panel connectors with a port of an external network device. In some examples, the switch and substrate may further include a management module that manages one or more on-board functions of the switch module.

Abstract: An alternating current/direct current input device includes an appliance input socket and an information and communications technology (ICT) device. The ICT device is powered by the appliance input socket. The appliance input socket includes a ground contact, a positive electrode contact, a negative electrode contact, and a signal switch. A contact depth of the signal switch in the appliance input socket is less than a contact depth of the positive electrode contact or the negative electrode contact in the appliance input socket. The signal switch is configured to generate a control signal when a direct current connector is separated from the appliance input socket. The control signal can be used to enable the ICT device to disconnect the appliance input socket from a conductive electrode of the direct current connector after the ICT device enters a no load state.

Abstract: A controller is described that a building design can be input into, the building design comprising inputting a layout, predefined resources and positions for resources. within the layout. The resources may have a predefined physics nature that includes physics equations, allowable inputs and outputs, etc. The system then can determine how many controllers are needed of what type, and create a guided wiring system. In some implementations a user can control certain aspects of the wiring system, such as how full the individual controllers are and how much money is to be spent on labor versus money spent on equipment.

Abstract: A bundled cable assembly comprises groups of jumpers arranged to define a main section and terminal sections that each extend from the main section. The main section includes a plurality of tap locations at spaced apart locations along a length of the main section. At least some of the jumpers are bundled together in the main section between the tap locations. The terminal sections each extend from one of the tap locations. Each of the jumpers includes a first jumper end in one of the terminal sections and a second jumper end in another of the terminal sections. The groups of jumpers are arranged such that each of the terminal sections comprises the first jumper ends the jumpers from a respective group of the groups of jumpers and at least one second jumper end from each of the other groups of jumpers.

Abstract: Multimedia poles, light poles and/or other structures capable of facilitating multiple operations, such as sensing, lighting, messaging, etc., optionally in a connected manner whereby devices positioned at different locations may communication to implement coordinated activities, are contemplated.

Abstract: A heat dissipation system and an electronic device. The heat dissipation system configured to circulate working fluid and to cool heat source. Heat dissipation system includes casing, first tube, second tube, condenser and flow rate controller. Partition is fixed in the base and is located in the accommodation space to divide the accommodation space into a first and a second accommodation space. The first accommodation space is located above the second accommodation space along a gravitational direction. The inlet is in fluid communication with the first accommodation space. The outlet is in fluid communication with the second accommodation space. The partition includes a plurality of drip holes. The first and the second accommodation spaces are in fluid communication with each other via the drip holes. The working fluid is configured to drip onto the heat source via the plurality of drip holes.

Abstract: A heat sink according to one embodiment of the present invention comprises: a main heat sink; a heat pipe mounted in a groove formed on one surface of the main heat sink; a heat dissipation member which is formed above the heat pipe and transfers heat generated from a heat generation component to the heat pipe; and an elastic member which is mounted in a space formed inside the heat dissipation member and applies pressure to the main heat sink.

Abstract: Systems and methods for cooling a datacenter are disclosed. In at least one embodiment, a cold plate is coupled to a condenser section of a heat pipe and to a primary computing device, with the heat pipe coupled to an auxiliary computing device at an evaporator section of the heat pipe, so that the cold plate draws heat from the primary computing device and from the heat pipe.

Abstract: Among two main surfaces of a heat dissipation member, one main surface is curved to be convex in an outward direction and the other convex in an inward direction. When a straight line passing through both endpoints P1 and P2 of the curve is l1, a point at which a distance to l1 on the curve is maximum is Pmax, an intersection point between l1 and a perpendicular drawn from Pmax to l1 is P3, a middle point of a line segment P1P3 is P4, an intersection point between the curve and a straight line that passes through P4 and is perpendicular to l1 is Pmid, a length of the line segment P1P3 is L, a length of a line segment P3Pmax is H, and a length of a line segment P4Pmax is h, (2 h/L)/(H/L) is 1.1 or more.

Abstract: An electronic device is provided. The electronic device includes a display including a first area and a second area, a first housing forming a first space positioned on a rear surface of the first area, a second housing forming a second space positioned on a rear surface of the second area, a hinge assembly for causing the first area and the second area to be in a first state of forming substantially the same plane or to be in a second state of facing each other, and a plurality of front heat conduction members forming a heat conduction path between the hinge assembly and the display.

Abstract: An equipment cooling rack device, with a cooling cabinet, having a cooled area, adapted for holding multiple different heat creating structures to be cooled; a cooling structure, coupled to the cooling cabinet, and providing a first cooling coil for a left side of the rack and a second cooling coil for a right side of the rack, and orthogonal fans. The fans and coolant are controlled according to thermographic color of the cooling cabinet.

Abstract: Systems and methods for cooling a datacenter are disclosed. In at least one embodiment, a first interfacing flow controller includes a sensor and is associated with a first server tray of a rack, so that a first interfacing flow controller can receive sensor inputs and can communicate with a second interfacing flow controller by a communication line there between, where a second interfacing flow controller can be associated with a coolant distribution unit (CDU) to cause a balance of coolant flow to be provided from a CDU to one or more second server trays based in part on a change in a coolant flow to a first server tray as indicated by such sensor inputs.

Abstract: A radiator and an electrical device. The radiator includes a heat dissipation substrate and a heat dissipation assembly, wherein the heat dissipation substrate is provided with an installation position for installing the heat dissipation assembly, the installation position is provided with a stress release groove, and the heat dissipation assembly is welded on the installation position. According to the radiator provided in the present application, the stress release groove is provided in the installation position for installing the heat dissipation assembly on the heat dissipation substrate, such that the installation position is isolated from the connecting position of the heat dissipation assembly to form an island structure, and the island structure reduces stress pulling caused by thermal deformation of the two materials of the heat dissipation assembly and the radiator.

Abstract: A cooling device for a power electronics module for cooling a power electronic assembly of the power electronics module includes a heatsink for dissipating waste heat from at least one power electronic component arranged on a circuit board, and at least one heat-conducting element for providing a local heat-conducting path between the at least one power electronic component and the heatsink. Heat-conducting element is formed as a cooling adapter and is separate from the heatsink and has a heat-conducting core, which can be arranged between the heat sink and the power electronic assembly and is designed to bridge a distance between the at least one power electronic component and the heatsink.

Abstract: Disclosed is a display device. The display device of the present disclosure includes a display panel; a corrugate panel located in a rearward direction of the display panel, the corrugate panel including a front skin facing the display panel, a rear skin facing the front skin in a rearward direction of the front skin, and a wave-shaped core located between the front skin and the rear skin; a module cover coupled to the corrugate panel in a rearward direction of the corrugate panel; and a back cover coupled to the module cover in a rearward direction of the module cover.

Abstract: The device consists of a container manufactured from a metamaterial with the property of transparency to visible light, for the holding of electrical or electronic devices, which electromagnetically protects the same and renders them electromagnetically undetectable. The purpose of the device is to guarantee user confidentiality in the use of the electromagnetic waves associated with telecommunications, by means of the use of a type of container that encloses any type of telecommunication device or appliance, with the potentiality that the insertion thereof into said container prevents the detection by means of electromagnetic waves of said appliance, and therefore makes impossible the tracing of said appliance by electromagnetic remote sensing means, including mobile telephony, radiofrequencies, or satellite telecommunication means such as GPS, Galileo, or other systems, without it being necessary to switch off said appliance beforehand.

Abstract: Provided is a conformal electromagnetic interference (EMI) shielding film including a thermal-forming film layer and an electrically conductive film layer. The thermal-forming film layer is configured to conformally coat over one or more electronic components mounted on a substrate with application of heat. The electrically conductive film layer is formed on an opposite side of the thermal-forming film layer from the substrate and has a plurality of voids that are configured to deform during the application of heat and allow the electrically conductive film layer to conform together with the thermal-forming film layer.

Abstract: A novel memory device is provided. Over a driver circuit layer, N memory layers (N is a natural number greater than or equal to 2) including a plurality of memory cells provided in a matrix are stacked. The memory cell includes two transistors and one capacitor. An oxide semiconductor is used as a semiconductor included in the transistor. The memory cell is electrically connected to a write word line, a selection line, a capacitor line, a write bit line, and a read bit line. The write bit line and the read bit line extend in the stacking direction, whereby the signal propagation distance from the memory cell to the driver circuit layer is shortened.

Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

Abstract: Methods, apparatuses, and systems related to a sense line and cell contact for a semiconductor structure are described. An example apparatus includes a first source/drain region and a second source/drain region, where the first source/drain region and the second source/drain region are separated by a channel, a gate opposing the channel, a sense line material coupled to the first source/drain region by a cell contact, where the cell contact is made from a combination of a first polysilicon material and a second polysilicon material, and a storage node coupled to the second source/drain region.

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, in which a plurality of active areas arranged in an array are provided; buried word lines located in the substrate, in which each of the active areas intersects with two of the buried word lines; grooves located in an upper surface of the substrate, in which each of the grooves is located between two of the buried word lines in each of the active areas; bit line contact layers filling the grooves; insulating layers distributed between two of the grooves, in which a thickness between upper surfaces of the insulating layers and the upper surface of the substrate is smaller than a thickness between upper surfaces of the bit line contact layers and the upper surface of the substrate; and bit line conducting layers, covering the bit line contact layers and the insulating layers.

Abstract: A transistor, a memory and a method of forming the same are disclosed. The transistor includes a gate dielectric layer (200) having an upper portion (200b) and a lower portion (200a). The upper portion (200b) is multi-layer structure having an increased thickness without changing a thickness of the lower portion (200a). In this way, gate-induced drain current leakage of the transistor can be mitigated at uncompromised performance thereof. Additionally, the upper portion (200b) designed as multi-layer structure having an increased thickness can facilitate flexible adjustment in parameters of the upper portion (200b). The memory device includes dielectric material layers (DL), which are formed in respective word line trenches and each have an upper portion and a lower portion. In addition, in both trench isolation structures (STI) and active areas (AA), the upper portion of the dielectric material layers (DL) has a thickness greater than a thickness of the lower portion.

Abstract: Some embodiments include a method of forming an integrated assembly. A structure is provided to have conductive lines, and to have rails over the conductive lines and extending in a direction which crosses the conductive lines. Each of the rails includes pillars of semiconductor material. The rails have sidewall surfaces along spaces between the rails. The pillars have upper segments, middle segments and lower segments. First-material liners are formed along the sidewall surfaces of the rails. A second material is formed over the liners. First sections of the liners are removed to form gaps between the second material and the sidewall surfaces of the rails. Second sections of the liners remain under the gaps. Conductive material is formed within the gaps. The conductive material is configured as conductive lines which are along the middle segments of the pillars.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell and first, second, and third data lines located over a substrate. The memory cell includes a first transistor and a second transistor. The first transistor includes a charge storage structure located on a first level of the apparatus, and a first channel region electrically separated from the charge storage structure. The second transistor includes a second channel region located on a second level of the apparatus and electrically coupled to the charge storage structure. The first and second data lines are located on a third level of the apparatus and electrically coupled to the first channel region. The first level is between the substrate and the third level. The third data line is electrically coupled to the second channel region and electrically separated from the first channel region.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a first semiconductor layer, an array of NAND memory strings, and a first peripheral circuit of the array of NAND memory strings. Sources of the array of NAND memory strings are in contact with a first side of the first semiconductor layer. The first peripheral circuit includes a first transistor in contact with a second side of the first semiconductor layer opposite to the first side. The second semiconductor structure includes a second semiconductor layer and a second peripheral circuit of the array of NAND memory strings. The second peripheral circuit includes a second transistor in contact with the second semiconductor layer.

Abstract: A semiconductor memory includes a substrate, a source line layer above the substrate in a memory region and a peripheral region of the substrate, a first insulating layer above the source line layer, a first conductive layer on the first insulating layer in the memory and peripheral regions, an alternating stack of a plurality of second insulating layers and a plurality of second conductive layers on the first conductive layer in the memory region, and a plurality of pillars extending through the alternating stack of the second insulating layers and the second conductive layers, the first conductive layer, and the first insulating layer in the memory region. A bottom end of each of the pillars is in the source line layer in a thickness direction. A carrier density of the source line layer is higher in the memory region than in the peripheral region.

Abstract: A method comprising forming a stack precursor comprising alternating first materials and second materials, the first materials and the second materials exhibit different melting points. A portion of the alternating first materials and second materials is removed to form a pillar opening through the alternating first materials and second materials. A sacrificial material is formed in the pillar opening. The first materials are removed to form first spaces between the second materials, the first materials formulated to be in a liquid phase or in a gas phase at a first removal temperature. A conductive material is formed in the first spaces. The second materials are removed to form second spaces between the conductive materials, the second materials formulated to be in a liquid phase or in a gas phase at a second removal temperature. A dielectric material is formed in the second spaces. The sacrificial material is removed from the pillar opening and cell materials are formed in the pillar opening.

Abstract: The application discloses an integrated memory device, a manufacturing method and an operation method thereof. The integrated memory cell includes: a first memory cell; and an embedded second memory cell, serially coupled to the first memory cell, wherein the embedded second memory cell is formed on any one of a first side and a second side of the first memory cell.

Abstract: A three-dimensional semiconductor memory device including a first peripheral circuit including different decoder circuits, a first memory on the first peripheral circuit, the first memory including a first stack structure having first electrode layers stacked on one another and first inter-electrode dielectric layers therebetween, a first planarized dielectric layer covering an end of the first stack structure, and a through via that penetrates the end of the first stack structure, the through via electrically connected to one of the decoder circuits, and a second memory on the first memory and including a second stack structure having second electrode layers stacked on one another and second inter-electrode dielectric layers therebetween, a second planarized dielectric layer covering an end of the second stack structure, and a cell contact plug electrically connecting one of the second electrode layers to the through via.

Abstract: A semiconductor structure and a manufacturing method thereof are present. The method includes: forming a first mask layer having an etching window, wherein the first mask layer includes a first mask sublayer formed on the upper surface of bit line structures, and a second mask sublayer located on the upper surface of the first mask sublayer and the upper surface of an inter-layer dielectric layer, the first mask sublayer has the upper surface level with the upper surface of an inter-layer dielectric layer, and has a plurality of strip-shaped patterns extending in a first direction and spaced apart from each other, and the second mask sublayer has a plurality of strip-shaped patterns extending in a second direction and spaced apart from each other; and etching the inter-layer dielectric layer by using the first mask layer as a mask to form a contact hole exposing a surface of a substrate.

Abstract: A semiconductor device includes a stacked structure including a first region in which conductive layers and the insulating layers are stacked alternately with each other, and a second region in which sacrificial layers and the insulating layers are stacked alternately with each other, a first slit structure located at a boundary between the first region and the second region and including a first through portion passing through the stacked structure and first protrusions extending from a sidewall of the first through portion, a second slit structure located at the boundary and including a second through portion passing through the stacked structure and second protrusions extending from a sidewall of the second through portion and coupled to the first protrusions, a circuit located under the stacked structure, and a contact plug passing through the second region of the stacked structure and electrically connected to the circuit.

Abstract: Provided is a memory device including a stack structure, a first set of vertical channel structures, a second set of vertical channel structures and a first slit. The stack structure is disposed on a substrate, wherein a top surface of the substrate is parallel to a plane defined by a X direction and a Y direction perpendicular to the X direction. The first set of vertical channel structures and the second set of vertical channel structures are arranged along the Y direction and penetrating through the stack structure along a Z direction vertical to the plane to contact the substrate. The first slit is disposed between the first and second sets of vertical channel structures, and penetrates through the stack structure along the Z direction to expose the substrate, wherein the first slit includes a plurality of first sub-slits discretely disposed along the X direction.

Abstract: A semiconductor die comprises a first set of semiconductor devices disposed at a first location of the semiconductor die and a second set of semiconductor devices disposed at a second location of the semiconductor die different from the first location. Each of the first set of semiconductor devices have a first workfunction to cause each of the first set of semiconductor devices to store memory for a first time period. Moreover, each of the second set of semiconductor devices have a second workfunction that is higher greater than the first workfunction to cause each of the second set of semiconductor devices to store memory for a second time period greater than the first time period.

Abstract: A first conductive pillar is formed. A plurality of second conductive pillars are formed at different sides of the first conductive pillar. A plurality of dielectric pillars are respectively formed between the first conductive pillar and the plurality of second conductive pillars. A channel layer is formed to continuously surround the first conductive pillar, the plurality of second conductive pillars and the plurality of dielectric pillars. A memory material layer is formed to surround the channel layer.

Abstract: A device includes a semiconductor substrate; a first word line over the semiconductor substrate, the first word line providing a first gate electrode for a first transistor; and a second word line over the first word line. The second word line is insulated from the first word line by a first dielectric material, and the second word line providing a second gate electrode for a second transistor over the first transistor. The device further including a source line intersecting the first word line and the second word line; a bit line intersecting the first word line and the second word line; a memory film between the first word line and the source line; and a first semiconductor material between the memory film and the source line.

Abstract: 3D-NOR memory array devices and methods of manufacture are disclosed herein. A method includes forming a multi-layer stack over a substrate by forming alternating layers of an isolation material and a dummy material. An array of dummy nanostructures is formed in a channel region of the multi-layer stack by performing a wire release process. Once the nanostructures have been formed, a single layer of an oxide semiconductor material is deposited over and surrounds the dummy nanostructures. A memory film is then deposited over the oxide semiconductor material and a conductive wrap-around structure is formed over the memory film. Source/bit line structures may be formed by replacing the layers of the dummy material outside of the channel region with a metal fill material. A staircase conductor structure can be formed the source/bit line structures in a region of the multi-layer stack adjacent the memory array.

Abstract: A pocket integration for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a bottom electrode layer over a substrate and forming a seed layer over the bottom electrode layer. A ferroelectric switching layer is formed over the bottom electrode layer and to contact the seed layer. The ferroelectric switching layer is formed to have a first region with a first crystal phase and a second region with a different crystal phase. A top electrode layer is formed over the ferroelectric switching layer. One or more patterning processes are performed on the bottom electrode layer, the seed layer, the ferroelectric switching layer, and the top electrode layer to form a ferroelectric random access memory (FeRAM) device.

Abstract: A gated ferroelectric memory cell includes a dielectric material layer disposed over a substrate, a metallic bottom electrode, a ferroelectric dielectric layer contacting a top surface of the bottom electrode, a pillar semiconductor channel overlying the ferroelectric dielectric layer and capacitively coupled to the metallic bottom electrode through the ferroelectric dielectric layer, a gate dielectric layer including a horizontal gate dielectric portion overlying the ferroelectric dielectric layer and a tubular gate dielectric portion laterally surrounding the pillar semiconductor channel, a gate electrode strip overlying the horizontal gate dielectric portion and laterally surrounding the tubular gate dielectric portion and a metallic top electrode contacting a top surface of the pillar semiconductor channel.