Abstract: The present disclosure relates to a display device. The display device according to an exemplary embodiment of the present disclosure includes a substrate including an active area including a plurality of sub-pixels and a non-active area surrounding the active area; a plurality of transistors disposed in the plurality of sub-pixels, respectively; a plurality of first power supply lines connected to the plurality of sub-pixels; and a plurality of second power supply lines disposed to intersect the plurality of first power supply lines and made of the same material as gate electrodes of the plurality of transistors. Therefore, it is possible to improve the luminance of the display device and suppress the occurrence of mura.

Abstract: A display substrate, a display panel, an electronic device and a display method. The display substrate includes first electrodes in a first display region and second electrodes in a second display region, a first light-emitting portion in the first display region and a second light-emitting portion in the second display region, and the first electrodes being of strip shapes extending along a first direction and being spaced apart from each other along a second direction; third electrodes in the first display region and a fourth electrode in the second display region, the third electrode being of strip shapes extending along the second direction and being spaced apart from each other along the first direction.

Abstract: A display substrate is provided. The display substrate includes a pixel defining layer having a plurality of apertures corresponding to the sub pixels of at least two different colors. Orthographic projections of the plurality of apertures on the base substrate each are divided by the orthographic projections of the plurality of first power supply lines on the base substrate into a first portion and a second portion. For the sub pixels of the at least two different colors, a first area ratio is a ratio between areas of the first portions of the orthographic projections of the apertures on the base substrate, a second area ratio is a ratio between areas of the second portions of the orthographic projections of the apertures on the base substrate, and a ratio between the first area ratio and the second area ratio is in a range from 0.8 to 1.2.

Abstract: According to one embodiment, a display device includes a first area including a pixel and a second area different from the first area, wherein the pixel includes a pixel electrode, an organic material layer including a light-emitting layer, a first common electrode, and a second common electrode having transmittance higher than that of the first insulating layer, the second area is an area not overlapping the light-emitting layer in plan view, the second area is a transparent area, and the second area does not comprise the first common electrode provided therein.

Abstract: A display device includes first to third light emitting units disposed on a substrate, an encapsulation layer disposed on the first to third light emitting units, a sensor electrode disposed on the encapsulation layer, an insulating layer disposed on the sensor electrode, first to third color filters disposed on the touch insulating layer and overlapping the first to third light emitting units in a thickness direction of the substrate, respectively. The sensor electrode overlaps at least one of the first color filter, the second color filter, and the third color filter in the thickness direction of the substrate.

Abstract: A display apparatus includes a first pixel, a second pixel, and a third pixel that emit light of different colors, a first quantum conversion layer arranged corresponding to an emission area of the first pixel and including first quantum dots and first metal nanoparticles, and a second quantum conversion layer arranged corresponding to an emission area of the second pixel and including second quantum dots and second metal nanoparticles, where the plurality of first quantum dots has an average size different from an average size of the second quantum dots, and the first metal nanoparticles have an average size identical to an average size of the plurality of second metal nanoparticles, and outer shapes of the first metal nanoparticles and the second metal nanoparticles have sharper corners than virtual outer spherical shapes.

Abstract: A display device includes first and second light-emitting diodes in respective first and second emission areas, an encapsulation layer thereon, and including at least one inorganic encapsulation layer and at least one organic encapsulation layer, a color conversion-transmission layer on the encapsulation layer, and including a color conversion part to convert light emitted from the first or second light-emitting diodes into a different color, and a light blocking partition wall surrounding the color conversion part, first and second color filters on the color conversion-transmission layer, and respectively corresponding to the first and second emission areas, wherein respective first end portions of the first and second color filters are spaced from each other while overlapping the light blocking partition wall, and are partly covered with a third color material having a color that is different from the first and second color filters.

Abstract: An electronic device includes a display panel that includes a plurality of light emitting elements, and an input sensor disposed on the display panel and that includes a plurality of mesh patterns. The mesh patterns include a plurality of openings formed therein and spaced apart from each other in a first direction and a second direction that crosses the first direction. The mesh patterns include a plurality of conductive patterns spaced apart from each other in a direction that cross the first and second directions, where a center opening of the plurality of openings is disposed therebetween, and a plurality of mesh lines disposed along an edge of the center opening and connected to the conductive patterns. Each of the conductive patterns includes at least one cut-away portion opened toward one of the openings.

Abstract: The present disclosure discloses a display substrate and a display device. The display substrate includes: a base substrate; a plurality of light emitting devices, located on the base substrate; a plurality of photosensitive devices, located between a layer where the plurality of light emitting devices are located and the base substrate; a plurality of color resistors and a black matrix, located on a side of the layer where the plurality of light emitting devices are located facing away from the base substrate; a touch control structure, located between the layer where the plurality of light emitting devices are located and a layer where the black matrix is located; and an ultrathin glass cover plate, a whole face of which being disposed on a side of the layer where the black matrix is located facing away from the base substrate.

Abstract: An organic light-emitting diode device and a manufacturing method thereof are provided. The organic light-emitting diode device includes an array substrate, a light-emitting layer and a thin-film encapsulation layer stacked in order from bottom to top. The thin-film encapsulation layer includes a first inorganic layer, an organic layer and at least one dielectric structure layer in a stack. There is the dielectric structure layer is disposed in the thin-film encapsulation layer.

Abstract: A display apparatus including a substrate including a display area and a peripheral area outside the display area, a first insulating layer over the substrate in the display area and the peripheral area, the first insulating layer including a plurality of first contact holes located in the display area, a plurality of second contact holes located in the peripheral area, and a plurality of dummy contact holes located between the plurality of first contact holes and the plurality of second contact holes, first wirings filling the plurality of first contact holes, second wirings filling the plurality of second contact holes, and a second insulating layer covering the first wirings and the second wirings and filling the plurality of dummy contact holes.

Abstract: An organic light emitting diode (OLED) automatic production equipment is provided. The OLED automatic production equipment includes a vapor deposition device, a printing device, a sputtering device, a flexible packaging device, and a thin film packaging device. The thin film packaging device is in communication with the vapor deposition device, the printing device, the sputtering device, the flexible packaging device, and the like. Processors of the vapor deposition device, the printing device, the sputtering device, and the flexible packaging device are configured to perform two-way communication with a processor of the thin film packaging device.

Abstract: A method of manufacturing a display device includes forming a light emitting structure on a substrate and forming a thin film encapsulation layer on the light emitting structure by chemical vapor deposition equipment. The forming the thin film encapsulation layer includes forming a first inorganic layer and performing a first plasma treatment on a first portion of the first inorganic layer which is opposite to a second portion of the first inorganic layer facing the light emitting structure. A first raw material in the forming the first inorganic layer includes hydrogen. A second raw material in the performing the first plasma treatment exclusively consists of hydrogen.

Abstract: A display module includes a display panel including a plurality of pixels, a carrier panel on a rear surface of the display panel, and an adhesive layer disposed between the display panel and the carrier panel, where the adhesive layer is in contact with the carrier panel. Lateral surfaces of the adhesive layer are recessed from lateral surfaces of the carrier panel.

Abstract: The present invention concerns a method for deposition layers of an electronic device by slot-die deposition. Preferably, the method comprises slot-die deposition of formulation for providing compact inorganic layers, mesoporous inorganic layers, a carbon layer and a layer comprising organic-inorganic perovskite. In a preferred embodiment, the layers of a monolithic perovskite solar cell are entirely deposited by slot-die deposition. The method renders the manufacturing process of such electronic devices more efficient.

Abstract: Provided is a method of purifying a phosphorescent dopant, the method including reacting the phosphorescent dopant with Ag2O.

Abstract: An opto-electronic device includes a nucleating inhibiting coating (NIC) disposed on a first layer surface of the device in a first portion of a lateral aspect thereof; and a conductive coating disposed on a second layer surface of the device in a second portion of the lateral aspect thereof; wherein an initial sticking probability for forming the conductive coating onto a surface of the NIC in the first portion, is substantially less than the initial sticking probability for forming the conductive coating onto the surface in the second portion, such that the surface of the NIC in the first portion is substantially devoid of the conductive coating.

Abstract: An opto-electronic device includes: (1) a substrate including a first region and a second region; and (2) a conductive coating covering the second region of the substrate. The first region of the substrate is exposed from the conductive coating, and an edge the conductive coating adjacent to the first region of the substrate has a contact angle that is greater than about 20 degrees.

Abstract: Provided are an organometallic compound represented by Formula 1, an organic light-emitting device including the same and an electronic apparatus including the organic light-emitting device: M(L1)n1(L2)n2??<Formula 1> wherein M, L1, L2, n1, and n2 in Formula 1 are the same as described in the detailed description.

Abstract: Provided is an organic electroluminescence device including a first electrode, an organic layer on the first electrode, and a second electrode on the organic layer, wherein the organic layer includes a polycyclic compound represented by Formula 1. The organic electroluminescence device including a polycyclic compound represented by Formula 1 thereby exhibits high luminous efficiency.

Abstract: An organometallic compound represented by Formula 1: wherein, in Formula 1, groups and variables are the same as described in the specification.

Abstract: The present invention relates to a compound represented by the formula (1): wherein R1 to R4 and L1 to L4 are those defined in the specification, and Ar is the following formula (A) or (B): wherein R11 to R18 and R20 to R29 are those defined in the specification, and Ar is one defined in the specification.

Abstract: An organic light emitting device including a first electrode; a second electrode provided to face the first electrode; and an organic material layer having one, two or more layers provided between the first electrode and the second electrode, wherein the organic material layer includes a first organic material layer including a compound of Chemical Formula 1 and a second organic material layer including a compound of Chemical Formula 2.

Abstract: A light emitting device of an embodiment includes a first electrode, a second electrode disposed on the first electrode, and an emission layer disposed between the first electrode and the second electrode, wherein the emission layer includes a polycyclic compound represented by Formula 1. Accordingly, the light emitting device of an embodiment may show improved emission efficiency and increased life characteristics.

Abstract: An organic electroluminescence device of one or more embodiments includes a first electrode, a hole transport region disposed on the first electrode, an emission layer disposed on the hole transport region, an electron transport region disposed on the emission layer and a second electrode disposed on the electron transport region, wherein the emission layer includes a polycyclic compound represented by Formula 1, thereby showing high emission efficiency: wherein Y is O or S.

Abstract: A composition for an organic optoelectronic device, an organic optoelectronic device, and a display device, the composition comprising a first compound represented by Chemical Formula I; a second compound represented by Chemical Formula II; and a third compound represented by Chemical Formula III,

Abstract: An organic light-emitting device includes a first electrode; a second electrode facing the first electrode; and an organic layer between the first electrode and the second electrode, the organic layer including an emission layer. The emission layer includes at least one heterocyclic compound of Formula 1. The heterocyclic compound may be a host or a delayed fluorescent dopant. The organic light-emitting device including the heterocyclic compound may have a low driving voltage, high efficiency, high luminance, and a long lifespan.

Abstract: Compounds that are organic radicals that can have a dual function. The compounds can be fluorescent emitters that emit in the near-IR. The compounds can also facilitate reverse intersystem crossing (RISC) to convert triplet excitons in an OLED to singlet excited states to maximize utilization of generated excitons in the OLED and approach 100% internal quantum efficiency.

Abstract: The present application concerns compounds for use in electronic devices, processes for preparing the compounds, and electronic devices comprising the compounds.

Abstract: A light-emitting element having high emission efficiency is provided. A light-emitting element having a low driving voltage is provided. A novel compound which can be used for a transport layer or as a host material or a light-emitting material of a light-emitting element is provided. A novel compound with a benzofuropyrimidine skeleton is provided. Also provided is a light-emitting element which includes the compound with the benzofuropyrimidine skeleton between a pair of electrodes.

Abstract: A thermoelectric conversion material is a polycrystalline material composed of a plurality of crystal grains and has a composition represented by formula (I): Mg3+mSbaBi2?a?cAc. In the formula (I), A is at least one element selected from the group consisting of Se and Te, the value of m is greater than or equal to 0.01 and less than or equal to 0.5, the value of a is greater than or equal to 0 and less than or equal to 1.0, and the value of c is greater than or equal to 0.001 and less than or equal to 0.06. The thermoelectric conversion material has an Mg-rich region.

Abstract: A piezoelectric element comprising a compound represented by Formula 1, a piezoelectric device including the piezoelectric element, a vibration module including the piezoelectric device, and a display apparatus including the piezoelectric device are provided, where (1?x)(LizNa0.5-zK0.5)(Nb1-ySby)O3·xCaZrO3??[Formula 1] where x, y, and z have a range of 0.001?x?0.2, a range of 0?y?0.5, and a range of 0?z?0.2, respectively.

Abstract: A power generating element according to an aspect of the present disclosure includes at least one magnetostrictive portion containing a magnetostrictive material, at least one magnetic portion containing a magnetic material, part of a surface of the magnetic portion being fixed to the magnetostrictive portion, a coil housing part of one of the magnetostrictive portion and the magnetic portion, and a magnet portion including a magnet and fixed to the magnetostrictive portion, wherein the magnetic portion is magnetically connected in parallel to the magnetostrictive portion and is fixed to the magnetostrictive portion so as to have an interval between the magnetostrictive portion and the magnetic portion, the interval being magnetically connected in series to the magnetic portion.

Abstract: A method for fabricating a magnetic random access memory (MRAM) device includes the steps of first forming a first magnetic tunneling junction (MTJ) on a substrate, forming a first top electrode on the first MTJ, and then forming a passivation layer around the first MTJ. Preferably, the passivation layer includes a V-shape and a valley point of the V-shape is higher than a top surface of the first top electrode.

Abstract: Apparatus, and their methods of manufacture, including an integrated circuit device having metallization layers for interconnecting underlying electronic devices. Contacts contact conductors of an uppermost one of the metallization layers. A planarized first dielectric layer covers the contacts and the uppermost one of the metallization layers. An anisotropic magnetoresistive (AMR) stack is on the first dielectric layer between vertically aligned portions of an etch stop layer formed on the first dielectric layer and a second dielectric layer formed on the etch stop layer. Vias extend through the first dielectric layer to electrically connect the AMR stack and the contacts. A chemical-mechanical planarization (CMP) stop layer is on the AMR stack. A third dielectric layer is on the CMP stop layer. A passivation layer contacts the second dielectric layer portions, the third dielectric layer, and each opposing end of the AMR stack and the CMP stop layer.

Abstract: A method for manufacturing a magnetic memory array provides back end of line annealing for associated processing circuitry without causing thermal damage to magnetic memory elements of the magnetic memory array. An array of magnetic memory element pillars is formed on a wafer, and the magnetic memory elements are surrounded by a dielectric isolation material. After the pillars have been formed and surrounded by the dielectric isolation material an annealing process is performed to both anneal the memory element pillars to form a desired grain structure in the memory element pillars and also to perform back end of line thermal processing for circuitry associated with the memory element array.

Abstract: A device includes a resistance switching layer, a capping layer, a top electrode, a first spacer, and a second spacer. The resistance switching layer is over a substrate. The capping layer is over the resistance switching layer. The top electrode is over the capping layer. The first spacer lines the resistance switching layer and the capping layer. The second spacer lines the first spacer. The capping layer is in contact with the top electrode, the first spacer, and the second spacer.

Abstract: According to one embodiment, a magnetic memory device includes a first magnetoresistance effect element provided above a substrate, a first switching element member, and a first conductor. Each of the first switching element member and the first conductor is provided above the first magnetoresistance effect element. The first switching element member includes a first portion in contact with a lower surface of the first conductor directly above the first magnetoresistance effect element. An area of a lower surface of the first switching element member is smaller than a cross-sectional area of the first switching element member along the lower surface of the first conductor.

Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a dielectric layer, a plurality of MTJ stacked elements and at least one dummy MTJ stacked element located in the dielectric layer, a first nitride layer covering at least the sidewalls of the MTJ stacked elements and the dummy MTJ stacked elements, a second nitride layer covering the top surfaces of the dummy MTJ stacked elements, the thickness of the second nitride layer is greater than the thickness of the first nitride layer, and a plurality of contact structures located in the dielectric layer and electrically connected with each MTJ stacked element.

Abstract: A magnetic tunnel junction (MTJ) element is provided. The MTJ element includes a reference layer, a tunnel barrier layer disposed over the reference layer, a free layer disposed over the tunnel barrier layer, and a diffusion barrier layer disposed over the free layer. The MTJ element in accordance with the present disclosure exhibits a low resistance desired for a low-power write operation, and a high TMR coefficient desired for a low bit-error-rate (BER) read operation.

Abstract: A magnetic memory according to an embodiment includes: a first wiring and a second wiring; a nonmagnetic conductor extending in a first direction; a first magnetic member including a first portion electrically connected to the first wiring and a second portion electrically connected to the second wiring, the first magnetic member extending in the first direction from the first portion to the second portion to surround the nonmagnetic conductor; an insulation portion disposed between the nonmagnetic conductor and the first magnetic member; and a controller electrically connected to the nonmagnetic conductor, the first wiring, and the second wiring.

Abstract: A MRAM device includes a substrate, a first bottom electrode, a first MTJ stack, a first spacer, a topography-smoothing layer and a second ILD layer. The substrate includes a first ILD layer having a metal line. The first MTJ stack is over the first bottom electrode. The first spacer surrounds sidewalls of the first MTJ stack. The topography-smoothing layer extends over a top surface of the first ILD layer, along sidewalls of the first bottom electrode the first spacer. The topography-smoothing layer has a top portion over the first MTJ stack and a first side portion laterally surrounding the first spacer. The first side portion has a maximal lateral thickness greater than a maximal vertical thickness of the top portion. The second ILD layer is over the topography-smoothing layer and has a material different from a material of the topography-smoothing layer.

Abstract: A method for manufacturing a magnetic random access memory array incudes forming a source region within a surface of a substrate, forming an array of three-dimensional (3D) structures over the substrate, each 3D structure being separated from an adjacent 3D structure by a cavity region, depositing a channel material on a surface of at least one sidewall of each 3D structure, depositing a gate dielectric material over the channel material on the surface of the at least one sidewall of each 3D structure, forming a first isolation region in each cavity region between adjacent 3D structures over the substrate, and forming a first gate region over the first isolation region in each cavity region.

Abstract: A method includes forming a memory stack over a substrate. A dielectric layer is deposited to cover the memory stack. An opening is formed in the dielectric layer. The opening does not expose the memory stack. A spin-orbit-torque (SOT) layer is formed in the opening. A free layer is formed over the dielectric layer to interconnect the memory stack and the SOT layer.

Abstract: Superconducting metamaterials composed of lumped-element inductors and capacitors are used to implement microwave photonics with novel dispersion relations and dense mode spectra that can be coupled to qubits. Metamaterial lattices may have qubits coupled to different unit cells in the metamaterial such that each qubit will couple strongly to modes with an antinode at the qubit location. Through simultaneous driving of combinations of modes, large amplitudes are produced at only one or a few unit cells, resulting in large ac Stark shifts of qubits located there, and providing a frequency-addressable qubit array without requiring flux-tunability and with reduced control wiring.

Abstract: An integrated circuit is provided that comprises a first substrate having a plurality of conductive contact pads spaced apart from one another on a surface of the first substrate, a dielectric layer overlying the first substrate and the plurality of conductive contact pads, and a second substrate overlying the dielectric layer. A plurality of superconducting contacts extend through the second substrate and the dielectric layer to the first substrate, wherein each superconducting contact of the plurality of superconducting contacts is aligned with and in contact with a respective conductive contact pad of the plurality of conductive contact pads.

Abstract: A superconducting material includes YBa2Cu3O7-? and a nano-structured, preferably nanowires, WO3 dopant in a range of from 0.01 to 3.0 wt. %, preferably 0.075 to 0.2 wt. %, based on total material weight. Methods of making the superconductor may preferably avoid solvents and pursue solid-state synthesis employing Y, Ba, and/or Cu oxides and/or carbonates.

Abstract: A system that includes: an array of qubits, each qubit of the array of qubits comprising a first electrode corresponding to a first node and a second electrode corresponding to a second node, wherein, for a first qubit in the array of qubits, the first qubit is positioned relative to a second qubit in the array of qubits such that a charge present on the first qubit induces a same charge on each of the first node of the second qubit and the second node of the second qubit, such that coupling between the first qubit and the second qubit is reduced, and wherein none of the nodes share a common ground is disclosed.

Abstract: The disclosure provides a memory device, a method for configuring a first memory cell in an N-bit memory unit of a memory array, and a memory array. The memory device includes a memory array including an N-bit memory unit, wherein N is a positive integer. The N-bit memory unit includes a first memory cell, used to characterize at least two first bits of a plurality of least significant bits of the N-bit memory unit.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device. The RRAM device includes a first electrode over a substrate and a second electrode over the substrate. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure includes a first metal and a second metal. The first metal has a peak concentration at a first distance from the first electrode and the second metal has a peak concentration at a second distance from the first electrode. The first distance is different than the second distance.