Processes Of Growth With A Subsequent Step Acting On The Crystal To Adjust The Impurity Amount (e.g., Diffusing, Doping, Gettering, Implanting) Patents (Class 117/2)
  • Patent number: 11114252
    Abstract: Disclosures of the present invention mainly describe a method for manufacturing perovskite solar cell module. At first, a laser scribing is adopted for forming multi transparent conductive films (TCFs) on a transparent substrate. Subsequently, by using a first mask, multi HTLs, active layers, and ETLs are sequentially formed on the TCFs. Consequently, by the use of a second make, each of the ETLs is formed with an electrically connecting layer thereon, such that a perovskite solar cell module comprising a plurality of solar cell units is hence completed on the transparent substrate. It is worth explaining that, during the whole manufacturing process, each of the solar cell units is prevented from receiving bad influences that are provided by laser scribing or manufacture environment, such that each of the solar cell units is able to exhibit outstanding photoelectric conversion efficiency.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: September 7, 2021
    Assignee: CPC Corporation, Taiwan
    Inventors: Kuan-Chieh Huang, Li-Chung Lai, Chung-Kwang Lee
  • Patent number: 10862447
    Abstract: A method for processing a lithium tantalate crystal substrate includes providing a lithium tantalate crystal substrate and a metallic sheet, roughening at least one of the lithium tantalate crystal substrate and the metallic sheet, bringing the lithium tantalate crystal substrate and the metallic sheet into contact with each other after the at least one thereof is roughened, and subjecting the lithium tantalate crystal substrate to a reduction treatment. The reduction treatment is conducted at a temperature not higher than a Curie temperature of the lithium tantalate crystal substrate.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: December 8, 2020
    Assignee: Fujian Jing'An Optoelectronics Co., Ltd.
    Inventor: Mingxin Chen
  • Patent number: 10861945
    Abstract: A semiconductor element includes a high-resistivity substrate that includes a ?-Ga2O3-based single crystal including an acceptor impurity, a buffer layer on the high-resistivity substrate, the buffer layer including a ?-Ga2O3-based single crystal, and a channel layer on the buffer layer, the channel layer including a ?-Ga2O3-based single crystal including a donor impurity. A crystalline laminate structure includes a high-resistivity substrate that includes a ?-Ga2O3-based single crystal including an acceptor impurity, a buffer layer on the high-resistivity substrate, the buffer layer including a ?-Ga2O3-based single crystal, and a donor impurity-containing layer on the buffer layer, the donor impurity-containing layer including a ?-Ga2O3-based single crystal including a donor impurity.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: December 8, 2020
    Assignees: TAMURA CORPORATION, NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY, NATIONAL UNIVERSITY CORPORATION TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY
    Inventors: Kohei Sasaki, Ken Goto, Masataka Higashiwaki, Man Hoi Wong, Akinori Koukitu, Yoshinao Kumagai, Hisashi Murakami
  • Patent number: 10815586
    Abstract: A GaAs-based compound semiconductor crystal includes a straight body portion having a cylindrical shape, wherein the straight body portion has a diameter of more than or equal to 110 mm and has a length of more than or equal to 100 mm and less than or equal to 400 mm, and the straight body portion has a first end surface and a second end surface having a higher specific resistance than a specific resistance of the first end surface, and a ratio R20/R10 of a specific resistance R20 at the second end surface side to a specific resistance R10 at the first end surface side is more than or equal to 1 and less than or equal to 2.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: October 27, 2020
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yukio Ishikawa, Hidetoshi Takayama, Hirokazu Oota, Shuuichi Kaneko
  • Patent number: 10734274
    Abstract: A process separates a main body of a semiconductor substrate from a functional layer. The method includes the steps of implanting ions into a semiconductor substrate through a top surface of the semiconductor substrate to form an ion damage layer underneath the top surface of the semiconductor substrate. After the ions are implanted into the semiconductor substrate, a functional layer is formed on the top surface of the semiconductor substrate. The main body of the semiconductor substrate is then separated from the functional layer. The method also includes forming the functional layer on the semiconductor substrate after ion implanting and then separating the functional layer from the main body of the substrate at the ion damage layer. This method avoids bonding in SOI and can thus reduce process steps and cost.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: August 4, 2020
    Inventor: Bing Hu
  • Patent number: 10724979
    Abstract: Gas sensors are described herein that are useful for selectively detecting a second gas (e.g. isoprene) in the presence of a first gas (e.g. acetone). The gas sensors include a sensor element which includes a semiconductor sensing material and a porous material. The sensor element is configured so that the porous material absorbs more of the first gas than the second gas. Thus, when the gas being analyzed, such as a mammalian (including human) breath, a greater proportion of the second gas comes into contact with the semiconductor sensing material.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: July 28, 2020
    Assignee: Nitto Denko Corporation
    Inventor: Qianxi Lai
  • Patent number: 10692736
    Abstract: A method for producing a solar cell, which produces a single-crystal silicon solar cell by using a single-crystal silicon substrate, including: a high-temperature heat treatment process in which the single-crystal silicon substrate is subjected to heat treatment at 800° C. or higher and 1200° C. or lower, wherein the high-temperature heat treatment process includes a conveying step of loading the single-crystal silicon substrate into a heat treatment apparatus, a heating step of heating the single-crystal silicon substrate, a temperature keeping step of keeping the single-crystal silicon substrate at a predetermined temperature of 800° C. or higher and 1200° C. or lower, and a cooling step of cooling the single-crystal silicon substrate, and, in the high-temperature heat treatment process, the length of time during which the temperature of the single-crystal silicon substrate is 400° C. or higher and 650° C. or lower is set at 5 minutes or less throughout the conveying step and the heating step.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: June 23, 2020
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Hiroshi Hashigami, Takenori Watabe, Hiroyuki Ohtsuka
  • Patent number: 10633764
    Abstract: In a gallium nitride crystal, a nanovoid density in the crystal is less than 1×105 [cm?2]. A crystal growth apparatus is an apparatus for manufacturing a gallium nitride crystal, wherein a member having a B concentration of less than 1 ppm at least at a surface part is used as a member used at a part where a temperature is 500° C. or higher (high-temperature member) among members exposed to a crystal growth space. When such a crystal growth apparatus is used, a gallium nitride crystal wherein a nanovoid density in the crystal is less than 1×105 [cm?2] is obtained.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: April 28, 2020
    Assignee: KABUSHIKI KAISHA TOYOTA JIDOSHA CHUO KENKYUSHO
    Inventors: Taishi Kimura, Daisuke Nakamura
  • Patent number: 10629321
    Abstract: A p-type transparent conductive oxide (TCO) mixed metal oxide material layer formed upon a substrate has a formula M1xM2yOz generally, CaxCoyOz more specifically, and Ca3Co4O9 most specifically. Embodiments provide that the p-type TCO mixed metal oxide material may be formed absent an epitaxial crystalline relationship with respect to the substrate while using a sol-gel synthesis method that uses a chelating polymer material and not a block copolymer material.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: April 21, 2020
    Assignee: CORNELL UNIVERSITY
    Inventors: Mahmut Aksit, Richard D. Robinson
  • Patent number: 10629814
    Abstract: A coaxial nanocomposite including a core, which includes fibers of a first organic polymer, and a shell, which includes fibers of a second organic polymer, the first polymer and the second polymer forming a heterojunction.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: April 21, 2020
    Assignee: University of South Florida
    Inventors: William Serrano-Garcia, Sylvia Thomas
  • Patent number: 10585054
    Abstract: Provided in one embodiment is a method of identifying a stable phase of an ordering binary alloy system comprising a solute element and a solvent element, the method comprising: determining at least three thermodynamic parameters associated with grain boundary segregation, phase separation, and intermetallic compound formation of the ordering binary alloy system; and identifying the stable phase of the ordering binary alloy system based on the first thermodynamic parameter, the second thermodynamic parameter and the third thermodynamic parameter by comparing the first thermodynamic parameter, the second thermodynamic parameter and the third thermodynamic parameter with a predetermined set of respective thermodynamic parameters to identify the stable phase; wherein the stable phase is one of a stable nanocrystalline phase, a metastable nanocrystalline phase, and a non-nanocrystalline phase.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: March 10, 2020
    Assignee: Massachusetts Institute of Technology
    Inventors: Heather A. Murdoch, Christopher A. Schuh
  • Patent number: 10473692
    Abstract: A method of calibrating a topography metrology instrument using a calibration reference, which includes a substrate and a plurality of bi-layer stacks. Each bi-layer stack includes a plurality of bi-layer steps. At least one bi-layer step of the plurality of bi-layer steps includes two materials. The at least one bi-layer step of the plurality of bi-layer steps includes an etch stop layer and a bulk layer. The calibration reference includes a calibration reference step profile includes a plurality of predetermined bi-layer stack heights. The calibration reference step profile and the predetermined bi-layer stack heights are measured using a topography metrology instrument. The topography metrology instrument is calibrated based on the measured calibration reference step profile and the measured bi-layer stack heights.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: November 12, 2019
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Marc Christophersen, Bernard F. Phlips, Andrew J. Boudreau, Michael K. Yetzbacher
  • Patent number: 10450671
    Abstract: Provided is a SiC single crystal that has a large growth thickness and contains no inclusions. A SiC single crystal grown by a solution process, wherein the total length M of the outer peripheral section formed by the {1-100} faces on the {0001} growth surface of the SiC single crystal, and the length P of the outer periphery of the growth surface of the SiC single crystal, satisfy the relationship M/P?0.70, and the length in the growth direction of the SiC single crystal is 2 mm or greater.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: October 22, 2019
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, NIPPON STEEL & SUMITOMO METAL CORPORATION
    Inventors: Hironori Daikoku, Motohisa Kado, Kazuhito Kamei, Kazuhiko Kusunoki
  • Patent number: 10453881
    Abstract: An infrared image sensor component includes a semiconductor substrate, an active pixel region disposed on the semiconductor substrate for receiving an infrared ray, and a transistor coupled to the active pixel region. The transistor includes a gate and a source/drain stressor disposed adjacent to the gate. The active pixel region includes a III-V compound material.
    Type: Grant
    Filed: January 13, 2018
    Date of Patent: October 22, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ying Wu, Li-Hsin Chu, Chung-Chuan Tseng, Chia-Wei Liu
  • Patent number: 10431280
    Abstract: A ferroelectric opening switch is enabled by controlled polarization switching via nucleation in a ferroelectric material, such as BaTiO3, Pb(Zr,Ti)O3, LiNbO3, LiTaO3, or variants thereof. For example, nucleation sites can be provided by mechanical seeding, grain boundaries, or optical illumination. The invention can be used as an opening switch in large scale pulsed-power systems. However, the switch can also be used in compact pulsed-power systems (e.g., as drivers for high power microwave systems), as passive fault limiters for high voltage dc (HVDC) systems, and/or in other high power applications.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: October 1, 2019
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Geoffrey L. Brennecka, Steven F. Glover, Gary Pena, Fred J. Zutavern
  • Patent number: 10371657
    Abstract: A method for determining the original position of a wafer in an ingot made from semiconductor material comprises the following steps: measuring the interstitial oxygen concentration in an area of the wafer; measuring the concentration of thermal donors formed in said area of the wafer during a previous solidification of the ingot; determining the effective time of a thermal donor formation anneal undergone by the wafer when solidification of the ingot took place, from the thermal donor concentration and the interstitial oxygen concentration; and determining the original position of the wafer in the ingot from the effective time.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: August 6, 2019
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jordi Veirman, Sébastien Dubois
  • Patent number: 10355119
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include forming a trench and exposing a portion of a first film at a bottom portion of the trench by removing a portion of a second film by performing dry etching using a gas including a first element. The second film is provided on the first film. The first film includes Alx1Ga1-x1N (0?x1<1). The second film includes Alx2Ga1-x2N (0<x2<1 and x1<x2). The method can include performing heat treatment while causing the portion being exposed of the first film to contact an atmosphere including NH3, forming an insulating film on the portion of the first film after the heat treatment, and forming an electrode on the insulating film.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: July 16, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenjiro Uesugi, Aya Shindome, Daimotsu Kato, Masahiko Kuraguchi, Shinya Nunoue
  • Patent number: 10253431
    Abstract: A silicon carbide single crystal includes a spiral dislocation. The spiral dislocation includes a L dislocation having a burgers vector defined as b, which satisfies an equation of b><0001>+1/3<11-20>. The L dislocation has a density equal to or lower than 300 dislocations/cm2, preferably, 100 dislocations/cm2, since the L dislocation has large distortion and causes generation of leakage current. Thus, the silicon carbide single crystal with high quality is suitable for a device production which can suppress the leakage current.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: April 9, 2019
    Assignee: DENSO CORPORATION
    Inventors: Hiroyuki Kondo, Shoichi Onda, Yasuo Kitou, Hiroki Watanabe
  • Patent number: 10236338
    Abstract: A SiC single crystal seed of the present invention has a main surface with an offset angle of at least 2° but not more than 20° relative to the {0001} plane, and at least one sub-growth surface, wherein the sub-growth surface includes an initial facet formation surface that is on the offset upstream side of the main surface and has an inclination angle ? relative to the {0001} plane with an absolute value of less than 2° in any direction, and the initial facet formation surface has a screw dislocation starting point.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: March 19, 2019
    Assignee: SHOWA DENKO K.K.
    Inventors: Yuuki Furuya, Tomohiro Shonai, Yasushi Urakami, Itaru Gunjishima
  • Patent number: 10199216
    Abstract: In an embodiment, a method includes treating an edge region of a wafer including a substrate having an upper surface and one or more epitaxial Group III nitride layers arranged on the upper surface of the substrate, so as to remove material including at least one Group III element from the edge region.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: February 5, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Clemens Ostermaier, Gerhard Prechtl, Oliver Haeberlen
  • Patent number: 10143991
    Abstract: A process for preparing crystalline particles of an active principal in the presence of ultrasonic irradiation that comprises contacting a solution of a solute in a solvent in a first flowing stream with an anti-solvent in a second flowing stream causing the mixing thereof, wherein the flow rate ratio of the anti-solvent: solvent is higher than 20:1, and collecting crystals that are generated.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: December 4, 2018
    Assignee: Circassia Limited
    Inventors: James Robinson, Graham Ruecroft
  • Patent number: 10068973
    Abstract: Fabrication of doped AlN crystals and/or AlGaN epitaxial layers with high conductivity and mobility is accomplished by, for example, forming mixed crystals including a plurality of impurity species and electrically activating at least a portion of the crystal.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: September 4, 2018
    Assignee: CRYSTAL IS, INC.
    Inventors: Glen A. Slack, Leo J. Schowalter
  • Patent number: 10032856
    Abstract: A capacitive device includes a first electrode comprising a nanosheet stack, and a second electrode comprising a nanosheet stack, the second electrode arranged substantially parallel to the first electrode. A first conductive contact is arranged on a basal end of the first electrode, and a second conductive contact arranged on a basal end of the second electrode.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: July 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Zhenxing Bi, Kangguo Cheng, Zheng Xu
  • Patent number: 10026816
    Abstract: A semiconductor wafer includes first and second main surfaces opposite to each other along a vertical direction, and a side surface encircling the semiconductor wafer. A lateral distance perpendicular to the vertical direction between the side surface and a center of the semiconductor wafer includes first and second parts. The first part extends from the side surface to the second part and the second part extends from the first part to the center. An average concentration of at least one of nitrogen and oxygen in the first part is greater than 5×1014 cm?3 and exceeds an average concentration of the at least one of nitrogen and oxygen in the second part by more than 20% of the average concentration of the at least one of nitrogen and oxygen in the second part.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: July 17, 2018
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Helmut Oefner
  • Patent number: 10022721
    Abstract: Methods and systems for manipulating drops in microfluidic channels are provided.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: July 17, 2018
    Assignee: Bio-Rad Laboratories, Inc.
    Inventors: Sepehr Kiani, Joshua Blouwolff, Adnan Esmail, Jason Hung, Tony Hung, Adam R. Abate, Scott Powers, Pascaline Mary
  • Patent number: 10014400
    Abstract: A semiconductor device includes: a semiconductor substrate having a first side, a second side opposite the first side, and a thickness; at least one semiconductor component integrated in the semiconductor substrate; a first metallization at the first side of the semiconductor substrate; and a second metallization at the second side of the semiconductor substrate. The semiconductor substrate has an oxygen concentration along a thickness line of the semiconductor substrate which has a global maximum at a position of 20% to 80% of the thickness relative to the first side. The global maximum is at least 2-times larger than the oxygen concentrations at each of the first side and the second side of the semiconductor substrate.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: July 3, 2018
    Assignee: Infineon Technologies AG
    Inventors: Helmut Oefner, Nico Caspary, Mohammad Momeni, Reinhard Ploss, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
  • Patent number: 9945049
    Abstract: The present invention relates to a process for the preparation of hulk or thin-film single-crystals of cubic sesquioxides (space group No. 206, Ia-3) of scandium, yttrium or rare earth metals doped or not doped with lanthanide ions having a valency of +III by a high-temperature flux growth technique and to the applications of the nondoped single-crystals obtained according to this process, in particular in the optical field.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: April 17, 2018
    Assignee: CENTRE NATIONAL DE LA RECHERCHE SCINTIFIQI
    Inventors: Philippe Veber, Matias Velazquez, Oudomsack Viraphong, Gabriel Buse
  • Patent number: 9890474
    Abstract: An object of the present invention is to provide a crystal of a nitride of a Group-13 metal on the Periodic Table which has good crystallinity and has no crystal strain, and to provide a production method for the crystal. The crystal of a nitride of a Group-13 metal on the Periodic Table of the present invention, comprises oxygen atom and hydrogen atom in the crystal and has a ratio of a hydrogen concentration to an oxygen concentration therein of from 0.5 to 4.5.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: February 13, 2018
    Assignee: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Yutaka Mikawa, Hideo Namita, Hirotaka Ikeda, Kazunori Kamada, Hideo Fujisawa, Atsuhiko Kojima
  • Patent number: 9887087
    Abstract: A method of manufacturing p-n junction in semiconductor material such that small dimensions of such junctions are maintained, and associated lattice dislocations of such junctions may be preferentially maintained, and devices with such patterned semiconductor material, is disclosed. Typically, a neutron moderator is used to slow fast neutrons to thermal energies. A mask made from thermal neutron absorbing material, such as cadmium, is placed in close proximity to such neutron moderator. Thermal neutron focusing optics, such as compound refractive lenses, are used to collect and focus thermal neutrons emitted from the mask such that the pattern or portion of the pattern is transferred to the silicon body, with neutrons transmitted from the window areas in the mask and through the neutron optic so as to form the donor dopant concentration for the n-type regions by transmutation of silicon atoms into phosphorus.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: February 6, 2018
    Inventor: Michael Keith Fuller
  • Patent number: 9869031
    Abstract: This disclosure enables high-productivity fabrication of semiconductor-based separation layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers), optical reflectors (made of multi-layer/multi-porosity porous semiconductors such as porous silicon), formation of porous semiconductor (such as porous silicon) for anti-reflection coatings, passivation layers, and multi-junction, multi-band-gap solar cells (for instance, by forming a variable band gap porous silicon emitter on a crystalline silicon thin film or wafer-based solar cell). Other applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation).
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: January 16, 2018
    Assignee: OB Realty, LLC
    Inventors: George D. Kamian, Somnath Nag, Subramanian Tamilmani, Mehrdad M. Moslehi, Karl-Josef Kramer, Takao Yonehara
  • Patent number: 9833780
    Abstract: Microfluidic devices having superhydrophilic bi-porous interfaces are provided, along with their methods of formation. The device can include a substrate defining a microchannel formed between a pair of side walls and a bottom surface and a plurality of nanowires extending from each of the side walls and the bottom surface. For example, the nanowires can be silicon nanowires (e.g., pure silicon, silicon oxide, silicon carbide, etc., or mixtures thereof).
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: December 5, 2017
    Assignee: UNIVERSITY OF SOUTH CAROLINA
    Inventors: Chen Li, Fanhao Yang, Xianming Dai, Yan Tong
  • Patent number: 9822465
    Abstract: In one instance, the invention provides a group III nitride crystal having a first side exposing nitrogen polar c-plane of single crystalline or highly oriented polycrystalline group III nitride and a second side exposing group III polar surface, polycrystalline phase, or amorphous phase of group III nitride. Such structure is useful as a seed crystal for ammonothermal growth of bulk group III nitride crystals. The invention also discloses the method of fabricating such crystal. The invention also discloses the method of fabricating a bulk crystal of group III nitride by ammonothermal method using such crystal.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: November 21, 2017
    Assignee: SixPoint Materials, Inc.
    Inventor: Tadao Hashimoto
  • Patent number: 9790616
    Abstract: In one instance, the invention provides a group III nitride crystal having a first side exposing nitrogen polar c-plane of single crystalline or highly oriented polycrystalline group III nitride and a second side exposing group III polar surface, polycrystalline phase, or amorphous phase of group III nitride. Such structure is useful as a seed crystal for ammonothermal growth of bulk group III nitride crystals. The invention also discloses the method of fabricating such crystal. The invention also discloses the method of fabricating a bulk crystal of group III nitride by ammonothermal method using such crystal.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: October 17, 2017
    Assignee: SixPoint Materials, Inc.
    Inventor: Tadao Hashimoto
  • Patent number: 9789455
    Abstract: A apparatus comprising: a vessel component comprising a flow-through interior chamber having an interior sidewall and an exterior sidewall; at least two inlets for introducing chemical components into the flow-through interior chamber; at least one outlet for removing product from the flow-through interior chamber; and an off center rotation component which is operatively connected to the vessel component. During operation of the apparatus, the off center rotation component generates vortical movement of at least two chemical components through the flow-through interior chamber of the vessel, and converts at least a portion of the at least two chemical components to at least one reaction product or product mixture. A method of using the apparatus to produce reaction products or product mixtures. The apparatus and method are useful for producing specialty chemicals such as fragrance and flavor compounds, insect pheromones, petrochemicals, pharmaceutical compounds, agrichemical compounds, and the like.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: October 17, 2017
    Assignee: Bedoukian Research, Inc.
    Inventor: Matthew Bedoukian
  • Patent number: 9793355
    Abstract: An epitaxial wafer comprises an epitaxial layer disposed on a substrate. The epitaxial layer comprises first to third semiconductor layers. The third semiconductor layer has a thickness that is thicker than that of the first semiconductor layer. A second doping density of the second semiconductor layer is between a first doping density of the first semiconductor layer and a third doping density of the third semiconductor layer.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: October 17, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Seok Min Kang, Ji Hye Kim, Min Young Hwang
  • Patent number: 9755138
    Abstract: A method for producing an electronic component includes providing a piezoelectric main body, which is provided with electrodes. A first electric polarization field having a first polarity direction is applied to the piezoelectric main body between the two electrodes and then a second electric polarization field is applied in a second polarity direction, opposite to the first polarity direction, to the piezoelectric main body between the electrodes. The absolute value of the second electric polarization field differs from that of the first electric polarization field.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: September 5, 2017
    Assignee: EPCOS AG
    Inventor: Alexander Glazunov
  • Patent number: 9728395
    Abstract: A method for manufacturing a substrate wafer 100 includes providing a device wafer (110) having a first side (111) and a second side (112); subjecting the device wafer (110) to a first high temperature process for reducing the oxygen content of the device wafer (110) at least in a region (112a) at the second side (112); bonding the second side (112) of the device wafer (110) to a first side (121) of a carrier wafer (120) to form a substrate wafer (100); processing the first side (101) of the substrate wafer (100) to reduce the thickness of the device wafer (110); subjecting the substrate wafer (100) to a second high temperature process for reducing the oxygen content at least of the device wafer (110); and at least partially integrating at least one semiconductor component (140) into the device wafer (110) after the second high temperature process.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: August 8, 2017
    Assignee: Infineon Technologies AG
    Inventors: Helmut Oefner, Nico Caspary, Mohammad Momeni, Reinhard Ploss, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
  • Patent number: 9716004
    Abstract: A crystal laminate structure, in which crystals can be epitaxially grown on a ?-Ga2O3-based substrate with high efficiency to produce a high-quality ?-Ga2O3-based crystal film on the substrate; and a method for producing the crystal laminate structure are provided. The crystal laminate structure includes: a ?-Ga2O3-based substrate, of which the major face is a face that is rotated by 50 to 90° inclusive with respect to face; and a ?-Ga2O3-based crystal film which is formed by the epitaxial crystal growth on the major face of the ?-Ga2O3-based substrate.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: July 25, 2017
    Assignee: TAMURA CORPORATION
    Inventor: Kohei Sasaki
  • Patent number: 9709832
    Abstract: The present invention relates to an Electro-Optical (E-O) crystal elements, their applications and the processes for the preparation thereof. More specifically, the present invention relates to the E-O crystal elements (which can be made from doped or un-doped PMN-PT, PIN-PMN-PT or PZN-PT ferroelectric crystals) showing super-high linear E-O coefficient ?c, e.g., transverse effective linear E-O coefficient ?Tc more than 1100 pm/V and longitudinal effective linear E-O coefficient ?lc up to 527 pm/V, which results in a very low half-wavelength voltage Vl? below 200V and VT? below about 87V in a wide number of modulation, communication, laser, and industrial uses.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: July 18, 2017
    Assignee: PENGDI HAN
    Inventor: Pengdi Han
  • Patent number: 9705470
    Abstract: Degenerately doped semiconductor materials are deployed within resonant structures to control the first and higher order temperature coefficients of frequency, thereby enabling temperature dependence to be engineered without need for cumulative material layers which tend to drive up cost and compromise resonator performance.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: July 11, 2017
    Assignee: SiTime Corporation
    Inventors: Joseph C. Doll, Paul M. Hagelin, Ginel C. Hill, Nicholas Miller, Charles I. Grosjean
  • Patent number: 9685536
    Abstract: Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The structures are formed by selectively growing an initial epitaxial layer of mono crystalline silicon on the surface of a semi conductive substrate, and forming a thin film of insulative material over the epitaxial layer. A second epitaxial layer is selectively, grown on the exposed surface of the initial epitaxially grown crystal layer, and a thin insulative film is deposited over the second epitaxial layer. Additional epitaxial layers are added as desired to provide a vertical structure of a desired height comprising multiple layers of single silicon crystals, each epitaxial layer have insulated sidewalls, with the uppermost epitaxial layer also with an insulated top surface.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: June 20, 2017
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Er-Xuan Ping, Jeffrey A. McKee
  • Patent number: 9673380
    Abstract: The application is directed to piezoelectric single crystals having shear piezoelectric coefficients with enhanced temperature and/or electric field stability. These piezoelectric single crystal may be used, among other things, for vibration sensors as well as low frequency, compact sonar transducers with improved and/or enhanced performance.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: June 6, 2017
    Inventors: Wesley S. Hackenberger, Jun Luo, Shujun Zhang, Fei Li, Thomas R. Shrout, Kevin A. Snook, Raffi Sahul
  • Patent number: 9617602
    Abstract: Described herein are modified androgen receptor polypeptides that are resistant to inhibition by an androgen receptor inhibitor. Described herein are compositions, combinations, and kits containing the modified androgen receptor polypeptides and methods of using the modified androgen receptor polypeptides. Also described herein are methods of using the modified androgen receptor polypeptides as screening agents for the identification and design of third-generation androgen receptor modulators. Also described herein are third-generation androgen receptor modulators that inhibit the activity of the modified androgen receptor polypeptides. Also described are pharmaceutical compositions and medicaments that include the compounds described herein, as well as methods of using such androgen receptor modulators, alone and in combination with other compounds, for treating diseases or conditions, including cancers, such as castration resistant prostate cancers, that are mediated or dependent upon androgen receptors.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: April 11, 2017
    Assignee: ARAGON PHARMACEUTICALS, INC.
    Inventors: James David Joseph, Jeffrey H Hager, John Lee Sensintaffar, Nhin Lu, Jing Qian, Nicholas D Smith
  • Patent number: 9605358
    Abstract: A silicon carbide substrate, a silicon carbide ingot, and methods for manufacturing the silicon carbide substrate and the silicon carbide ingot capable of improving a yield of a semiconductor device having silicon carbide as constituent material are provided. In the silicon carbide substrate, patterns formed by crossing straight lines extending along the <11-20> direction and being observable by means of an X-ray topography are present at a number density of less than or equal to 0.1 patterns/cm2 on one main surface. As described above, in the silicon carbide substrate, the number density of the crossing patterns present on the main surface is reduced to less than or equal to 0.1 patterns/cm2. Therefore, when the semiconductor device is manufactured with use of a silicon carbide substrate, a lowering of a yield caused by the crossing patterns can be suppressed.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: March 28, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Makoto Sasaki
  • Patent number: 9588027
    Abstract: Fluidic devices and methods associated with mixing of fluids in fluidic devices are provided. In some embodiments, a method may involve the mixing of two or more fluids in a channel segment of a fluidic device. The fluids may be in the form of, for example, at least first, second and third fluid plugs, composed of first, second, and third fluids, respectively. The second fluid may be immiscible with the first and third fluids. In certain embodiments, the fluid plugs may be flowed in series in the channel segment, e.g., in linear order, causing the first and third fluids to mix without the use of active to components such as mixers. The mixing of fluids in a channel segment as described herein may allow for improved performance and simplification in the design and operations of fluidic devices that rely on mixing of fluids.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: March 7, 2017
    Assignee: UPKO Diagnostics, LLC
    Inventors: Matthew Dirckx, Vincent Linder, Jason Taylor
  • Patent number: 9540234
    Abstract: A nanogap device which may include a first insulation layer having a nanopore formed therein, a first channel layer which may be on the first insulation layer, a first source electrode and a first drain electrode which may be respectively in contact with both ends of the first channel layer, a second insulation layer which may cover the first channel layer, the first source electrode, and the first drain electrode, and a first nanogap electrode which may be on the second insulation layer and may be divided into two parts with a nanogap, which faces the nanopore, interposed between the two parts.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: January 10, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-seung Lee, Yong-sung Kim, Jeo-young Shim, Joo-ho Lee
  • Patent number: 9484606
    Abstract: Embodiments are disclosed herein that relate to recycling and refurbishing battery electrode materials. For example, one disclosed embodiment provides a method comprising obtaining a quantity of spent electrode material, reacting the spent electrode material with an aqueous lithium solution in an autoclave while heating the spent electrode material and the aqueous lithium solution to form a hydrothermally reacted spent electrode material, removing the hydrothermally reacted spent electrode material from the aqueous lithium solution, and sintering the hydrothermally reacted spent material to form a recycled electrode material.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: November 1, 2016
    Assignee: Hulico LLC
    Inventors: Steven E. Sloop, Marshall Allen
  • Patent number: 9475040
    Abstract: A Cu-amine complex of hydrated copper sulfate and ethylene diamine or an oligomer of ethylene diamine is employed in a direct (one-pot) synthesis of a copper-cation containing silicoaluminophosphate (SAPO) zeolite material having the Cu/SAPO-34 structure. The copper-amine complex is included in an aqueous gel of precursors of the SiO2, Al2O3, and P2O5 constituents, which are mixed, aged, and thermally treated to form the desired Cu/SAPO-34 structure. The synthesized Cu/SAPO-34 material is demonstrated to be an effective catalyst material in conversion of nitric oxide to nitrogen (using ammonia as a reductant) in synthetic exhaust streams characteristic of diesel engine and other lean-burn vehicle engine exhaust streams.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: October 25, 2016
    Assignee: GM Global Technology Operations LLC
    Inventors: Gongshin Qi, Wei Li, Xiangju Meng, Fengshou Xiao
  • Patent number: 9469916
    Abstract: A method of producing a GaAs single crystal having high carrier concentration and high crystallinity and to provide a GaAs single crystal wafer using such a GaAs single crystal. In the method of producing a GaAs single crystal, a vertical boat method is performed with a crucible receiving a seed crystal, a Si material, a GaAs material serving as an impurity, solid silicon dioxide, and a boron oxide material, thereby growing a GaAs single crystal.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: October 18, 2016
    Assignee: DOWA ELECTRONICS MATERIALS CO., LTD.
    Inventors: Ryoichi Nakamura, Motoichi Murakami, Takehiro Miyaji
  • Patent number: 9464367
    Abstract: A method of producing an n-type group III nitride single crystal includes putting raw materials that include at least a substance including a group III element, an alkali metal, and boron oxide into a reaction vessel; melting the boron oxide by heating the reaction vessel to a melting point of the boron oxide; forming a mixed melt which includes the group III element, the alkali metal, and the boron oxide, in the reaction vessel by heating the reaction vessel to a crystal growth temperature of a group III nitride; dissolving nitrogen into the mixed melt by bringing a nitrogen-containing gas into contact with the mixed melt; and growing an n-type group III nitride single crystal, which is doped with oxygen as a donor, from the group III element, the nitrogen, and oxygen in the boron oxide that are dissolved in the mixed melt.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: October 11, 2016
    Assignee: RICOH COMPANY, LTD.
    Inventor: Hirokazu Iwata