Processes Of Growth With A Subsequent Step Acting On The Crystal To Adjust The Impurity Amount (e.g., Diffusing, Doping, Gettering, Implanting) Patents (Class 117/2)
  • Publication number: 20100244087
    Abstract: During the growth of a nitride semiconductor crystal on a nonpolar face nitride substrate, such as an m-face, the gas that constitutes the main flow in the process of heating up to a relatively high temperature range, before growth of the nitride semiconductor layer, (the atmosphere to which the main nitride face of the substrate is exposed) and the gas that constitutes the main flow until growth of first and second nitride semiconductor layers is completed (the atmosphere to which the main nitride face of the substrate is exposed) are primarily those that will not have an etching effect on the nitride, while no Si source is supplied at the beginning of growth of the nitride semiconductor layer. Therefore, nitrogen atoms are not desorbed from near the nitride surface of the epitaxial substrate, thus suppressing the introduction of defects into the epitaxial film. This also makes epitaxial growth possible with a surface morphology of excellent flatness.
    Type: Application
    Filed: November 20, 2008
    Publication date: September 30, 2010
    Applicant: Mitsubishi Chemical Corporation
    Inventors: Hideyoshi Horie, Kaori Kurihara
  • Patent number: 7777403
    Abstract: A photonic-crystal filament is formed by mixing a slurry comprising particles of substantially uniform size and a precursor material for a desired metal, urging the slurry through an orifice to force the particles and precursor material into a combination having a desired crystallographic configuration, drying the combination emerging from the orifice, and sintering the precursor material.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: August 17, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: David Champion, Gregory S. Herman, Hubert A. Vander Plas, David M. Schut
  • Patent number: 7776724
    Abstract: A method of forming a densified nanoparticle thin film is disclosed. The method includes positioning a substrate in a first chamber; and depositing a nanoparticle ink, the nanoparticle ink including a set of Group IV semiconductor particles and a solvent. The method also includes heating the nanoparticle ink to a first temperature between about 30° C. and about 300° C., and for a first time period between about 1 minute and about 60 minutes, wherein the solvent is substantially removed, and a porous compact is formed; and positioning the substrate in a second chamber, the second chamber having a pressure of between about 1×10?7 Torr and about 1×10?4 Torr. The method further includes depositing on the porous compact a dielectric material; wherein the densified nanoparticle thin film is formed.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: August 17, 2010
    Assignee: Innovalight, Inc.
    Inventors: Francesco Lemmi, Elena V. Rogojina, Pingrong Yu, David Jurbergs, Homer Antoniadis, Maxim Kelman
  • Patent number: 7771849
    Abstract: An epitaxial substrate including a single-crystal base material and an upper layer of a group III nitride crystal film which is epitaxially formed on a main surface of the base material undergoes heating treatment in a nitrogen atmosphere at 1950° C. or higher for one minute. The result showed that, while a ?-ALON layer was formed only at the interface between the base material and the upper layer, the dislocation density in the group III nitride crystal was reduced to one tenth or less of the dislocation density before the heating treatment. The result also showed that the surface of the epitaxial substrate after the heating treatment had a reduced number of pits, which confirmed that high-temperature and short-time heating treatment was effective at improving the crystal quality and surface flatness of the group III nitride crystal.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: August 10, 2010
    Assignees: NGK Insulators, Ltd., Dowa Electronics Material Co., Ltd.
    Inventors: Tomohiko Shibata, Shigeaki Sumiya
  • Patent number: 7758695
    Abstract: One embodiment of the present invention provides a method for fabricating a high-quality metal substrate. During operation, the method involves cleaning a polished single-crystal substrate. A metal structure of a predetermined thickness is then formed on a polished surface of the single-crystal substrate. The method further involves removing the single-crystal substrate from the metal structure without damaging the metal structure to obtain the high-quality metal substrate, wherein one surface of the metal substrate is a high-quality metal surface which preserves the smoothness and flatness of the polished surface of the single-crystal substrate.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: July 20, 2010
    Assignee: Lattice Power (Jiangxi) Corporation
    Inventors: Chuanbing Xiong, Wenqing Fang, Li Wang, Guping Wang, Fengyi Jiang
  • Patent number: 7754585
    Abstract: A method of subjecting a silicon wafer doped with boron to a heat treatment in an argon atmosphere, wherein the argon atmosphere is replaced with a hydrogen atmosphere or a mixed gas of an argon gas and a hydrogen gas in a proper fashion, to thereby uniformize a boron concentration in the thickness direction of the surface layer of the silicon wafer doped with boron.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: July 13, 2010
    Assignee: Sumco Techxiv Corporation
    Inventors: Yuji Sato, Shirou Yoshino, Hiroshi Furukawa, Hiroyuki Matsuyama
  • Patent number: 7754008
    Abstract: A method of forming a stressed thin film on a substrate includes forming a plurality of islands on a viscous layer that is present on a surface of a substrate. Adjacent islands are bridged with a stressor layer. The structure is annealed at an elevated temperature above the glass flow temperature of the viscous layer to transfer at least a portion of the stress from the stressor layer to the underlying islands. The bridges are then removed to expose the stressed islands of thin film on the substrate.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: July 13, 2010
    Assignee: The Regents of the University of California
    Inventors: Ya-Hong Xie, Jeehwan Kim
  • Patent number: 7754012
    Abstract: A method for manufacturing Group III nitride crystals with high quality is provided. By the method, a crystal raw material solution and gas containing nitrogen are introduced into a reactor vessel, which is heated, and crystals are grown in an atmosphere of pressure applied thereto. The gas is introduced from a gas supplying device to the reactor vessel through a gas inlet of the reactor vessel, and then is exhausted to the inside of a pressure-resistant vessel through a gas outlet of the reactor vessel. Since the gas is introduced directly to the reactor vessel, impurities attached to the pressure-resistant vessel and the like into the crystal growing site can be prevented. Further, the gas flows through the reactor vessel, to suppress aggregation of an evaporating alkali metal, etc., at the gas inlet and reduce flow of the metal vapor into the gas supplying device.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: July 13, 2010
    Assignees: Panasonic Corporation
    Inventors: Hisashi Minemoto, Yasuo Kitaoka, Isao Kidoguchi, Yusuke Mori, Fumio Kawamura, Takatomo Sasaki, Hidekazu Umeda, Yasuhito Takahashi
  • Patent number: 7732352
    Abstract: By using a two-step RTP (rapid thermal processing) process, the wafer is provided which has an ideal semiconductor device region secured by controlling fine oxygen precipitates and OiSFs (Oxidation Induced Stacking Fault) located on the surface region of the wafer. By performing the disclosed two-step rapid thermal process, the distribution of defects can be accurately controlled and an ideal device active zone can be formed up to a certain distance from the surfaces of the wafer. In addition, it is possible to maximize the internal gettering (IG) efficiency by enabling the oxygen precipitates and the bulk stacking faults to have constant densities in the depth direction in an internal region of the wafer, that is, the bulk region. In order to obtain the constant concentration profile of the oxygen precipitates and the bulk stacking faults in the bulk region, the wafer is subjected to the aforementioned two-step rapid thermal process in a predetermined mixed gas atmosphere.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: June 8, 2010
    Assignees: Hynix Semiconductor Inc., Siltron Inc.
    Inventors: Young Hee Mun, Kun Kim, Chung Geun Koh, Seung Ho Pyi
  • Publication number: 20100126406
    Abstract: In a method of producing diamonds by microwave plasma-assisted chemical vapor deposition which comprises providing a substrate and establishing a microwave plasma ball in an atmosphere comprising hydrogen, a carbon source and oxygen at a pressure and temperature sufficient to cause the deposition of diamond on said substrate, the improvement wherein the diamond is deposited under a pressure greater than 400 torr at a growth rate of at least 200 ?m/hr. from an atmosphere which is either essentially free of nitrogen or includes a small amount of nitrogen.
    Type: Application
    Filed: November 24, 2009
    Publication date: May 27, 2010
    Inventors: Chih-Shiue YAN, Ho-kwang MAO, Russell J. HEMLEY, Qi LIANG, Yufei MENG
  • Patent number: 7718515
    Abstract: The principal objects of the present invention are to provide structure of a semiconductor device capable of reducing a bowing of a wafer, and a method for fabricating the semiconductor device. The present invention is applied to a semiconductor device, which is fabricated with a semiconductor substrate having a silicon carbide (SiC) film. The method includes the steps of: forming the SiC film on a semiconductor wafer; discriminating a deformation condition of the semiconductor wafer; and forming grooves in the SiC film, the grooves having a shape determined in accordance with the deformation condition of the semiconductor wafer.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: May 18, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Kazuhide Abe
  • Patent number: 7704322
    Abstract: A static fluid and a second fluid are placed into contact along a microfluidic free interface and allowed to mix by diffusion without convective flow across the interface. In accordance with one embodiment of the present invention, the fluids are static and initially positioned on either side of a closed valve structure in a microfluidic channel having a width that is tightly constrained in at least one dimension. The valve is then opened, and no-slip layers at the sides of the microfluidic channel suppress convective mixing between the two fluids along the resulting interface. Applications for microfluidic free interfaces in accordance with embodiments of the present invention include, but are not limited to, protein crystallization studies, protein solubility studies, determination of properties of fluidics systems, and a variety of biological assays such as diffusive immunoassays, substrate turnover assays, and competitive binding assays.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: April 27, 2010
    Assignee: California Institute of Technology
    Inventors: Carl L. Hansen, Stephen R. Quake, James M. Berger
  • Publication number: 20100015438
    Abstract: A method of producing CVD diamond having a high colour, which is suitable for optical applications, for example. The method includes adding a gaseous source comprising a second impurity atom type to counter the detrimental effect on colour caused by the presence in the CVD synthesis atmosphere of a first impurity atom type. The described method applies to the production of both single crystal diamond and polycrystalline diamond.
    Type: Application
    Filed: June 22, 2006
    Publication date: January 21, 2010
    Inventors: Stephen David Williams, Daniel James Twitchen, Philip Maurice Martineau, Geoffrey Alan Scarsbrook, Ian Friel
  • Patent number: 7641735
    Abstract: Fabrication of doped AlN crystals and/or AlGaN epitaxial layers with high conductivity and mobility is accomplished by, for example, forming mixed crystals including a plurality of impurity species and electrically activating at least a portion of the crystal.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: January 5, 2010
    Assignee: Crystal IS, Inc.
    Inventors: Glen A. Slack, Leo J. Schowalter
  • Patent number: 7637997
    Abstract: A silicon single crystal is grown by the CZ method. A silicon melt from which the crystal is grown is added with dopant such that the crystal has a resistivity of 0.025 to 0.08 ?cm. As well as the dopant, carbon is added to the silicon melt. The crystal is pulled in a hydrogen-bearing inert atmosphere.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: December 29, 2009
    Assignee: Sumco Corporation
    Inventors: Toshiaki Ono, Wataru Sugimura, Masataka Hourai
  • Publication number: 20090304975
    Abstract: An epitaxial silicon wafer in which on growing an epitaxial film only on the front side of a large-sized wafer which is 450 mm or more in diameter, the wafer can be decreased in warpage to obtain a high intrinsic gettering performance and a method for producing the epitaxial silicon wafer. Intrinsic gettering functions have been imparted to a high resistant large-sized silicon wafer which is 450 mm or more in diameter and 0.1 ?·cm or more in specific resistance by introducing nitrogen, carbon or both of them to a melt on pulling up an ingot. Thereby, after the growth of an epitaxial film, a silicon wafer is less likely to warp greatly. As a result, it is possible to decrease the warpage of an epitaxial silicon wafer and also to obtain a high intrinsic gettering performance.
    Type: Application
    Filed: June 4, 2009
    Publication date: December 10, 2009
    Applicant: SUMCO CORPORATION
    Inventors: Seiji SUGIMOTO, Kazushige TAKAISHI
  • Patent number: 7628853
    Abstract: A lithium tantalate substrate obtained by working in the state of a substrate a lithium tantalate crystal grown by the Czochralski method is buried in a mixed powder of Al and Al2O3, followed by heat treatment carried out at a temperature kept to from 350 to 600° C., to manufacture a lithium tantalate substrate having volume resistivity which has been controlled within the range of from more than 108 to less than 1010 ?cm. The substrate obtained has no pyroelectricity, and it can be made colored and opaque from a colorless and transparent state and also sufficiently has the properties required as a piezoelectric material.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: December 8, 2009
    Assignee: Sumitomo Metal Mining Co., Ltd.
    Inventors: Tomio Kajigaya, Takashi Kakuta
  • Publication number: 20090260563
    Abstract: A method of producing a zinc oxide-based semiconductor crystal, including: introducing at least zinc and oxygen on a surface of a substrate; and growing a zinc oxide-based semiconductor crystal on the substrate, wherein a total or partial portion of the zinc is ionized in a vacuum atmosphere of 1×10?4 Torr or less and is introduced to the surface of the substrate to grow the ZnO based semiconductor crystal. As a result, it is possible to provide a method of producing a zinc oxide based semiconductor crystal capable of growing a zinc oxide semiconductor crystal having excellent surface flatness and crystallinity and including an extremely small amount of impurities at a high growth rate.
    Type: Application
    Filed: June 22, 2007
    Publication date: October 22, 2009
    Applicants: Fujikura Ltd., Chiba University
    Inventors: Koji Omichi, Yoshikazu Kaifuchi, Munehisa Fujimaki, Akihiko Yoshikawa
  • Patent number: 7566951
    Abstract: A silicon structure with improved protection against failures induced by excess radiation-induced charge carrier migration from the bulk region into the near-surface region. The structure comprises bulk and near-surface regions that are doped with a dopant, wherein the concentration in the near-surface region is at least 10 times the maximum concentration, c, of dopant in the bulk region. The structure further comprises a transition region between the bulk and near-surface regions extending less than about 1 ?m from the near-surface region toward the central plane.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: July 28, 2009
    Assignee: MEMC Electronic Materials, Inc.
    Inventor: Michael R. Seacrist
  • Publication number: 20090187243
    Abstract: We describe herein biocompatible single crystal Cu-based shape memory alloys (SMAs). In particular, we show biocompatibility based on MEM elution cell cytotoxicity, ISO intramuscular implant, and hemo-compatibility tests producing negative cytotoxic results. This biocompatibility may be attributed to the formation of a durable oxide surface layer analogous to the titanium oxide layer that inhibits body fluid reaction to titanium nickel alloys, and/or the non-existence of crystal domain boundaries may inhibit corrosive chemical attack. Methods for controlling the formation of the protective aluminum oxide layer are also described, as are devices including such biocompatible single crystal copper-based SMAs.
    Type: Application
    Filed: December 1, 2008
    Publication date: July 23, 2009
    Inventor: Alfred David Johnson
  • Patent number: 7563320
    Abstract: Scandium, yttrium, and lanthanide sesquioxide crystals having the formula Ln2O3, wherein Ln is selected from Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, with or without an activator ion, are made by a hydrothermal method for a variety of end-use applications.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: July 21, 2009
    Inventors: Joseph Kolis, Colin D. McMillen
  • Publication number: 20090169814
    Abstract: A method for growing a low-resistance phosphorus-doped epitaxial thin film having a specific resistance of 300 ?cm or less at 300 K on a principal surface of a {111} monocrystal substrate under conditions in which the phosphorus atom/carbon atom ratio is 3% or higher, includes the principal surface having an off-angle of 0.50° or greater. The diamond monocrystal having a low-resistance phosphorus-doped diamond epitaxial thin film is such that the thin-film surface has an off-angle of 0.50° or greater with respect to the {111} plane, and the specific resistance of the low-resistance phosphorus-doped diamond epitaxial thin film is 300 ?cm or less at 300 K.
    Type: Application
    Filed: December 26, 2007
    Publication date: July 2, 2009
    Inventors: Akihiko Ueda, Kiichi Meguro, Yoshiyuki Yamamoto, Yoshiki Nishibayashi, Takahiro Imai
  • Publication number: 20090130014
    Abstract: In order to efficiently recycle a silicon scrap obtained by cutting a silicon chunk as a raw material silicon for solar batteries, a silicon recycling method of the present invention, according to one aspect, includes the steps of melting a silicon scrap by heating, and immersing a crystallization substrate in molten silicon and depositing silicon on a surface of the crystallization substrate. The step of separating silicon on the surface of the crystallization substrate from the crystallization substrate is preferably included. In addition, a silicon ingot obtained by melting the silicon raw material for solar batteries in a mold and solidifying the same is suitable as the silicon chunk.
    Type: Application
    Filed: July 3, 2006
    Publication date: May 21, 2009
    Inventors: Toshiaki Fukuyama, Tetsuhiro Okuno, Junzo Wakuda
  • Publication number: 20090127663
    Abstract: A growing method of a group III nitride semiconductor crystal includes the steps of preparing an underlying substrate, and growing a group III nitride semiconductor crystal doped with silicon by using silicon tetrafluoride gas as doping gas, on the underlying substrate by vapor phase growth.
    Type: Application
    Filed: November 18, 2008
    Publication date: May 21, 2009
    Applicant: Sumitomo Electric Industries. Ltd.
    Inventors: Takuji Okahisa, Tomohiro Kawase, Tomoki Uemura, Muneyuki Nishioka, Satoshi Arakawa
  • Publication number: 20090092810
    Abstract: An SOI substrate has a gettering layer of silicon-germanium (SiGe) with 5-10% Ge, and a thickness of approximately 50-1000 nm. Carbon (C) may be added to SiGe to stabilize the dislocation network. The SOI substrate may be a SIMOX SOI substrate, or a bonded SOI substrate, or a seeded SOI substrate. The gettering layer may disposed under a buried oxide (BOX) layer. The gettering layer may be disposed on a backside of the substrate.
    Type: Application
    Filed: October 4, 2007
    Publication date: April 9, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Junedong Lee, Devendra K. Sadana, Dominic J. Schepis
  • Publication number: 20090087645
    Abstract: Affords methods of manufacturing AlN crystals, and AlN crystals, AlN crystal substrates, and semiconductor devices fabricated employing the AlN crystal substrates, that enable semiconductor devices having advantageous properties to be obtained. One aspect of the present invention is an AlN crystal manufacturing method including a step of growing AlN crystal onto the surface of a SiC seed-crystal substrate, and a step of picking out at least a portion of the AlN crystal lying a range of from 2 mm to 60 mm from the SiC seed-crystal substrate surface into the AlN crystal. Furthermore, other aspects are AlN crystals and AlN crystal substrates manufactured by the method, and semiconductor devices fabricated employing the AlN crystal substrates.
    Type: Application
    Filed: January 10, 2007
    Publication date: April 2, 2009
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Naho Mizuhara, Michimasa Miyanaga, Tomohiro Kawase, Shinsuke Fujiwara
  • Patent number: 7507293
    Abstract: Fabrication of a photonic crystal is described. A patterned array of nanowires is formed, the nanowires extending outward from a surface, the nanowires comprising a catalytically grown nanowire material. Spaces between the nanowires are filled with a slab material, the patterned array of nanowires defining a patterned array of channels in the slab material. The nanowire material is then removed from the channels.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: March 24, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Zhiyong Li, R. Stanley Williams, M. Saif Islam, Philip J. Kuekes
  • Patent number: 7507289
    Abstract: In a solid solution system of Al2O3 and CAO or SrO, it has been difficult to obtain a material having a high electrical conductivity (>10?4 S·cm?) at room temperature. A compound is provided in which electrons at a high concentration are introduced into a 12CaO.7Al2O3 compound, a 12SrO.7Al2O3 compound, or a mixed crystal compound containing 12CaO.7Al2O3 and 12SrO.7Al2O3. The compound formed by substituting all the free oxygen ions with electrons is regarded as an electride compound in which [Ca24Al28O64]4+(4e?) or [Sr24Al28O64]4+(4e?) serves as a cation and electrons serve as anions. When a single crystal or a hydrostatic pressure press molded material of a fine powder thereof is held at approximately 700° C. in an alkaline metal vapor or an alkaline earth metal vapor, melt of a hydrostatic pressure press molded material of a powder is held at approximately 1,600° C. in a carbon crucible, followed by slow cooling for solidification, or a thin film of the compound held at approximately 600° C.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: March 24, 2009
    Assignee: Japan Science and Technology Agency
    Inventors: Hideo Hosono, Masahiro Hirano, Katsuro Hayashi, Masashi Miyakawa, Isao Tanaka
  • Publication number: 20090071394
    Abstract: A low dislocation density AlxInyGa1-x-yN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing an AlxInyGa1-x-yN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).
    Type: Application
    Filed: November 18, 2008
    Publication date: March 19, 2009
    Applicant: SUMITOMO ELECTRONIC INDUSTRIES, LTD.
    Inventors: Seiji NAKAHATA, Ryu HIROTA, Kensaku MOTOKI, Takuji OKAHISA, Koji UEMATSU
  • Publication number: 20090056374
    Abstract: A gemstone can include a crown portion having a table facet, a plurality of trapezoidal facets, a plurality of irregular-hexagonal facets, a plurality of irregular-pentagonal facets, and a plurality of triangular crown-facets. The gemstone can also include a pavilion portion having a plurality of first kite facets, a plurality of irregular-quadrilateral facets, a plurality of second kite facets, and a plurality of triangular pavilion-facets.
    Type: Application
    Filed: August 31, 2007
    Publication date: March 5, 2009
    Inventor: Steven L. Abate
  • Patent number: 7494888
    Abstract: The present invention provides a process for manufacturing a semiconductor device that can be incorporated into an integrated circuit. The method includes, forming a first doped layer of isotopically enriched silicon over a foundational substrate, forming a second layer of an isotopically enriched semiconductor material silicon over the first doped layer, and constructing active devices on the second layer. The device includes a first doped layer of an isotopically enriched semiconductor material and a second layer of an isotopically enriched semiconductor material located over the first doped layer, and active devices located on the second layer.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: February 24, 2009
    Assignee: Agere Systems Inc.
    Inventors: Peter L. Gammel, Bailey R. Jones, Isik Kizilyalli, Hugo F. Safar
  • Publication number: 20090041648
    Abstract: A radiation detector crystal is made from CdxZn1-xTe, where 0?x?1; an element from column III or column VII of the periodic table, desirably in a concentration of about 1 to 10,000 atomic parts per billion; and the element Ruthenium (Ru), the element Osmium (Os) or the combination of Ru and Os, desirably in a concentration of about 1 to 10,000 atomic parts per billion using a conventional crystal growth method, such as, for example, the Bridgman method, the gradient freeze method, the electro-dynamic gradient freeze method, the so-call traveling heater method or by the vapor phase transport method. The crystal can be used as the radiation detecting element of a radiation detection device configured to detect and process, without limitation, X-ray and Gamma ray radiation events.
    Type: Application
    Filed: January 27, 2006
    Publication date: February 12, 2009
    Inventors: Csaba Szeles, Scott E. Cameron, Vincent D. Mattera, JR., Utpal K. Chakrabarti
  • Publication number: 20090007839
    Abstract: The present invention provides a method for manufacturing a silicon single crystal wafer in which a silicon single crystal ingot is pulled by a CZ method, and a wafer sliced from the ingot is subjected to a rapid thermal annealing, wherein wafers sliced from the ingot which has been pulled while changing a pulling rate are subjected to rapid thermal annealings in various heat treatment temperatures, oxide dielectric breakdown voltage measurements are performed to get a relation between the pulling rate and the heat treatment temperatures, and a result of the oxide dielectric breakdown voltage measurements in advance, conditions of a pulling rate and a heat treatment temperature are determined based on the relation so that the whole area thereof in the radial direction may become N region after the rapid thermal annealing, and the pulling of the ingot and the rapid thermal annealing are performed to thereby manufacture the silicon single crystal wafer.
    Type: Application
    Filed: December 21, 2006
    Publication date: January 8, 2009
    Applicant: Shin-Etsu Handotai Co., Ltd.
    Inventor: Koji Ebara
  • Publication number: 20080311019
    Abstract: In a Czochralski (CZ) single crystal puller equipped with a cooler and a thermal insulation member, which are to be disposed in a CZ furnace, smooth recharge and additional charge of material are made possible. Further, elimination of dislocations from a silicon seed crystal by use of the Dash's neck method can be performed smoothly. To these ends, there is provided a CZ single crystal puller, wherein a cooler and a thermal insulation member are immediately moved upward away from a melt surface during recharge or additional charge of material or during elimination of dislocations from a silicon seed crystal by use of the Dash's neck method.
    Type: Application
    Filed: October 31, 2007
    Publication date: December 18, 2008
    Applicant: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventors: Hiroshi Inagaki, Shigeki Kawashima, Makoto Kamogawa, Toshirou Kotooka, Toshiaki Saishoji, Daisuke Ebi, Kentaro Nakamura, Kengo Hayashi, Yoshinobu Hiraishi, Shigeo Morimoto, Hiroshi Monden, Tadayuki Hanamoto, Tadashi Hata
  • Patent number: 7462237
    Abstract: The present invention provides computer-implementable systems and methods for generating images of crystals. The systems each include (a) a light source; (b) a rotatable first polarizing material; (c) a rotatable second polarizing material; (d) a light-capturing device; and (e) a software program executable on the computer-implementable system for analyzing electrical signals from the light-capturing device.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: December 9, 2008
    Assignee: deCODE biostructures, Inc.
    Inventors: Peter Nollert-von Specht, Mark B. Mixon
  • Patent number: 7459025
    Abstract: Systems and methods for transferring a thin film from a substrate onto another substrate, a layer of the same area as the substrate, of a thickness from sub-micron to tens of micron, and of the thickness and flatness required by VLSI and MEMS applications, and with sufficiently low defect density in the transferred layer are disclosed. The method enables separating a solid layer from a supply substrate and optionally transferring the solid layer onto a target substrate. The method generally includes providing the solid layer on a hydrogen recombination region containing hydrogen-recombination-dopant at a concentration higher than that of the solid layer. The supply substrate includes the solid layer, a mother substrate, and the hydrogen recombination region. The hydrogen recombination region may form a part of the mother substrate or may be separate therefrom.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: December 2, 2008
    Inventor: Tien-Hsi Lee
  • Patent number: 7442250
    Abstract: A lithium tantalate substrate obtained by working in the state of a substrate a lithium tantalate crystal grown by the Czochralski method is buried in a mixed powder of Al and Al2O3, followed by heat treatment carried out at a temperature kept to from 350 to 600° C, to manufacture a lithium tantalate substrate having volume resistivity which has been controlled within the range of from 106 to 108 ?cm. The substrate obtained has no piezoelectricity, and it can be made colored and opaque from a colorless and transparent state and also sufficiently has the properties required as a piezoelectric material.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: October 28, 2008
    Assignee: Sumitomo Metal Mining Co., Ltd.
    Inventors: Tomio Kajigaya, Takashi Kakuta
  • Patent number: 7438762
    Abstract: A manufacture method that can manufacture ZnO based compound semiconductor crystal of good quality. A ZnO substrate is prepared to have a principal surface made of a plurality of terraces of (0001) planes arranged stepwise along an m-axis direction, the envelop of the principal surface being inclined relative to the (0001) plane by about 2 degrees or less. ZnO based compound semiconductor crystal is grown on the principal surface.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: October 21, 2008
    Assignee: Stanley Electric Co., Ltd., Tokyo Denpa Co., Ltd., and Tohoku University
    Inventors: Hiroyuki Kato, Michihiro Sano, Katsumi Maeda, Hiroshi Yoneyama, Takafumi Yao, Meoung Whan Cho
  • Patent number: 7431764
    Abstract: The axial temperature gradient G at the vicinity of the solid-liquid interface 24 in an ingot is calculated in consideration of the heating value of a heater 18, the dimensions and physical property values of furnace inside components and the convection of the melt 12 before pulling up the single crystal ingot 15 by a puller 10 by use of a numerical simulation of synthetic heater transfers and a numerical simulation of melt convection. Then, the pulling velocity V of the single crystal ingot is determined from an value experienced of the ratio C=V/G of the pulling velocity V and the axial temperature gradient G of the single crystal ingot at which the single crystal ingot becomes defect-free, obtained when the single crystal ingot was pulled up by a same type puller as the puller in the past, and the axial temperature gradient G calculated by use of the simulations.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: October 7, 2008
    Assignee: Sumco Corporation
    Inventors: Senlin Fu, Naoki Ono
  • Publication number: 20080223285
    Abstract: Systems and methods for transferring a thin film from a substrate onto another substrate, a layer of the same area as the substrate, of a thickness from sub-micron to tens of micron, and of the thickness and flatness required by VLSI and MEMS applications, and with sufficiently low defect density in the transferred layer are disclosed. The method enables separating a solid layer from a supply substrate and optionally transferring the solid layer onto a target substrate. The method generally includes providing the solid layer on a hydrogen recombination region containing hydrogen-recombination-dopant at a concentration higher than that of the solid layer. The supply substrate includes the solid layer, a mother substrate, and the hydrogen recombination region. The hydrogen recombination region may form a part of the mother substrate or may be separate therefrom.
    Type: Application
    Filed: June 3, 2003
    Publication date: September 18, 2008
    Inventor: Tien-Hsi Lee
  • Publication number: 20080216736
    Abstract: A microfluidic method is provided that comprises: delivering a first fluid to a first lumen of a microfluidic device and a second, different fluid to a second lumen of the microfluidic device, the first and second lumens sharing a common wall which allows for diffusion between the lumens over at least a portion of the length of the lumens; and having the first and second fluids diffuse between the first and second lumens.
    Type: Application
    Filed: May 23, 2008
    Publication date: September 11, 2008
    Applicant: TAKEDA SAN DIEGO, INC.
    Inventor: Peter R. David
  • Publication number: 20080213543
    Abstract: A semiconductor compound material, preferably a III-N-bulk crystal or a III-N-layer, is manufactured in a reactor by means of hydride vapour phase epitaxy (HVPE), wherein in a mixture of carrier gases a flow profile represented by local mass flow rates is formed in the reactor. The mixture can carry one or more reaction gases towards a substrate. Thereby, a concentration of hydrogen important for the reaction and deposition of reaction gases is adjusted at the substrate surface independently from the flow profile simultaneously formed in the reactor.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 4, 2008
    Inventors: Gunnar Leibiger, Frank Habel, Stefan Eichler
  • Patent number: 7419547
    Abstract: In a first exemplary embodiment of the present invention, a method is provided for marking a sample of a doped crystalline material. According to a feature of the present invention, the method comprises the steps of causing a controlled alteration to the crystalline material at a preselected spot on the sample of the crystalline material, sufficient to cause a change in a cathodoluminescence spectrum of the crystalline material at the preselected spot and utilizing the altered cathodoluminescence spectrum to mark the crystalline material.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: September 2, 2008
    Assignee: American Museum of Natural History
    Inventor: Jacob Louis Mey
  • Publication number: 20080185580
    Abstract: A ZnO crystal growth method has the steps of (a) preparing a substrate having a surface capable of growing ZnO crystal exposing a Zn polarity plane; (b) supplying Zn and O above the surface of the substrate by alternately repeating a Zn-rich condition period and an O-rich condition period; and (c) supplying conductivity type determining impurities above the surface of the substrate while Zn and O are supplied at the step (b).
    Type: Application
    Filed: February 8, 2008
    Publication date: August 7, 2008
    Inventors: Hiroyuki KATO, Michihiro Sano
  • Publication number: 20080171133
    Abstract: The invention relates to a method for producing c-plane GaN substrates or AlxGa1-xN substrates using an original substrate. Said method is characterized by the following steps: a tetragonal (100)-oriented or (?100)-oriented original LiAlO2 substrate is used; said original substrate is nitrided in a nitrogen compound-containing atmosphere at temperatures lying below the decomposition temperature of LiAlO2; a nucleation layer is grown at temperatures ranging between 500° C. and 700° C. by adding GaCl or AlCl or a mixture of GaCl and AlCl in a nitrogen compound-containing atmosphere; single-crystalline c-plane-oriented GaN or AlxGa1-xN is grown on the nucleation layer at temperatures ranging between 900° C. and 1050° C. by means of hydride vapor phase epitaxy (HVPE) with GaCl or AlCl or a GaCl/AlCl mixture in a nitrogen compound-containing atmosphere; and the substrate is cooled.
    Type: Application
    Filed: January 18, 2006
    Publication date: July 17, 2008
    Applicant: Freiberger Compound Materials GMBH
    Inventors: Eberhard Richter, Gunther Trankle, Markus Weyers
  • Publication number: 20080163813
    Abstract: An anneal of an epitaxially grown crystalline semiconductor layer comprising a combination of group-IV elements. The layer contains at least one of the group of carbon and tin. The layer of epitaxially grown material is annealed at a temperature substantially in a range of 1,000 to 1,400 degrees Celsius for a period not to exceed 100 milliseconds within 10% of the peak temperature. The anneal is performed for example with a laser anneal or a flash lamp anneal. The limited-time anneal may improve carrier mobility of a transistor.
    Type: Application
    Filed: January 8, 2007
    Publication date: July 10, 2008
    Inventors: Stefan Zollner, Veeraraghavan Dhandapani, Paul A. Grudowski, Gregory S. Spencer
  • Patent number: 7397110
    Abstract: A high-resistance silicon wafer is manufactured in which a gettering ability, mechanical strength, and economical efficiency are excellent and an oxygen thermal donor is effectively prevented from being generated in a heat treatment for forming a circuit, which is implemented on the side of a device maker. A heat treatment for forming an oxygen precipitate nucleus is performed at 500 to 900° C. for 5 hours or more in a non-oxidizing atmosphere and a heat treatment for growing an oxygen precipitate is performed at 950 to 1050° C. for 10 hours or more on a high-oxygen and carbon-doped high-resistance silicon wafer in which resistivity is 100 ?cm or more, an oxygen concentration is 14×1017 atoms/cm3 (ASTM F-121, 1979) or more and a carbon concentration is 0.5×1016 atoms/cm3 or more. By these heat treatments, a remaining oxygen concentration in the wafer is controlled to be 12×1017 atoms/cm3 (ASTM F-121, 1979) or less.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: July 8, 2008
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Nobumitsu Takase, Hideshi Nishikawa, Makoto Ito, Koji Sueoka, Shinsuke Sadamitsu
  • Patent number: 7396404
    Abstract: The present disclosure provides methods for forging cylindrical alkali halide melt-grown single-crystal-type ingots into rectangular blocks. The resulting rectangular blocks are devoid of peripheral cracks and fissures, and possess uniform properties and reduced levels of impurities.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: July 8, 2008
    Assignee: Siemens Medical Solutions USA, Inc.
    Inventors: Olexy V. Radkevich, Efim Toutchinskii, Yuriy Yakovlev, Robert S. Zwolinski
  • Publication number: 20080156255
    Abstract: The present invention relates to an apparatus for vapour phase crystal growth to produce multiple single crystals in one growth cycle comprising one central source chamber, a plurality of growth chambers, a plurality of passage means adapted for transport of vapour from the source chamber to the growth chambers, wherein the source chamber is thermally decoupled from the growth chambers.
    Type: Application
    Filed: February 2, 2006
    Publication date: July 3, 2008
    Inventors: Arnab Basu, Max Robinson, Ben Cantwell, Andy Brinkman
  • Publication number: 20080152568
    Abstract: A method for producing crystallized silicon according to the EFG process by using a shaping part, between which part and a silicon melt, crystallized silicon grows in a growth zone. Inert gas and at least water vapor are fed into the silicon melt and/or growth zone, by means of which the oxygen content of the crystallized silicon is increased. From 50 to 250 ppm of vapor water is added to the inert gas, and the inert gas has an oxygen, CO and/or CO2 content of less than 20 ppm total.
    Type: Application
    Filed: December 14, 2007
    Publication date: June 26, 2008
    Applicant: SCHOTT SOLAR GMBH
    Inventors: Albrecht SEIDL, Ingo SCHWIRTLICH