{b,al,ga,in,tl}{p,as,sb,bi} Compound Containing, Except Intermetallics Thereof (i.e., Except {al,ga,in,tl}{sb,bi}) {c30b 29/40} Patents (Class 117/953)
  • Patent number: 11781240
    Abstract: The invention discloses a method for preparing an indium phosphide crystal by using an indium-phosphorus mixture, belongs to the technical field of semiconductors, and comprises the steps of preparing an indium-phosphorus mixed ball, charging, maintaining the high furnace pressure and the low temperature of the indium-phosphorus mixed ball, melting a covering agent, feeding, synthesizing and crystal growing, which is synthesized by directly melting the proportioned indium-phosphorus mixed ball. Indium powder and phosphorus powder are uniformly mixed and pressed into spherical indium-phosphorus mixed particles, then the mixture of the indium-phosphorus mixed balls and the boron oxide powder is fed into a melt with a boron oxide covering agent, and crystal growth in situ is performed after synthesis.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: October 10, 2023
    Assignee: THE 13TH RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Niefeng Sun, Shujie Wang, Yanlei Shi, Huimin Shao, Lijie Fu, Xiaolan Li, Yang Wang, Senfeng Xu, Huisheng Liu, Tongnian Sun
  • Patent number: 11725300
    Abstract: In a crystal growth furnace having an array of vertically arranged heaters to provide controlled heating zones within a chamber, and a crucible for holding crystal material, wherein the crystal is grown vertically through the heating zones, the improvement includes a laser mounted outside the chamber which radiates a beam of energy to locally melt precipitates and inclusions. The furnace includes a mechanism to position the laser vertically to, at or near the interface between the formed crystal and crystal melt material above the formed crystal. The crystal material can be CdZnTe.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: August 15, 2023
    Assignee: EPIR, INC.
    Inventors: Sushant Sonde, Yong Chang, Silviu Velicu
  • Patent number: 11427925
    Abstract: The present application provides an apparatus and a method for ingot growth. The apparatus for ingot growth comprises a growth furnace, a crucible, a heater, a lifting mechanism, an infrared detector, a dividing disc, a sensor and a control device. The crucible is located within the growth furnace. The lifting mechanism comprises a lifting wire and a driving device, wherein the lifting wire connects to the top of the ingot via one terminal and to the driving device via another terminal. The bottom of the ingot puts inside the crucible, and the ingot has plural crystal lines thereon. The infrared detector is located outside the growth furnace. The dividing disc is above the growth furnace, connects to the lifting mechanism, and rotates with the ingot synchronously under the driving of the lifting mechanism, and an orthographic projection of bisector of the dividing disc is between two adjacent crystal lines. The sensor is located on the periphery of the dividing disc.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: August 30, 2022
    Assignee: Zing Semiconductor Corporation
    Inventor: Xuliang Zhao
  • Patent number: 9805914
    Abstract: Methods for removing contamination from a surface disposed in a substrate processing system are provided herein. In some embodiments, a method for removing contaminants from a surface includes: providing a first process gas comprising a chlorine containing gas, a hydrogen containing gas, and an inert gas to a process chamber having the surface disposed within the process chamber; igniting the first process gas to form a plasma from the first process gas; and exposing the surface to the plasma to remove contaminants from the surface. In some embodiments, the surface is an exposed surface of a process chamber component. In some embodiments, the surface is a surface of a first layer disposed atop a substrate, such as a semiconductor wafer.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: October 31, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chun Yan, Jim Zhongyi He, Xinyu Bao, Teng-Fang Kuo, Zhenwen Ding, Adam Lane
  • Patent number: 8815010
    Abstract: A method for producing a low-dislocation InP single crystal suitably used for an optical device such as a semiconductor laser, and the low-dislocation InP single crystal wafer are provided. In a liquid-encapsulated Czochralski method in which a semiconductor raw material and an encapsulant are contained in a raw material melt containing part comprising a cylindrical crucible having a bottom, the raw material containing part is heated to melt the raw material, and a seed crystal is brought into contact with a surface of a melt of the raw material in a state of being covered with the encapsulant to grow a crystal while the seed crystal is raised; a crystal shoulder part is grown from the seed crystal by setting a temperature gradient in a crystal growth direction to 25° C./cm or less and setting a temperature-fall amount to 0.25° C./hr or more. Thus, an iron-doped or undoped InP single crystal wafer in which an area having a dislocation density of 500/cm2 or less occupies 70% or more is realized.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: August 26, 2014
    Assignee: Nippon Mining & Metals Co., Ltd.
    Inventors: Akira Noda, Ryuichi Hirano
  • Patent number: 8231728
    Abstract: An epitaxial growth method forming a semiconductor thin film including a heterojunction of a group III-V compound semiconductor by means of molecular beam epitaxy. The method is configured to include: a first step of irradiating a molecular beam of at least one of group III elements and a molecular beam of a first group V element to form a first compound semiconductor layer; a second step of stopping the irradiation of the molecular beam of the group III element and the molecular beam of the first group V element to halt growth until an amount of the first group V element supplied is reduced to 1/10 or less of a supply of the first group V element in the first step; and a third step of irradiating a molecular beam of at least one of the group III elements and a molecular beam of a second group V element to form a second compound semiconductor layer, which is different from the first compound semiconductor, on the first compound semiconductor layer.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: July 31, 2012
    Assignee: Nippon Mining & Metals Co., Ltd.
    Inventors: Misao Takakusaki, Susumu Kanai
  • Patent number: 7804019
    Abstract: A substrate is provided including a growth surface that is offcut relative to a plane defined by a crystallographic orientation of the substrate at an offcut angle of about 5 degrees to about 45 degrees. A thermoelectric film is epitaxially grown on the growth surface. A crystallographic orientation of the thermoelectric film may be tilted about 5 degrees to about 30 degrees relative to the growth surface. The growth surface of the substrate may also be patterned to define a plurality of mesas protruding therefrom prior to epitaxial growth of the thermoelectric film. Related methods and thermoelectric devices are also discussed.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: September 28, 2010
    Assignee: Nextreme Thermal Solutions, Inc.
    Inventors: Jonathan Pierce, Robert P. Vaudo
  • Patent number: 7323256
    Abstract: Large area, uniformly low dislocation density single crystal III-V nitride material, e.g., gallium nitride having a large area of greater than 15 cm2, a thickness of at least 1 mm, an average dislocation density not exceeding 5E5 cm?2, and a dislocation density standard deviation ratio of less than 25%. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: January 29, 2008
    Assignee: Cree, Inc.
    Inventors: Xueping Xu, Robert P. Vaudo
  • Publication number: 20070256630
    Abstract: A crystal growth setup within a physical vapor transport growth furnace system for producing AlN monocrystal boules at high temperatures includes a crucible effective to contain an AlN source material and a growing AlN crystal boule. This crucible has a thin wall thickness in at least that portion housing the growing AlN crystal boule. Other components include a susceptor, in case of an inductive heating, or a heater, in case of a resistive heating, a thermal insulation enclosing the susceptor or heater effective to provide a thermal gradient inside the crucible in the range of 5-100° C./cm and a furnace chamber capable of being operated from a vacuum (<0.1 torr) to a gas pressure of at least 4000 torr through filling or flowing a nitrogen gas or a mixture of nitrogen gas and argon gas. The high temperatures contribute to a high boule growth rate and the thin wall thickness contributes to reduced imparted stress during boule removal.
    Type: Application
    Filed: April 25, 2007
    Publication date: November 8, 2007
    Inventor: Shaoping Wang
  • Patent number: 7211337
    Abstract: Provided are a compound semiconductor crystal substrate capable of reducing planar defects such as twins and anti-phase boundaries occurring in epitaxially grown crystals without additional steps beyond epitaxial growth, and a method of manufacturing the same. A compound single crystal substrate, the basal plane of which is a nonpolar face, with said basal plane having a partial surface having polarity (a partial polar surface). Said partial polar surface is a polar portion of higher surface energy than said basal plane.
    Type: Grant
    Filed: December 15, 2003
    Date of Patent: May 1, 2007
    Assignee: Hoya Corporation
    Inventors: Hiroyuki Nagasawa, Kuniaki Yagi, Takamitsu Kawahara
  • Patent number: 7135070
    Abstract: Monolithic stacked/layered room-temperature-processed materials whose internal crystalline structures are laser modification to create arrays of mechanical, and combined mechanical and electrical, devices with precision-established properties, such as important mechanical properties. Methodology and system configurations are disclosed.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: November 14, 2006
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: John W. Hartzell
  • Patent number: 7132091
    Abstract: A single crystal silicon ingot having a constant diameter portion that contains arsenic dopant atoms at a concentration which results in the silicon having a resistivity that is less than about 0.003 ?·cm.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: November 7, 2006
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Milind Kulkarni, Mohsen Banan, Christopher V. Luers
  • Patent number: 7128783
    Abstract: Thin-film laser-effected internal crystalline structure modified materials suitable for the creation of various small-dimension mechanical devices, either singly or in monolithic arrays, such as MEMS devices. Processing is carried out at room temperature and atmospheric pressure.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: October 31, 2006
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: John W. Hartzell
  • Patent number: 7125451
    Abstract: Laser processing of various materials to create mechanical devices whose internal mechanical properties are provided in final useable form by adjustments made in internal crystalline structure.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: October 24, 2006
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: John W. Hartzell
  • Patent number: 7118813
    Abstract: A III–V nitride, e.g., GaN, substrate including a (0001) surface offcut from the <0001> direction predominantly toward a direction selected from the group consisting of <10-10> and <11-20> directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 ?m2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm?2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III–V nitride-based microelectronic and opto-electronic devices.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: October 10, 2006
    Assignee: Cree, Inc.
    Inventors: Xueping Xu, Robert P. Vaudo, Jeffrey S. Flynn, George R. Brandes
  • Patent number: 7097920
    Abstract: To provide a semiconductor substrate of a group III nitride with a little warp, this invention provides a process comprising such steps of: epitaxial-growing a GaN layer 33 with a GaN low temperature grown buffer layer 32 upon a sapphire substrate 31; removing the sapphire substrate 31, the GaN buffer layer 32 and a small portion of the GaN layer 33 from the substrate taken out of a growth reactor to obtain a self-supporting GaN substrate 35; and after that, heat-treating the GaN substrate 35 by putting it into an electric furnace under the NH3 atmosphere at 1200° C. for 24 hours; which leads to a marked reduction of the warp of the self-supporting GaN substrate 35 such that dislocation densities of its obverse and reverse surface are 4×107 cm?2 and 8×105 cm?2, and thereby such a low ratio of dislocation densities of 50 is well-controlled.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: August 29, 2006
    Assignees: NEC Corporation, Hitachi Cable, Ltd.
    Inventors: Akira Usui, Masatomo Shibata, Yuichi Oshima
  • Patent number: 7011707
    Abstract: A reaction prevention layer is formed to prevent Si from reacting with a gallium nitride group semiconductor (semiconductor crystal A) which is deposited after the reaction prevention layer is formed. By forming a reaction prevention layer comprising a material whose melting point or thermal stability is higher than that of a gallium nitride group semiconductor, e.g., AlN, on a sacrifice layer, a reaction part is not formed in the semiconductor substrate deposited on the reaction prevention layer when the gallium nitride group semiconductor is grown by crystal growth for a long time. In short, owing to the effect that the reaction prevention layer prevents silicon (Si) from diffusing, the reaction part is generated only in the sacrifice layer and it is never formed at the upper portion of the reaction prevention layer even by growing the semiconductor crystal A at a high temperature for a long time.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: March 14, 2006
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Seiji Nagai, Kazuyoshi Tomita, Yoshihiro Irokawa, Kenji Ito
  • Patent number: 6955858
    Abstract: Transition metal doped II–V nitride material films exhibit ferromagnetic properties at or above room temperature. A III–V nitride material film may be doped with a transition metal film in-situ during metal-organic chemical vapor deposition and/or by solid-state diffusion processes. Doping of the III–V nitride material films may proceed in the absence of hydrogen and/or in the presence of nitrogen. In some embodiments, transition metal-doped III–V nitride material films comprise carbon concentrations of at least 1017 atoms per cubic centimeter.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: October 18, 2005
    Assignee: North Carolina State University
    Inventors: Nadia A. ElMasry, Salah M. Bedair, Meredith L. Reed, Hans Stadelmaier
  • Patent number: 6936103
    Abstract: A method of suppression of Indium carry-over in the MOCVD growth of thin InGaAsP quantum wells, with low Indium content, on top of thick GaInAsP, with high Indium content. These quantum wells are essential in the stimulated emission of 808 to 880 nm phosphorous-based laser structures. The Indium carryover effect is larger in large multi wafer reactors and therefore is this invention focused on large multiwafer MOCVD reactors. This invention improves the quality of the quantum well, as measured by photo-luminescence spectra and uniformity of wavelength radiation.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: August 30, 2005
    Assignee: Spectra-Physics, Inc.
    Inventor: Frank Reinhardt
  • Patent number: 6936357
    Abstract: Bulk GaN and AlGaN single crystal boules, preferably fabricated using a modified HVPE process, are provided. The single crystal boules typically have a volume in excess of 4 cubic centimeters with a minimum dimension of approximately 1 centimeter. If desired, the bulk material can be doped during growth, for example to achieve n-, i-, or p-type conductivity.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: August 30, 2005
    Assignee: Technologies and Devices International, Inc.
    Inventors: Yuri V. Melnik, Vitali Soukhoveev, Vladimir Ivantsov, Katie Tsvetkov, Vladimir A. Dmitriev
  • Patent number: 6911079
    Abstract: The resistivity of a p-doped III-V or a p-doped II-VI semiconductor material is reduced. The reduction of resistivity of the p-type III-V or a II-VI semiconductor material is achieved by applying an electric field to the semiconductor material. III-V nitride-based light emitting diodes are prepared.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: June 28, 2005
    Assignee: Kopin Corporation
    Inventors: Peter Rice, Schang-Jing Hon, Alexander Wang, Kevin O'Connor
  • Patent number: 6884291
    Abstract: An optical semiconductor device operable in a 0.6 ?m band includes an active layer of GaInNP sandwiched by a pair of GaInP layers each having a thickness of about 2 molecular layers or less.
    Type: Grant
    Filed: September 8, 1999
    Date of Patent: April 26, 2005
    Assignee: Ricoh Company, Ltd.
    Inventors: Naoto Jikutani, Shunichi Sato, Takashi Takahashi
  • Patent number: 6860939
    Abstract: Processing and systems to create, and resulting products related to, very small-dimension singular, or monolithically arrayed, semiconductor mechanical devices. Processing is laser performed on selected semiconductor material whose internal crystalline structure becomes appropriately changed to establish the desired mechanical properties for a created device.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: March 1, 2005
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: John W. Hartzell
  • Patent number: 6841274
    Abstract: The GaN single-crystal substrate 11 in accordance with the present invention has a polished surface subjected to heat treatment for at least 10 minutes at a substrate temperature of at least 1020° C. in a mixed gas atmosphere containing at least an NH3 gas. As a consequence, an atomic rearrangement is effected in the surface of the substrate 11 in which a large number of minute defects are formed by polishing, so as to flatten the surface of the substrate 11. Therefore, the surface of an epitaxial layer 12 formed on the substrate 11 can be made flat.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: January 11, 2005
    Assignees: Sumitomo Electric Industries, Ltd., Institute of Materials Research & Engineering
    Inventors: Masaki Ueno, Eiryo Takasuka, Soo-Jin Chua, Peng Chen
  • Patent number: 6703144
    Abstract: A semiconductor structure including a first substrate, and an epitaxial layer bonded to the substrate. The epitaxial layer has a threading dislocation density of less than 107 cm−2 and an in-plane lattice constant that is different from that of the first substrate and a second substrate on which the epitaxial layer is fabricated. In another embodiment, there is provided a method of processing a semiconductor structure including providing a first substrate; providing a layered structure including a second substrate having an epitaxial layer provided thereon, the epitaxial layer having an in-plane lattice constant that is different from that of the first substrate and a threading dislocation density of less than 107 cm−2; bonding the first substrate to the layered structure; and removing the second substrate.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: March 9, 2004
    Assignee: AmberWave Systems Corporation
    Inventor: Eugene A. Fitzgerald
  • Patent number: 6692568
    Abstract: A method utilizes sputter transport techniques to produce arrays or layers of self-forming, self-oriented columnar structures characterized as discrete, single-crystal Group III nitride posts or columns on various substrates. The columnar structure is formed in a single growth step, and therefore does not require processing steps for depositing, patterning, and etching growth masks. A Group III metal source vapor is produced by sputtering a target, for combination with nitrogen supplied from a nitrogen-containing source gas. The III/V ratio is adjusted or controlled to create a Group III metal-rich environment within the reaction chamber conducive to preferential column growth. The reactant vapor species are deposited on the growth surface to produce single-crystal MIIIN columns thereon. The columns can be employed as a strain-relieving platform for the growth of continuous, low defect-density, bulk materials.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: February 17, 2004
    Assignee: Kyma Technologies, Inc.
    Inventors: Jerome J. Cuomo, N. Mark Williams, Andrew David Hanser, Eric Porter Carlson, Darin Taze Thomas
  • Patent number: 6692837
    Abstract: A semi-insulating InP substrate in which a Ru-doped semi-insulating semiconductor layer is formed on the surface is provided, wherein the Ru-doped semi-insulating semiconductor layer has a complete semi-insulating property. The semiconductor optical device is fabricated by forming the Ru-doped semi-insulating semiconductor layer on a Fe-doped semi-insulating InP substrate, and forming a semiconductor crystal layer to which a p-type impurity is doped.
    Type: Grant
    Filed: May 10, 2002
    Date of Patent: February 17, 2004
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Ryuzo Iga, Matsuyuki Ogasawara, Susumu Kondo, Yasuhiro Kondo
  • Patent number: 6656615
    Abstract: The present invention refers to an ammonobasic method for preparing a gallium-containing nitride crystal, in which gallium-containing feedstock is crystallized on at least one crystallization seed in the presence of an alkali metal-containing component in a supercritical nitrogen-containing solvent. The method can provide monocrystalline gallium-containing nitride crystals having a very high quality.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: December 2, 2003
    Assignees: Nichia Corporation, Ammono Sp. z o.o.
    Inventors: Robert Tomasz Dwili&nacute;ski, Roman Marek Doradzi&nacute;ski, Jerzy Garczy&nacute;ski, Leszek Piotr Sierzputowski, Yasuo Kanbara
  • Patent number: 6623559
    Abstract: A method for producing compound semiconductor quantum particles from at least a metallic element selected from Groups IIA, IIB, IIIA, IVA, and VA of the Periodic Table and at least a non-oxygen reactant element selected from the group consisting of P, As, S, Se, and Te. The method includes: (a) operating a heating and atomizing means to provide a stream of super-heated fine-sized fluid droplets of a selected metallic element into a reaction chamber; (b) directing a stream of a reactant element-containing fluid medium into the chamber to impinge upon and react with the super-heated metal fluid droplets to form substantially nanometer-sized phosphide, arsenide, sulfide, selenide, and/or telluride compound particles; and (c) cooling and/or passivating the compound particles to form the desired compound semiconductor quantum particles. These quantum particles are particularly useful for photo luminescence and biological labeling applications.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: September 23, 2003
    Assignee: Nanotek Instruments, Inc.
    Inventor: Wen-Chiang Huang
  • Patent number: 6613162
    Abstract: The present application discloses a method for preparing a homogeneous ternary or quaternary alloy from a quaternary melt. The method includes providing a family of phase diagrams for the quaternary melt which shows (i) composition/temperature data, (ii) tie lines connecting equilibrium liquid and solid compositions, and (iii) isotherms representing boundaries of a miscibility gap. Based on the family of phase diagrams, a quaternary melt composition and an alloy growth temperature is selected. A quaternary melt having the selected quaternary melt composition is provided and a ternary or quaternary alloy is grown from the quaternary melt at the selected alloy growth temperature. A method for making homogeneous ternary or quaternary alloy from a ternary or quaternary melt is also disclosed, as are homogeneous quaternary single-crystal alloys which are substantially free from crystal defects and which have the formula AxB1−xCyD1−y, x and y being the same or different and in the range of 0.001 to 0.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: September 2, 2003
    Assignee: Rensselaer Polytechnic Institute
    Inventors: Partha S. Dutta, Thomas R. Miller
  • Publication number: 20030157376
    Abstract: A boule formed by high rate vapor phase growth of Group III-V nitride boules (ingots) on native nitride seeds, from which wafers may be derived for fabrication of microelectronic device structures. The boule is of microelectronic device quality, e.g., having a transverse dimension greater than 1 centimeter, a length greater than 1 millimeter, and a top surface defect density of less than 107 defects cm−2. The Group III-V nitride boule may be formed by growing a Group III-V nitride material on a corresponding native Group III-V nitride seed crystal by vapor phase epitaxy at a growth rate above 20 micrometers per hour.
    Type: Application
    Filed: February 19, 2003
    Publication date: August 21, 2003
    Inventors: Robert P. Vaudo, Jeffrey S. Flynn, George R. Brandes, Joan M. Redwing, Michael A. Tischler
  • Patent number: 6602613
    Abstract: A semiconductor structure including a first substrate, and an epitaxial layer bonded to the substrate. The epitaxial layer has a threading dislocation density of less than 107 cm−2 and an in-plane lattice constant that is different from that of the first substrate and a second substrate on which the epitaxial layer is fabricated. In another embodiment, there is provided a method of processing a semiconductor structure including providing a first substrate; providing a layered structure including a second substrate having an epitaxial layer provided thereon, the epitaxial layer having an in-plane lattice constant that is different from that of the first substrate and a threading dislocation density of less than 107 cm−2; bonding the first substrate to the layered structure; and removing the second substrate.
    Type: Grant
    Filed: January 17, 2001
    Date of Patent: August 5, 2003
    Assignee: AmberWave Systems Corporation
    Inventor: Eugene A. Fitzgerald
  • Patent number: 6468347
    Abstract: A GaN single crystal is grown by synthesizing GaN in vapor phase, piling a GaN crystal on a substrate, producing a three-dimensional facet structure including facets in the GaN crystal without making a flat surface, maintaining the facet structure without burying the facet structure, and reducing dislocations in the growing GaN crystal. The facet structure reduces the EPD down to less than 106 cm−2.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: October 22, 2002
    Assignee: Sumitomo Electric Industries Ltd.
    Inventors: Kensaku Motoki, Takuji Okahisa, Naoki Matsumoto
  • Patent number: 6440212
    Abstract: A process of making thermoelectric coolers by direct printing of n- and p-type semiconductor materials suitable for making thermoelectric coolers is disclosed. Micro Jet Printing of arrays on n and p-type materials belong to conductive site pads on non-conductive substrate and crystalization of these materials in the preferred direction as they cool produces thermoelectric cooler components without the need for sawing and machining operations. A non-conductive top substrate having conductive bonding pads is secured to the tops of the columns n and p-type semiconductor materials thereby forming an electrical and physical bond to make a thermoelectric cooler package.
    Type: Grant
    Filed: February 27, 2001
    Date of Patent: August 27, 2002
    Assignee: MicroFab Technologies, Inc.
    Inventor: Donald J. Hayes
  • Patent number: 6375739
    Abstract: Apparatus for bulk vapor phase crystal growth comprising: at least one source zone and at least one sink zone each associated with means for independent temperature control within the zone; and at least one passage means adapted for transport of vapor from source to sink zone; and additionally comprising means for in-situ monitoring of the sink zone; wherein means for monitoring is substantially non-intrusive in terms of temperature regulation within the sink zone; process for bulk vapor phase crystal growth employing the apparatus; method for starting up the process; method for controlling the process; use for any bulk vapor transport technique; equipment for monitoring growth using the apparatus or process; and crystal grown with the apparatus or process.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: April 23, 2002
    Assignee: University of Durham
    Inventor: John Tomlinson Mullins
  • Patent number: 6231668
    Abstract: A method for manufacturing and calibrating a scale in the nanometer range for technical devices which are used for the high-resolution or ultrahigh-resolution imaging of structures, and such a scale. To construct the scale, at least two different crystalline or amorphous materials are used, which, when imaged, are easily distinguished from one another by their contrast. These material layers are deposited using a suitable material deposition method as a heterolayer sequence onto a substrate material. The produced heterolayer sequence is characterized experimentally using an analysis method that is sensitive to the individual layer thicknesses of the heterolayer sequence. The data obtained from the analysis method are evaluated and recorded. The layer structure is exposed by splitting open the heterolayer sequence in the deposition direction.
    Type: Grant
    Filed: February 6, 1997
    Date of Patent: May 15, 2001
    Assignee: Deutsche Telekom AG
    Inventors: Rainer Loesch, Hartmut Hillmer, Winfried Schlapp, Armin Poecker, Walter Betz, Rainer Goebel
  • Patent number: 6179912
    Abstract: Provided is a system and continuous flow process for producing monodisperse semiconductor nanocrystals comprising reservoirs for the starting materials, a mixing path in which the starting materials are mixed, a first reactor in which the mixture of starting materials is mixed with a coordinating solvent and in which nucleation of particles occurs, a second reactor in which controlled growth of the nanocrystals occurs, and a growth termination path in which the growth of the nanocrystals is halted.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: January 30, 2001
    Assignee: BioCrystal Ltd.
    Inventors: Emilio Barbera-Guillem, Marlin O. Thurston
  • Patent number: 6107112
    Abstract: In a distributed feedback semiconductor laser includes an InP substrate and a multiple layer structure formed on a main surface of the InP substrate, the multiple layer structure includes at least an active layer for emitting laser light and a periodical structure for distributed feedback of the laser light, and the periodical structure includes a plurality of semiconductor regions each having a triangular cross section in a direction perpendicular to the main surface of the InP substrate and parallel to a cavity length of the distributed feedback semiconductor laser, the triangular cross section projecting toward the InP substrate.
    Type: Grant
    Filed: October 7, 1999
    Date of Patent: August 22, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Kito, Masato Ishino, Nobuyuki Otsuka, Yasushi Matsui, Shinji Nakamura
  • Patent number: 6099640
    Abstract: A method of promoting evaporation of excess indium from a surface of an indium containing compound semiconductor single crystal layer during a discontinuation of a molecular beam epitaxial growth. Substantial supply of all elements for the indium containing compound semiconductor single crystal layer are stopped at least until a substrate temperature rises to a predetermined temperature of not less than an indium re-evaporation initiation temperature.
    Type: Grant
    Filed: September 3, 1998
    Date of Patent: August 8, 2000
    Assignee: NEC Corporation
    Inventor: Hitoshi Negishi
  • Patent number: 6036773
    Abstract: A Group III atomic layer required for fabrication of a semiconductor quantum nanostructure is grown to be properly restricted to a monolayer.A substrate is configured to have a fast-growth surface portion where growth of a Ga atomic layer proceeds at a relatively high rate and a slow-growth surface portion where the growth of the Ga atomic layer proceeds at a relatively low rate. Ga atoms are supplied to the fast-growth surface portion in an amount not less than that which grows one layer of the Group III atoms. Excess Ga atoms on the fast-growth surface portion are allowed to migrate to the slow-growth surface portion by surface migration, thereby growing only one layer of the Ga atoms on the fast-growth surface portion.
    Type: Grant
    Filed: March 27, 1997
    Date of Patent: March 14, 2000
    Assignee: Agency of Industrial Science & Technology, Ministry of International Trade & Industry
    Inventors: Xue-Lun Wang, Mutsuo Ogura
  • Patent number: 6036769
    Abstract: An indium phosphate semiconductor substrate is prepared for subsequent growth of epitaxial layers to form a semiconductor device. In the preparation, the substrate is first annealed to promote any tendency for surface accumulation of impurity atoms by diffusion from the substrate and to promote impurity atom removal from the surface of the substrate. The substrate is then surface etched to remove further impurities and to provide a clean, flat surface for subsequent epitaxial layer growth. The final stage of preparation involves growing a semi-insulating buffer layer on the substrate to isolate the device epitaxial layers from the substrate.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: March 14, 2000
    Assignee: British Telecommunications Public Limited Company
    Inventors: Paul C. Spurdens, Mark A. Salter, Michael J. Harlow, David J. Newson
  • Patent number: 6007622
    Abstract: A method is provided for preparing, with high reproducibility, a carbon-doped group III-V compound semiconductor crystal having favorable electrical characteristics and having impurities removed therefrom, and in which the amount of doped carbon can be adjusted easily during crystal growth. This method includes the steps of: filling a crucible with compound raw material, solid carbon, and boron oxide; sealing the filled crucible gas impermeable material; heating and melting the compound raw material under the sealed state in the airtight vessel; and solidifying the melted compound raw material to grow a carbon-doped compound semiconductor crystal.
    Type: Grant
    Filed: April 25, 1997
    Date of Patent: December 28, 1999
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tomohiro Kawase, Masami Tatsumi
  • Patent number: 5985023
    Abstract: While a nitrogen-doped gallium phosphide epitaxial layer in an epitaxial wafer as a material of light-emitting diodes is desired to have a high concentration of nitrogen in order to enhance the efficiency of light emission, the present invention provides a reliable and efficient means to accomplish a high nitrogen concentration by the increase of the concentration of ammonia as a nitrogen source in the doping atmosphere to the contrary to the general understanding that increase of the ammonia concentration to exceed a limit rather has an effect of decreasing the concentration of nitrogen doped in the epitaxial layer. The inventive method is based on the discovery that an exponential relationship is held between the growth rate of the epitaxial layer and the concentration of nitrogen in the thus grown epitaxial layer.
    Type: Grant
    Filed: March 22, 1996
    Date of Patent: November 16, 1999
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Susumu Higuchi, Masato Yamada, Munehisa Yanagisawa
  • Patent number: 5980632
    Abstract: A process for producing a Group III--V compound semiconductor represented by the general formula In.sub.x Ga.sub.y Al.sub.z N (provided that x+y+z=1, 0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, and 0.ltoreq.z.ltoreq.1) employs a support member for forming the semiconductor, wherein the member constitutes SiC which is obtained by converting a graphite base material into SiC. In another embodiment, the member comprises a graphite-SiC composite wherein at least a surface layer part of a graphite substrate is converted into SiC. The member of the invention has superior chemical and mechanical stability, thereby making it useful in high-productivity production devices for making compound semiconductors.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: November 9, 1999
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Yasushi Iyechika, Toshihisa Katamime, Yoshinobu Ono, Tomoyuki Takada
  • Patent number: 5888294
    Abstract: An improved epitaxial growth rate varying method for a side surface of a semiconductor pattern capable of controlling a growth rate of a side surface of a semiconductor pattern by controlling the amount of CCl.sub.4 gas supplied when forming an epitaxial layer on a patterned GaAs substrate in a metalorganic chemical deposition method, thus fabricating a desired quantum wire, and which is characterized by controlling a side-surface growth rate of an epitaxial layer in accordance with the CCl.sub.4 doping gas flow rate while an epitaxial layer is formed on a patterned GaAs substrate in a metalorganic chemical deposition method and in achieving a desired substantial flatness.
    Type: Grant
    Filed: March 1, 1996
    Date of Patent: March 30, 1999
    Assignee: Korea Institute of Science and Technology
    Inventors: Suk-Ki Min, Moo Sung Kim, Yong Kim
  • Patent number: 5888296
    Abstract: A layered bismuth ferroelectric structure (12) and a method for forming the bismuth layered ferroelectric structure (12). A monolayer (12A) of bismuth is formed in intimate contact with a single crystalline semiconductor material (11). A layered ferroelectric material (12) is grown on the monolayer (12A) of bismuth such that the monolayer (12A) of bismuth becomes a part of the layered ferroelectric material (12). The ferroelectric material (12) forms a layered ferroelectric material which is not a pure perovskite, wherein the crystalline structure at the interface between the single crystalline semiconductor material (11) and the monolayer (12A) of bismuth are substantially the same.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: March 30, 1999
    Assignee: Motorola, Inc.
    Inventors: William J. Ooms, Daniel S. Marshall, Jerald A. Hallmark
  • Patent number: 5855669
    Abstract: A grating coupler is formed by growing an optical waveguide layer on a substrate by an epitaxial growing process such as a metalorganic chemical vapor deposition and a molecular beam deposition. The optical waveguide layer has a surface on which a cross-hatch pattern serving as the grating is continuously formed. The optical waveguide layer is formed with a material having a reflective index greater than a reflective index of the substrate or an atmosphere. Specifically, the substrate is formed with GaAs and the optical waveguide layer is formed with InGaAs. Further, the substrate is an on-substrate having an orientation coinciding with a ?100! plane, so as to form the optical waveguide layer having continuous cross-hatch patterns on the surface thereof. The spacing between the cross-hatch patterns can be varied according to variation of a growth temperature of the optical waveguide layer.
    Type: Grant
    Filed: April 17, 1997
    Date of Patent: January 5, 1999
    Assignee: Electronics And Telecommunications Research Institute
    Inventors: Jong-Hyeob Baek, Bun Lee
  • Patent number: 5824151
    Abstract: The method of forming a III-V group compound semiconductor crystalline layer on a semiconductor crystal containing at least V-group compound, includes the steps of: performing the crystal growth of the III-V compound semiconductor crystalline layer; and supplying an n-type dopant and a material compound containing a V-group element onto the semiconductor crystal without causing the crystal growth of the III-V compound semiconductor crystalline layer.
    Type: Grant
    Filed: May 21, 1997
    Date of Patent: October 20, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Nobuhiro Ohkubo
  • Patent number: RE39778
    Abstract: A method is provided for preparing, with high reproducibility, a carbon-doped group III-V compound semiconductor crystal having favorable electrical characteristics and having impurities removed therefrom, and in which the amount of doped carbon can be adjusted easily during crystal growth. This method includes the steps of: filling a crucible with compound raw material, solid carbon, and boron oxide; sealing the filled crucible within an airtight vessel formed of a gas impermeable material; heating and melting the compound raw material under the sealed state in the airtight vessel; and solidifying the melted compound raw material to grow a carbon-doped compound semiconductor crystal.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: August 21, 2007
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tomohiro Kawase, Masami Tatsumi
  • Patent number: RE41551
    Abstract: A method is provided for preparing, with high reproducibility, a carbon-doped group III-V compound semiconductor crystal having favorable electrical characteristics and having impurities removed therefrom, and in which the amount of doped carbon can be adjusted easily during crystal growth. This method includes the steps of: filling a crucible with compound raw material, solid carbon, and boron oxide; sealing the filled crucible gas impermeable material; heating and melting the compound raw material under the sealed state in the airtight vessel; and solidifying the melted compound raw material to grow a carbon-doped compound semiconductor crystal.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: August 24, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tomohiro Kawase, Masami Tatsumi