{zn,cd,hg}{s,se,te} Compound Containing {c30b 29/46} Patents (Class 117/956)
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Patent number: 11215757Abstract: A spot size converter includes a first waveguide including a first core layer, the first waveguide propagating light; and a second waveguide including a second core layer and provided on the first waveguide, the second waveguide propagating light. The first waveguide and the second waveguide extend in a waveguide direction. A first region and a second region are provided continuously along the waveguide direction. In the first region, the second waveguide has a tapered shape in a cross section which becomes narrower as going up away from the first waveguide. An angle between a side surface of the second waveguide and a bottom surface of the second waveguide is 60° or less.Type: GrantFiled: July 15, 2020Date of Patent: January 4, 2022Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Masataka Watanabe, Hajime Tanaka
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Patent number: 9812844Abstract: An edge-emitting semiconductor laser includes a semiconductor structure having a waveguide layer with an active layer, the waveguide layer extending in a longitudinal direction between first and second side facets of the semiconductor structure, the semiconductor structure has a tapering region adjacent to the first side facet, a thickness of the waveguide layer in the tapering region increases longitudinally, the waveguide layer is arranged between first and second cladding layers, a thickness of the second cladding layer in the tapering region of the semiconductor structure increases longitudinally, the tapering region includes first and second subregions, the first subregion is arranged closer to the first side facet than the second subregion, thickness of the waveguide layer increases longitudinally in the first subregion, thickness of the waveguide layer is constant in the longitudinal direction in the second subregion, and thickness of the second cladding layer increases longitudinally in the second subType: GrantFiled: June 17, 2014Date of Patent: November 7, 2017Assignee: OSRAM Opto Semiconductors GmbHInventors: Alvaro Gomez-Iglesias, Harald König, Christian Lauer
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Patent number: 9755402Abstract: Semiconductor laser device with mirror protection includes transversally a structure with a double waveguide, consisting of an active waveguide and a separated or adjacent trapping waveguide, and longitudinally a main segment and end segments, the thickness of the upper cladding of the end segments being gradually decreased toward the mirrors. In the main segment, the field distribution is asymmetric, preponderantly located in the lower cladding. In the end segments, the field distribution gradually further shifts toward the lower cladding. Along the end segments, the fundamental mode confinement factor ? is gradually and substantially reduced. The reduction of the confinement factor ? protects against degradation the projection of the active region on the exit mirrors, the laser element most sensitive to degradation.Type: GrantFiled: June 5, 2015Date of Patent: September 5, 2017Inventor: Iulian Basarab Petrescu-Prahova
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Patent number: 8986446Abstract: This invention provides an Si doped GaAs single crystal ingot, which has a low crystallinity value as measured in terms of etch pit density (EPD) per unit area and has good crystallinity, and a process for producing the same. An Si-doped GaAs single crystal wafer produced in a latter half part in the growth of the Si doped GaAs single crystal ingot is also provided. A GaAs compound material is synthesized in a separate synthesizing oven (a crucible). An Si dopant is inserted into the compound material to prepare a GaAs compound material with the Si dopant included therein. The position of insertion of the Si dopant is one where, when the GaAs compound material is melted, the temperature is below the average temperature. After a seed crystal is inserted into a crucible for an apparatus for single crystal growth, the GaAs compound material with the Si dopant included therein and a liquid sealing compound are introduced into the crucible.Type: GrantFiled: October 25, 2010Date of Patent: March 24, 2015Assignee: Dowa Electronics Materials Co., Ltd.Inventor: Yoshikazu Oshika
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Patent number: 8968469Abstract: A structure including a substrate, an intermediate layer provided and formed directly onto the substrate, a transition region, and a group II-VI bulk crystal material provided and formed as an extension of the transition region. The transition region acts to change the structure from the underlying substrate to that of the bulk crystal. In a method of manufacture, a similar technique can be used for growing the transition region and the bulk crystal layer.Type: GrantFiled: October 11, 2010Date of Patent: March 3, 2015Assignee: Kromek LimitedInventors: Arnab Basu, Max Robinson, Ben Cantwell, Andy Brinkman
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Patent number: 8834628Abstract: A method is described for the manufacture of semiconductor nanoparticles. Improved yields are obtained by use of a reducing agent or oxygen reaction promoter.Type: GrantFiled: December 23, 2009Date of Patent: September 16, 2014Assignee: Life Technologies CorporationInventors: Donald A. Zehnder, Joseph Treadway
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Patent number: 8568531Abstract: A seed holder for use in a crystal growth reactor. The seed holder has a drool and a washer of outer diameter substantially the same as the drool inner diameter. A main body is disposed over the washer and drool, forming an enclosure above the washer and drool, the enclosure forming a cavity above the washer and drool.Type: GrantFiled: July 27, 2007Date of Patent: October 29, 2013Assignee: Pronomic Industry ABInventors: Olof Claes Erik Kordina, Shailaja Rao, Joshua R. Christie
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Patent number: 8409348Abstract: A production method of a zinc oxide single crystal, comprising depositing a crystal of zinc oxide on a seed crystal from a mixed melt of zinc oxide and a solvent capable of melting zinc oxide and having a higher average density than zinc oxide in the melt. Preferably, a zinc oxide single crystal is continuously pulled while supplying the same amount of a zinc oxide raw material as that of the pulled zinc oxide. A single crystal excellent in the crystal quality and long in the pulling direction can be continuously produced.Type: GrantFiled: March 14, 2008Date of Patent: April 2, 2013Assignee: Ube Industries, Ltd.Inventors: Yoshizumi Tanaka, Itsuhiro Fujii
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Patent number: 7875957Abstract: Provided is a semiconductor substrate for epitaxial growth which does not require any etching treatment as a pretreatment in the stage of performing an epitaxial growth of HgCdTe film. A CdTe system compound semiconductor substrate for the epitaxial growth of the HgCdTe film is housed in an inactive gas atmosphere, in a predetermined period of time (for example, 10 hours) after mirror finish treatment thereof, to thereby regulate the proportion of Te oxide of the total amount of Te on the substrate surface which is obtained by XPS measurement so as to be not more than 30%.Type: GrantFiled: August 17, 2007Date of Patent: January 25, 2011Assignee: Nippon Mining & Metals Co., Ltd.Inventors: Kenji Suzuki, Ryuichi Hirano, Hideki Kurita
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Patent number: 7829207Abstract: A manufacture method that can manufacture ZnO based compound semiconductor crystal of good quality. A ZnO substrate is prepared to have a principal surface made of a plurality of terraces of (0001) planes arranged stepwise along an m-axis direction, the envelop of the principal surface being inclined relative to the (0001) plane by about 2 degrees or less. ZnO based compound semiconductor crystal is grown on the principal surface.Type: GrantFiled: September 27, 2008Date of Patent: November 9, 2010Assignees: Stanley Electric Co., Ltd., Tokyo Denpa Co., Ltd., Tohoku UniversityInventors: Hiroyuki Kato, Michihiro Sano, Katsumi Maeda, Hiroshi Yoneyama, Takafumi Yao, Meoung Whan Cho
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Patent number: 7777303Abstract: The invention described herein provides for thin films and methods of making comprising inorganic semiconductor-nanocrystals dispersed in semiconducting-polymers in high loading amounts. The invention also describes photovoltaic devices incorporating the thin films.Type: GrantFiled: March 18, 2003Date of Patent: August 17, 2010Assignee: The Regents of The University of CaliforniaInventors: A. Paul Alivisatos, Janke J. Dittmer, Wendy U. Huynh, Delia Milliron
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Patent number: 7544343Abstract: It is to define the resistivity and the contained amount of impurities of a CdTe system compound semiconductor single crystal and to provide a CdTe system compound semiconductor single crystal which is useful as a substrate for optical devices such as an infrared sensor and the like. In a CdTe system compound semiconductor single crystal for an optical device, a Group 1 (1A) element is included in a range of 5×1014 to 6×1015 cm?3 in the crystal, a total amount of a Group 13 (3B) element and a Group 17 (7B) element included in the crystal is less than 2×1015 cm?3 and less than a total amount of the Group 1 (1A) element, and resistivity of the crystal is in a range of 10 to 104 ?cm.Type: GrantFiled: November 16, 2005Date of Patent: June 9, 2009Assignee: Nippon Mining & Metals Co., Ltd.Inventors: Atsutoshi Arakawa, Ryuichi Hirano
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Patent number: 7465352Abstract: A method of homogeneously forming metal chalcogenide nanocrystals includes the steps combining a metal source, a chalcogenide source, and at least one solvent at a first temperature to form a liquid comprising assembly, and heating the assembly at a sufficient temperature to initiate nucleation to form a plurality of metal chalcogenide nanocrystals. The plurality of metal chalcogenide nanocrystals are then grown without injection of either the metal source or the chalcogenide source at a temperature at least equal to the sufficient temperature, wherein growth proceeds substantially without nucleation to form a plurality of monodisperse metal chalcogenide nanocrystals. An optional nucleation initiator can help control the final size of the monodisperse crystals. Such synthesis, without the need for precursor injection, is suitable for the industrial preparation of high-quality nanocrystals.Type: GrantFiled: July 25, 2005Date of Patent: December 16, 2008Assignee: University of Florida Research Foundation, Inc.Inventor: Yunwei Charles Cao
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Patent number: 7303632Abstract: A vapor transport growth process for bulk growth of high quality gallium nitride for semiconductor applications is disclosed. The method includes the steps of heating a gallium nitride source material, a substrate suitable for epitaxial growth of GaN thereon, ammonia, a transporting agent that will react with GaN to form gallium-containing compositions, and a carrier gas to a temperature sufficient for the transporting agent to form volatile Ga-containing compositions from the gallium nitride source material. The method is characterized by maintaining the temperature of the substrate sufficiently lower than the temperature of the source material to encourage the volatile gallium-containing compositions to preferentially form GaN on the substrate.Type: GrantFiled: May 26, 2004Date of Patent: December 4, 2007Assignee: Cree, Inc.Inventor: Gerald H. Negley
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Patent number: 7261775Abstract: A method of growing a group III nitride crystal grows a group III nitride crystal from a solution in which an alkaline metal, a group III metal and nitrogen are dissolved, and includes, in the solution, a material which increases solubility of the nitrogen into the solution.Type: GrantFiled: January 28, 2004Date of Patent: August 28, 2007Assignee: Ricoh Company, Ltd.Inventors: Hirokazu Iwata, Seiji Sarayama, Hisanori Yamane, Masahiko Shimada, Masato Aoki
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Patent number: 7255742Abstract: The present invention provides a method of manufacturing Group III nitride crystals that are of high quality, are manufactured efficiently, and are useful and usable as a substrate for semiconductor manufacturing processes. A semiconductor layer that is made of a semiconductor and includes crystal-nucleus generation regions at its surface is formed. The semiconductor is expressed by a composition formula of AluGavIn1-u-vN (where 0?u?1, 0?v?1, and u+v?1). Group III nitride crystals then are grown on the semiconductor layer by bringing the crystal-nucleus generation regions of the semiconductor layer into contact with a melt in an atmosphere including nitrogen. The melt contains nitrogen, at least one Group III element selected from the group consisting of gallium, aluminum, and indium, and at least one of alkali metal and alkaline-earth metal.Type: GrantFiled: July 2, 2004Date of Patent: August 14, 2007Assignees: Matsushita Electric Industrial Co., Ltd.Inventors: Yasuo Kitaoka, Hisashi Minemoto, Isao Kidoguchi, Takatomo Sasaki, Yusuke Mori, Fumio Kawamura
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Patent number: 7211142Abstract: A CdTe single crystal, wherein chlorine concentration in the crystal is between 0.1 and 5.0 ppmwt and resistivity at room temperature is not less than 1.0×109 ?·cm is obtained by growing the crystal according to one of a vertical gradient freezing method, a horizontal gradient freezing method, a vertical Bridgman method, a horizontal Bridgman method, and a liquid encapsulated Czochralski method by using a CdTe polycrystal, in which 50 to 200 ppmwt of chlorine is doped, as a raw material.Type: GrantFiled: November 29, 2002Date of Patent: May 1, 2007Assignee: Nippon Mining & Metals Co., Ltd.Inventor: Ryuichi Hirano
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Patent number: 7175707Abstract: A p-type GaAs single crystal containing Si, Zn, B and In as dopants has an average dislocation density of 100 cm?2 or less. It may be produced by cooling a GaAs melt containing Si, Zn, B and In as dopants in a crystal-growing container having a seed crystal placed at a lower end thereof in an upward increasing temperature gradient, to cause a single crystal to grow upward from the seed crystal.Type: GrantFiled: March 24, 2003Date of Patent: February 13, 2007Assignee: Hitachi Cable Ltd.Inventors: Kenya Itani, Masaya Ohnishi, Shinji Komata, Seiji Mizuniwa
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Patent number: 7147712Abstract: A method is described for the manufacture of semiconductor nanoparticles. Improved yields are obtained by use of a reducing agent or oxygen reaction promoter.Type: GrantFiled: October 1, 2002Date of Patent: December 12, 2006Assignee: Invitrogen CorporationInventors: Donald A. Zehnder, Joseph A. Treadway
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Patent number: 7144458Abstract: Nanocrystals are synthesized with a high degree of control over reaction conditions and hence product quality in a flow-through reactor in which the reaction conditions are maintained by on-line detection of characteristic properties of the product and by adjusting the reaction conditions accordingly. The coating of nanocrystals is achieved in an analogous manner.Type: GrantFiled: December 2, 2003Date of Patent: December 5, 2006Assignee: Invitrogen CorporationInventors: Donald A. Zehnder, Marcel P. Bruchez, Joseph A. Treadway, Jonathan P. Earhart
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Patent number: 7022182Abstract: The present invention provides a single-crystal ZnO thin film having a high ferromagnetic transition temperature. In one aspect of the present invention, the ZnO thin film comprises a ferromagnetic p-type single-crystal zinc oxide including a transition metal element consisting of Mn, and a p-type dopant. In another aspect of the present invention, the thin film comprises a ferromagnetic p-type single-crystal zinc oxide including a transition metal element consisting of Mn, a p-type dopant, and an n-type dopant. The single-crystal zinc oxide material can be applied to quantum computers and high-capacity magnetic-optical recording medium by combining with conventional n-type or p-type transparent electrode ZnO materials or optical fibers, and to powerful information-communication devices or quantum computers as a photoelectric material usable for a wide range from visible light to ultraviolet light.Type: GrantFiled: July 3, 2000Date of Patent: April 4, 2006Assignee: Japan Science and Technology AgencyInventors: Hiroshi Yoshida, Kazunori Sato
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Patent number: 7014702Abstract: A heat treatment chamber (30) is provided comprising a treatment region containing a charge (5) of compound material comprising a plurality of n atomic species, each atomic species being associated with at least one gas species. The chamber (30) is placed in a furnace (7). The chamber has a gas permeable barrier, constituted by a plug (4) and wadding (6), which partially encloses the treatment region. The barrier serves as an effusive hole to inhibit, but not prevent, gas vapour release, thereby to elevate the gas vapour pressure in the treatment region. Application of inert gas through a valve (8) is also used to increase background pressure in the treatment region during heat treatment. The elevated gas pressures present in the treatment region during treatment are measurable in an absorption cell (3) adjacent to the treatment region. It is thus possible to monitor the gas pressures during heat treatment and thereby stop the heat treatment once a desired charge stoichiometry is achieved.Type: GrantFiled: May 30, 2001Date of Patent: March 21, 2006Assignee: Pirelli Cavi e Sistemi S.p.A.Inventors: Andrea Zappettini, Lucio Zanotti, Mingzheng Zha, Francesco Bissoli
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Patent number: 6911079Abstract: The resistivity of a p-doped III-V or a p-doped II-VI semiconductor material is reduced. The reduction of resistivity of the p-type III-V or a II-VI semiconductor material is achieved by applying an electric field to the semiconductor material. III-V nitride-based light emitting diodes are prepared.Type: GrantFiled: April 19, 2002Date of Patent: June 28, 2005Assignee: Kopin CorporationInventors: Peter Rice, Schang-Jing Hon, Alexander Wang, Kevin O'Connor
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Patent number: 6884291Abstract: An optical semiconductor device operable in a 0.6 ?m band includes an active layer of GaInNP sandwiched by a pair of GaInP layers each having a thickness of about 2 molecular layers or less.Type: GrantFiled: September 8, 1999Date of Patent: April 26, 2005Assignee: Ricoh Company, Ltd.Inventors: Naoto Jikutani, Shunichi Sato, Takashi Takahashi
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Patent number: 6800135Abstract: A ZnO/sapphire substrate includes an R-plane sapphire substrate whose (0 1-1 2) planes are parallel to the surface thereof and a ZnO epitaxial film formed on the R-plane sapphire substrate. The (1 1-2 0) planes of the ZnO epitaxial film are disposed with an interplanar spacing in the range of about 1.623 to 1.627 Å parallel to the (0 1-1 2) planes of the R-plane sapphire substrate.Type: GrantFiled: June 17, 2002Date of Patent: October 5, 2004Assignee: Murata Manufacturing Co., Ltd.Inventors: Jun Koike, Hideharu Ieki
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Patent number: 6682596Abstract: Nanocrystals are synthesized with a high degree of control over reaction conditions and hence product quality in a flow-through reactor in which the reaction conditions are maintained by on-line detection of characteristic properties of the product and by adjusting the reaction conditions accordingly. The coating of nanocrystals is achieved in an analogous manner.Type: GrantFiled: December 26, 2001Date of Patent: January 27, 2004Assignee: Quantum Dot CorporationInventors: Donald A. Zehnder, Marcel P. Bruchez, Joseph A. Treadway, Jonathan P. Earhart
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Publication number: 20030213428Abstract: In the present invention, there are provided self-assembled ZnO nanotips grown on relatively low temperatures on various substrates by metalorganic chemical vapor deposition (MOCVD). The ZnO nanotips are made at relatively low temperatures, giving ZnO a unique advantage over other wide bandgap semiconductors such as GaN and SiC. The nanotips have controlled uniform size, distribution and orientation. These ZnO nanotips are of single crystal quality, show n-type conductivity and have good optical properties. Selective growth of ZnO nanotips also has been realized on patterned (100) silicon on r-sapphire (SOS), and amorphous SiO2 on r-sapphire substrates. Self-assembled ZnO nanotips can also be selectively grown on patterned layers or islands made of a semiconductor, an insulator or a metal deposited on R-plane (01{overscore (1)}2) Al2O3 substrates as long as the ZnO grows in a columnar stucture along the c-axis [0001] of ZnO on these materials.Type: ApplicationFiled: September 13, 2002Publication date: November 20, 2003Applicant: Rutgers, The State University of New JerseyInventors: Yicheng Lu, Sriram Muthukumar, Nuri William Emanetoglu
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Patent number: 6599362Abstract: A process of growing a material on a substrate, particularly growing a Group II-VI or Group III-V material, by a vapor-phase growth technique where the growth process eliminates the need for utilization of a mask or removal of the substrate from the reactor at any time during the processing. A nucleation layer is first grown upon which a middle layer is grown to provide surfaces for subsequent lateral cantilever growth. The lateral growth rate is controlled by altering the reactor temperature, pressure, reactant concentrations or reactant flow rates. Semiconductor materials, such as GaN, can be produced with dislocation densities less than 107/cm2.Type: GrantFiled: January 3, 2001Date of Patent: July 29, 2003Assignee: Sandia CorporationInventors: Carol I. Ashby, David M. Follstaedt, Christine C. Mitchell, Jung Han
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Patent number: 6440214Abstract: A method of growing a nitride semiconductor layer, such as a GaN layer, by molecular beam epitaxy comprises the step of growing a GaAlN nucleation layer on a substrate by molecular beam epitaxy. The nucleation layer is annealed, and a nitride semiconductor layer is then grown over the nucleation layer by molecular beam epitaxy. The nitride semiconductor layer is grown at a V/III molar ratio of 100 or greater, and this enables a high substrate temperature to be used so that a good quality semiconductor layer is obtained. Ammonia gas is supplied during the growth process, to provide the nitrogen required for the MBE growth process.Type: GrantFiled: June 9, 2000Date of Patent: August 27, 2002Assignee: Sharp Kabushiki KaishaInventors: Stewart Edward Hooper, Jennifer Mary Barnes, Jonathan Heffernan, Alistair Henderson Kean
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Patent number: 6325849Abstract: Disclosed are a P-type GaAs single crystal having an average dislocation density of 500 cm−2 or lower, and a manufacturing method therefor. The P-type GaAs single crystal is characterized by containing, as dopants, Si at an atomic concentration of from 1×1017 to 1×1019 cm−3 and Zn at an atomic concentration of from 2×1018 to 6×1019 cm−3. Further, as another example, B is contained at an atomic concentration of from 1×1017 to 1×1020 cm−3.Type: GrantFiled: July 7, 1999Date of Patent: December 4, 2001Assignee: Mitsubishi Chemical CorporationInventors: Fujisawa Hideo, Katano Kizuku, Yamamoto Osamu
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Patent number: 6299680Abstract: An object of the present invention is to reduce the etch pit density (EPD) and the full-width-half-maximum (FWHM) value of the double crystal X-ray rocking curve, and to provide a CdTe crystal or a CdZnTe crystal which does not include deposits having Cd or Te and the process for producing the same. After a CdTe crystal or a CdZnTe crystal was grown, while the temperature of the crystal is from 700 to 1050° C., the Cd pressure is adjusted so as to keep the stoichiometry of the crystal at the above temperature. The crystal is left for time t which is determined so that each of a diameter L(r) of the crystal and a length L(z) thereof satisfies the following equation 1: {L(r),(L(z))}/2<{4exp(−1.15/kT)×t}½. Then, when the crystal is cooled, the temperature of the crystal is decreased within a range in which the temperature of the crystal and that of a Cd reservoir satisfy the following equation 2: −288+1.68×TCd<TCdTe<402+0.76×TCd.Type: GrantFiled: January 6, 2000Date of Patent: October 9, 2001Assignee: Japan Energy CorporationInventors: Akio Koyama, Ryuichi Hirano
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Patent number: 6290774Abstract: A method for forming a relatively thick epitaxial film of a III-V compound on a non-native substrate involves sequentially forming a plurality of epitaxial layers on the substrate at a growth temperature. By cooling the substrate and each sequentially grown epitaxial layer to a sub-growth temperature prior to resumption of epitaxial growth, stress within the sample (due to thermal mismatch between the substrate and the epitaxial layer) is periodically relieved. Sequential epitaxial growth is combined with system etching to provide an epitaxial layer which not only has a lower propensity to shatter, but also exhibits improved surface morphology. Sequential hydride vapor-phase epitaxy using HCl as both source gas and etchant, allows integration of sequential deposition and system etching into a single process.Type: GrantFiled: May 7, 1999Date of Patent: September 18, 2001Assignees: CBL Technology, Inc., Matsushita Electric Industrial Co., Ltd.Inventors: Glenn S. Solomon, David J. Miller, Tetsuzo Ueda
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Patent number: 6241819Abstract: Doped semiconductor nanoparticles of a size (<100 Å) which exhibit quantum effects. The nanoparticles are grown and doped within a polymer matrix.Type: GrantFiled: April 20, 1993Date of Patent: June 5, 2001Assignee: North American Philips Corp.Inventors: Rameshwar Bhargava, Dennis Gallagher
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Patent number: 6139631Abstract: A crystal growth method having the steps of: preparing a growth container having a vapor generating chamber VC provided with a source material 14, a growth chamber GC provided with a seed crystal 12, and a coupling portion 18 having a cross sectional area narrower than a cross sectional area of each of the vapor generating chamber and the growth chamber, the coupling portion coupling the vapor generating chamber and the growth chamber; and vapor-phase growing a single crystal on the seed crystal by forming a temperature gradient in the growth container and by maintaining the seed crystal in the growth chamber at a growth temperature and the source material in the vapor generating chamber at a vapor supply temperature higher than the growth temperature. A crystal having a diameter larger than that of a seed crystal can be formed easily.Type: GrantFiled: August 12, 1998Date of Patent: October 31, 2000Assignee: Stanley Electric Co., Ltd.Inventor: Hiroyuki Kato
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Patent number: 6132506Abstract: An object of the present invention is to provide a method for the heat treatment of ZnSe crystal whereby the crystal can be prevented from deterioration of crystallinity and caused to have low resistivity without occurrence of precipitates in the crystal. The feature of the present invention consists in a method for the heat treatment of ZnSe comprising subjecting ZnSe crystal grown by a chemical vapor transport method using iodine as a transport agent to a heat treatment in a Zn vapor atmosphere and controlling a cooling rate after the heat treatment in 10 to 200.degree. C./min.Type: GrantFiled: June 18, 1999Date of Patent: October 17, 2000Assignee: Sumitomo Electric Industries, Ltd.Inventors: Ryu Hirota, Shinsuke Fujiwara
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Solution synthesis of mixed-metal chalcogenide nanoparticles and spray deposition of precursor films
Patent number: 6126740Abstract: A colloidal suspension comprising metal chalcogenide nanoparticles and a volatile capping agent. The colloidal suspension is made by reacting a metal salt with a chalcogenide salt in an organic solvent to precipitate a metal chalcogenide, recovering the metal chalcogenide, and admixing the metal chalcogenide with a volatile capping agent. The colloidal suspension is spray deposited onto a substrate to produce a semiconductor precursor film which is substantially free of impurities.Type: GrantFiled: January 27, 1998Date of Patent: October 3, 2000Assignee: Midwest Research InstituteInventors: Douglas L. Schulz, Calvin J. Curtis, David S. Ginley -
Patent number: 6045614Abstract: A method is provided for depositing a (111)-oriented heteroepitaxial II-VI alloy film on Si substrates. The (111)-oriented heteroepitaxial II-VI alloy film may comprise II-VI semiconductor and/or II-VI semimetal. As such, the method of the present invention provides a means for growing a (111)-oriented heteroepitaxial II-VI semiconductor film or a (111)-oriented heteroepitaxial II-VI semimetal film. The method of the present invention overcomes the inherent difficulties associated with forming (111)-oriented heteroepitaxial II-VI alloy films on Si(001). These difficulties include twin formation and poor crystalline quality. The novelty of the method of the present invention consists principally in choosing a Si substrate having a surface which has a specific Si crystallographic orientation. In particular, the present invention utilizes a Si surface having a crystallographic orientation near Si(111) rather than Si(001). The Si surface is vicinal Si(111).Type: GrantFiled: March 14, 1996Date of Patent: April 4, 2000Assignee: Raytheon CompanyInventors: Terence J. de Lyon, Scott M. Johnson
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Patent number: 6043141Abstract: A method of growing a p-type doped Group II-VI semiconductor film includes the steps of forming a lattice comprising a Group II material and a Group VI material wherein a cation-rich condition is established at a surface of the lattice. The method further includes the steps of generating an elemental Group V flux by evaporating an elemental Group V material and providing the elemental Group V flux to a Group VI sublattice of the lattice.Type: GrantFiled: November 6, 1997Date of Patent: March 28, 2000Assignee: Hughes Electronics CorporationInventors: Owen K. Wu, Rajesh D. Rajavel
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Patent number: 6036772Abstract: A method for making a semiconductor device comprises: depositing at least one Group II-VI compound semiconductor layer comprising at least one Group II element selected from the group consisting of zinc, magnesium, manganese, beryllium, cadmium and mercury and at least one Group VI element selected from the group consisting of oxygen, sulfur, selenium and tellurium onto a Group III-V compound semiconductor layer comprising at least one Group III element selected from the group consisting of gallium, aluminum, boron and indium and at least one Group V element selected from the group consisting of nitrogen, phosphorus, arsenic, antimony and bismuth; whereinbefore depositing the Group II-VI compound semiconductor layer, a particle beam composed of at least one Group II element selected from the group consisting of zinc, magnesium, beryllium, cadmium and mercury is radiated onto the Group III-V compound semiconductor layer in a dose of 8.times.10.sup.-4 Torr.multidot.sec or more.Type: GrantFiled: December 29, 1997Date of Patent: March 14, 2000Assignee: Sony CorporationInventors: Tomonori Hino, Satoshi Taniguchi, Satoshi Ito
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Patent number: 6037189Abstract: A method of fabricating an integrated waveguide device includes forming a ridge having a width that varies in a tapered shape along the [011] direction on a semiconductor substrate and growing a laminated layer structure including a light waveguide layer where the width varies in a tapered shape of the ridge so that a waveguide has a tapered shape in the laminated layer structure, thereby producing an integrated waveguide device having a tapered light waveguide. The thickness of the semiconductor layer and the wavelength guided by the waveguide are controlled with high precision and the reliability of the device is enhanced.Type: GrantFiled: October 13, 1995Date of Patent: March 14, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Katsuhiko Goto
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Patent number: 6001669Abstract: Epitaxial layers of II-VI semiconductor compounds having low incidence of lattice defects such as stacking faults are produced by first depositing a fraction of a monolayer of the cation species of the compound, followed by depositing a thin layer of the compound by migration enhanced epitaxy (MEE). Growth of the remainder of the layer by MBE results in much lower defects than if the entire layer had been grown by MBE. Layers are useful in devices such as LEDs and injection lasers.Type: GrantFiled: July 21, 1992Date of Patent: December 14, 1999Assignee: Philips Electronics North America CorporationInventors: James Matthew Gaines, John Petruzzello
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Patent number: 6001271Abstract: A composition of matter comprising a bulk material of uniform composition having first and second spaced apart surface regions and a dopant in the bulk material of progressively increasing concentration in a direction from the first to said second surface regions providing an interface intermediate the first and second surface regions wherein the portion of the bulk material on one side of the interface is electrically conductive and the portion of the bulk material on the other side of the interface is relatively electrically insulative. The bulk material is one of Ge, Si, group II-VI compounds and group III-V compounds and preferably GaAs or Gap. The dopant is a shallow donor for the bulk material involved and for GaAs and GaP is Se, Te or S. The ratio of the resistivity of the portion of the bulk material on one side of the interface to the portion of the bulk material on the other side of the interface is at least about 1:10.sup.7.Type: GrantFiled: June 7, 1995Date of Patent: December 14, 1999Assignee: Raytheon CompanyInventor: Paul Klocek
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Patent number: 5989339Abstract: A molecular beam epitaxy system having a plurality of chambers which contain at least a first chamber and a second chamber. The first chamber is used to form II-VI column compound semiconductor layers not containing Te. The second chamber is used to form II-VI column compound semiconductor layers containing at least Te. A semiconductor device having an ohmic characteristics can be fabricated without mixing Te into other layers.Type: GrantFiled: September 13, 1995Date of Patent: November 23, 1999Assignee: Sony CorporationInventors: Koshi Tamamura, Hironori Tsukamoto, Masao Ikeda
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Patent number: 5944891Abstract: An object of the present invention is to provide a method for the heat treatment of a ZnSe crystal whereby the crystal can be prevented from crystallinity deterioration and caused to have low resistivity without occurrence of precipitates in the crystal.The feature of the present invention consists in a method for the heat treatment of ZnSe comprising subjecting ZnSe crystal grown by a chemical vapor transport method using iodine as a transport agent to a heat treatment in a Zn vapor atmosphere and controlling a cooling rate after the heat treatment in 10 to 200.degree. C./min.Type: GrantFiled: August 11, 1997Date of Patent: August 31, 1999Assignee: Sumitomo Electric Industries, Ltd.Inventors: Ryu Hirota, Shinsuke Fujiwara
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Patent number: 5891243Abstract: In a process for growing a ZnSe crystal by an MBE or MOCVD process, N.sub.2 gas dissociated by electromagnetic waves and vapor In are prepared at a ratio of N:In being 2:1. The atomic gases may be prepared by decomposing InN at a high temperature with electromagnetic irradiation and adding N.sub.2 gas to the decomposed product. The atomic gases are fed onto a substrate in a crystal growth region, so as to simultaneously dope ZnSe with In and N at a ratio of 1:2. A n-type dopant In substitutionally occupying a position of Zn makes a 1:1 couple with a p-type dopant N substitutionally occupying a position of Se, and another one N atom coordinates near the atomic couple and serves as an acceptor. As a result, the acceptor is kept in activated state up to higher concentration, and the ZnSe crystal can be heavily doped with the p-type dopant N.Type: GrantFiled: August 7, 1997Date of Patent: April 6, 1999Assignee: Japan Science and Technology CorporationInventor: Hiroshi Yoshida
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Patent number: 5766345Abstract: An epitaxial growth method of semiconductor can reliably avoid irregularities from being produced when a II-VI compound semiconductor is grown epitaxially. When this method is applied to a method of manufacturing a semiconductor light-emitting device, it is possible to obtain a semiconductor light-emitting device having a long life and excellent light-emitting characteristic. When a II-VI compound semiconductor is grown epitaxially, a VI/II ratio, i.e., a supplying ratio of VI-group element and II-group element used in the epitaxial growth is selected in a range of from 1.3 to 2.5.Type: GrantFiled: October 16, 1995Date of Patent: June 16, 1998Assignee: Sony CorporationInventors: Shigetaka Tomiya, Kazushi Nakano, Satoshi Ito, Rikako Minatoya
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Patent number: 5711803Abstract: A process for the preparation of a semiconductor film. The process comprises depositing nanoparticles of a semiconductor material onto a substrate whose surface temperature during nanoparticle deposition thereon is sufficient to cause substantially simultaneous fusion of the nanoparticles to thereby coalesce with each other and effectuate film growth.Type: GrantFiled: September 29, 1995Date of Patent: January 27, 1998Assignee: Midwest Research InstituteInventors: Martin Pehnt, Douglas L. Schulz, Calvin J. Curtis, David S. Ginley
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Patent number: 5693139Abstract: A cycle of alternately or cyclically introducing external gases containing molecules of component elements of a compound semiconductor to be formed on a substrate is repeated while appropriately controlling the pressure, substrate temperature and gas introduction rate in a crystal growth vessel, so that a monocrystal which is dimensionally as precise as a single monolayer can grow on the substrate by making use of chemical reactions on the heated substrate surface.Doped molecular layer epitaxy of a compound semiconductor comprising individual steps of introducing and evacuating a first source gas, introducing and evacuating a second source gas, and introducing and evacuating an impurity gas which contains an impurity element. The doped impurity concentration varies almost linearly with the pressure during doping in a wide range.Type: GrantFiled: June 15, 1993Date of Patent: December 2, 1997Assignees: Research Development Corporation of Japan, Jun-Ichi Nishizawa, Oki Electric Company, Soubei SuzukiInventors: Junichi Nishizawa, Hitoshi Abe, Soubei Suzuki
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Patent number: 5637530Abstract: Epitaxial layers of II-VI semiconductor compounds having low incidence of lattice defects such as stacking faults are produced by first depositing a fraction of a monolayer of the cation species of the compound, followed by depositing a thin layer of the compound by migration enhanced epitaxy (MEE). Growth of the remainder of the layer by MBE results in much lower defects than if the entire layer had been grown by MBE. Layers are useful in devices such as LEDs and injection lasers.Type: GrantFiled: June 10, 1996Date of Patent: June 10, 1997Assignee: U.S. Philips CorporationInventors: James M. Gaines, John Petruzzello
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Patent number: 5616178Abstract: A method for growth of II-VI compound semiconductors grows a p-type II-VI compound semiconductor such as a p-type ZnSe by vapor deposition such as metallorganic chemical vapor deposition and molecular beam epitaxy using gaseous materials. The method uses as a p-type dopant an organic compound including at least one nitrogen atom and at least two groups of atoms each having a molecular weight larger than 12 and both combined with the nitrogen atom. One of such organic compounds is di-isopropylamine.Type: GrantFiled: May 31, 1995Date of Patent: April 1, 1997Assignee: Sony CorporationInventors: Atsushi Toda, Daisuke Imanishi