Plasma Cleaning Patents (Class 134/1.1)
  • Patent number: 11214864
    Abstract: A method for reducing metal contamination performed after dry cleaning of a process chamber used for a film deposition process and before starting the film deposition process is provided. In the method, a temperature in the process chamber is changed from a first temperature during the dry cleaning to a film deposition temperature. Hydrogen and oxygen are activated in the vacuum chamber while supplying hydrogen and oxygen into the process chamber. An inside of the process chamber is coated by performing the film deposition process without a substrate in the process chamber after the step of activating hydrogen and oxygen.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: January 4, 2022
    Assignee: Tokyo Electron Limited
    Inventor: Takahito Umehara
  • Patent number: 11211232
    Abstract: The present disclosure describes a chuck-based device and a method for cleaning a semiconductor manufacturing system. The semiconductor manufacturing system can include a chamber with the chuck-based device configured to clean the chamber, a loading port coupled to the chamber and configured to hold one or more wafer storage devices, and a control device configured to control a translational displacement and a rotation of the chuck-based device. The chuck-based device can include a based stage, one or more supporting rods disposed at the base stage and configured to be vertically extendable or retractable, and a padding film disposed on the one or more supporting rods.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ian Hsieh, Che-fu Chen, Yan-Hong Liu
  • Patent number: 11183391
    Abstract: A method for processing semiconductor wafer is provided. The method includes supplying a processing gas into an etching chamber containing a semiconductor wafer. The method also includes detecting a pressure in the etching chamber. The method further includes regulating an exhaust flow from the etching chamber by adjusting an open ratio of a valve according to a data in relation to a pressure in the etching chamber produced by the pressure sensor. In addition, the method includes determining an etching endpoint based on the open ratio of the valve.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: November 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Lee-Chuan Tseng
  • Patent number: 11158490
    Abstract: A processing apparatus performs a predetermined process on an object to be processed by supplying halogen-based gas into a chamber in which a vacuum is maintained, to which chamber a member having an oxide film formed on a surface thereof is connected, or which chamber has an oxide film formed on a surface thereof, wherein the predetermined processing is performed on the target object once or a plurality of times in the chamber. Later, oxygen gas or dry air is supplied to the chamber to purge the chamber, and then the chamber is opened and exposed to the atmosphere.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: October 26, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tomohito Matsuo, Hiroshi Nagaike
  • Patent number: 11152269
    Abstract: Provided is a plasma processing apparatus including: a plurality of gas supply nozzles which are provided on a wall surface of a processing container and supply process gas toward the inside of the processing container in a radial direction; N microwave introducing modules of which the number disposed in a circumferential direction of a ceiling plate of the processing container so as to introduce microwaves for generating plasma into the processing container, in which N?2; and M sensors provided on the wall surface of the processing container so as to monitor at least any one of electron density Ne and electron temperature Te of the plasma generated in the processing container, in which M equals to N or a multiple of N.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: October 19, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Taro Ikeda, Yuki Osada
  • Patent number: 11133450
    Abstract: A device includes a first chip having a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, a superconducting bump bond on the barrier layer, and a second chip joined to the first chip by the superconducting bump bond, the second chip having a first quantum circuit element, in which the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: September 28, 2021
    Assignee: Google LLC
    Inventors: Joshua Yousouf Mutus, Erik Anthony Lucero
  • Patent number: 11124867
    Abstract: The present invention provides a gradient material layer and a method for manufacturing the same. The gradient material layer has a base-material region, a diffusion region, and a compound region, wherein the diffusion region is located between the base-material region and the compound region. The base-material region includes a metal material. The diffusion region doped with nitrogen includes the metal material. The compound region includes metal nitride. The nitrogen content of the compound region is greater than that of the diffusion region.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: September 21, 2021
    Assignee: National Taiwan University of Science and Technology
    Inventors: Yu-Lin Kuo, Hsien-Po Wang, Jhao-Yu Guo
  • Patent number: 11121002
    Abstract: Exemplary etching methods may include flowing a halogen-containing precursor into a substrate processing region of a semiconductor processing chamber. The methods may include contacting a substrate housed in the substrate processing region with the halogen-containing precursor. The substrate may define an exposed region of a transition-metal-containing material. The methods may also include removing the transition-metal-containing material. The flowing and the contacting may be plasma-free operations.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: September 14, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Zhenjiang Cui, Hanshen Zhang, Siliang Chang, Daniella Holm
  • Patent number: 11107705
    Abstract: A cleaning solution production system is for cleaning a semiconductor substrate. The system includes a pressure tank, a plasma reaction tank configured to form a plasma in gas bubbles suspended in a decompressed liquid obtained from the pressure tank to thereby generate radical species in the decompressed liquid, a storage tank configured to store a cleaning solution containing the radical species generated in the plasma reaction tank, and a nozzle configured to supply the cleaning solution from the storage tank to a semiconductor substrate.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: August 31, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Beom Jin Yoo, Min Hyoung Kim, Sang Ki Nam, Won Hyuk Jang, Kyu Hee Han, Young Do Kim, Jeong Min Bang
  • Patent number: 11091830
    Abstract: To provide a moth-eye transfer mold and a method of manufacturing a moth-eye transfer mold that provide a simple and inexpensive manufacturing process. A moth-eye transfer mold 1 is characterized by including a base 10, an underlayer 20 formed on the base 10, and a glassy carbon layer 30 formed on the underlayer 20, the glassy carbon layer 30 has an inverted moth-eye structure RM over a surface 30a, and the inverted moth-eye structure RM is randomly arranged cone-shaped pores.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: August 17, 2021
    Assignees: Tokyo University of Science Foundation, GEOMATEC CO., LTD.
    Inventors: Jun Taniguchi, Hiroyuki Sugawara
  • Patent number: 11086215
    Abstract: A reticle and a method for manufacturing a reticle are provided. The method includes forming a reflective multilayer (ML) over a front-side surface of a mask substrate. The method further includes forming a capping layer over the reflective ML. The method further includes forming a sacrificial multilayer over the capping layer. The method further includes forming an opening in the sacrificial multilayer to expose the capping layer. The method further includes forming a first absorption layer over the sacrificial multilayer and covering the capping layer in the opening. The method further includes removing the first absorption layer outside the opening in the sacrificial multilayer to form a first absorption pattern on a portion of the capping layer.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Yue Lin, Hsin-Chang Lee
  • Patent number: 11062912
    Abstract: A process for etching a film layer on a semiconductor wafer is disclosed. The process is particularly well suited to etching carbon containing layers, such as hardmask layers, photoresist layers, and other low dielectric films. In accordance with the present disclosure, a reactive species generated from a plasma is contacted with a surface of the film layer. Simultaneously, the substrate or semiconductor wafer is subjected to rapid thermal heating cycles that increase the temperature past the activation temperature of the reaction in a controlled manner.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: July 13, 2021
    Assignees: Mattson Technology, Inc., Beijing E-Town Semiconductor Technology Co., Ltd.
    Inventor: Shawming Ma
  • Patent number: 11062897
    Abstract: Methods and apparatuses for etching metal-doped carbon-containing materials are provided herein. Etching methods include using a mixture of an etching gas suitable for etching the carbon component of the metal-doped carbon-containing material and an additive gas suitable for etching the metal component of the metal-doped carbon-containing material and igniting a plasma to selectively remove metal-doped carbon-containing materials relative to underlayers such as silicon oxide, silicon nitride, and silicon, at high temperatures. Apparatuses suitable for etching metal-doped carbon-containing materials are equipped with a high temperature movable pedestal, a plasma source, and a showerhead between a plasma generating region and the substrate.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: July 13, 2021
    Assignee: Lam Research Corporation
    Inventors: Yongsik Yu, David Wingto Cheung, Kirk J. Ostrowski, Nikkon Ghosh, Karthik S. Colinjivadi, Samantha Tan, Nathan Musselwhite, Mark Naoshi Kawaguchi
  • Patent number: 11043393
    Abstract: Apparatus, systems, and methods for processing a workpiece are provided. In one example implementation, the workpiece can include a silicon nitride layer and a silicon layer. The method can include admitting an ozone gas into a processing chamber. The method can include exposing the workpiece to the ozone gas. The method can include generating one or more species from a process gas using a plasma induced in a plasma chamber. The method can include filtering the one or more species to create a filtered mixture. The method can further include exposing the workpiece to the filtered mixture in the processing chamber such that the filtered mixture at least partially etches the silicon nitride layer more than the silicon layer. Due to ozone gas reacting with surface of silicon layer prior to etching process with fluorine-containing gas, selective silicon nitride etch over silicon can be largely promoted.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: June 22, 2021
    Assignees: Mattson Technology, Inc., Beijing E-Town Semiconductor Technology Co., Ltd.
    Inventors: Shanyu Wang, Ting Xie, Chun Yan, Xinliang Lu, Hua Chung, Michael X. Yang
  • Patent number: 11020778
    Abstract: A photoresist removal method is provided. The photoresist removal method includes analyzing the process status of each of a number of semiconductor substrate models undergoing a tested plasma ash process by a residue gas analyzer. The tested plasma ash processes for the semiconductor substrate models utilize a plurality of tested recipes. The photoresist removal method further includes selecting one of the tested recipes as a process recipe based on the analysis results from the residue gas analyzer and at least one expected performance criterion. In addition, the photoresist removal method includes performing a plasma ash process on a semiconductor substrate according to the process recipe to remove a photoresist layer from the semiconductor substrate.
    Type: Grant
    Filed: July 4, 2019
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Jen Hsiao, Ya-Ping Chen, Chien-Hung Lin, Wen-Pin Liu, Chin-Wen Chen
  • Patent number: 11008646
    Abstract: A vapor deposition apparatus disclosed by an embodiment comprises: a vacuum chamber (8); a mask holder (15) for holding a deposition mask 1; a substrate holder (29) for holding a substrate for vapor deposition (2); an electromagnet (3) disposed above a surface; a vapor deposition source 5 for vaporizing or sublimating a vapor deposition material; and a heat pipe (7) including at least a heat absorption part (71) and a heat dissipation part (72), the heat absorption part being in contact with the electromagnet (3), and the heat dissipation part being derived to an outside of the vacuum chamber (8). The heat pipe (7) and the electromagnet (3) are in intimate contact with each other at an area of a contact part between the heat pipe (7) and the electromagnet (3), the area being equal to or more than a cross-sectional area within an inner perimeter of a coil (32).
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: May 18, 2021
    Assignee: Sakai Display Products Corporation
    Inventors: Susumu Sakio, Katsuhiko Kishimoto
  • Patent number: 11000045
    Abstract: A method of treating a product or surface with a reactive gas, comprises producing the reactive gas by forming a high-voltage cold plasma (HVCP) from a working gas; transporting the reactive gas at least 5 cm away from the HVCP; followed by contacting the product or surface with the reactive gas. The HVCP does not contact the product or surface.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: May 11, 2021
    Assignee: NanoGuard Technologies, LLC
    Inventors: Kevin M. Keener, Mark A. Hochwalt
  • Patent number: 10991551
    Abstract: A cleaning method is provided. In the cleaning method, a cleaning gas is supplied into a processing chamber, a radio frequency (RF) power for plasma generation is applied to one of a first electrode on which a substrate is to be mounted and a second electrode disposed to be opposite to the first electrode in the processing chamber, and a negative voltage is applied to an edge ring disposed to surround the substrate. Further, plasma is generated from the cleaning gas and a cleaning process using the plasma is performed.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: April 27, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Mohd Fairuz Bin Budiman, Shinya Morikita, Toshifumi Nagaiwa
  • Patent number: 10971339
    Abstract: An ion source includes a plasma chamber, and a suppression electrode disposed downstream of the plasma chamber, and is operable to irradiate the suppression electrode with an ion beam produced from a cleaning gas to clean the suppression electrode. Prior to cleaning, the ion source moves the suppression electrode or the plasma chamber in a first direction to increase a distance between the plasma chamber and the suppression electrode.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: April 6, 2021
    Assignee: NISSIN ION EQUIPMENT CO., LTD.
    Inventors: Masakazu Adachi, Yuya Hirai, Tomoya Taniguchi
  • Patent number: 10964746
    Abstract: Some embodiments of the present disclosure relate to a method in which a functional layer is formed over an upper semiconductor surface of a semiconductor substrate, and a capping layer is formed over the functional layer. A first etchant is used to form a recess through the capping layer and through the functional layer. The recess has a first depth and exposes a portion of the semiconductor substrate there through. A protective layer is formed along a lower surface and inner sidewalls of the recess. A second etchant is used to remove the protective layer from the lower surface of the recess and to extend the recess below the upper semiconductor surface to a second depth to form a deep trench. To prevent etching of the functional layer, the protective layer remains in place along the inner sidewalls of the recess while the second etchant is used.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hsien Chou, Shih Pei Chou, Chih-Yu Lai, Sheng-Chau Chen, Chih-Ta Chen, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 10950449
    Abstract: Examples of a substrate processing apparatus includes a chamber, a susceptor provided in the chamber, a flow control ring of an insulator that is mounted on the chamber and surrounds the susceptor, a shower plate opposed to the susceptor, and a metal film that is formed on a lower surface of the flow control ring while exposing an upper surface of the flow control ring, and is in contact with the chamber.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: March 16, 2021
    Assignee: ASM IP Holding B.V.
    Inventors: Wataru Adachi, Kazuo Sato
  • Patent number: 10952309
    Abstract: The present disclosure is drawn to plasma treatment heads. In one example, a plasma head can include a dielectric barrier formed of a dielectric material. The dielectric barrier can have a treatment surface and an interior surface opposite of the treatment surface. A first electrode can be embedded within the dielectric barrier beneath the treatment surface. A second electrode can also be embedded within the dielectric barrier beneath the treatment surface and spaced laterally apart from the first electrode. A plurality of injection holes can penetrate through the dielectric plate from the interior surface to the treatment surface. The plurality of injection holes can be located between the first electrode and second electrode.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: March 16, 2021
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: James P. Shields
  • Patent number: 10950416
    Abstract: Processes for surface treatment of a workpiece are provided. In one example implementation, a method can include conducting a pre-treatment process on a processing chamber to generate a hydrogen radical affecting layer on a surface of the processing chamber prior to performing a hydrogen radical based surface treatment process on a workpiece in the processing chamber. In this manner, a pretreatment process can be conducted to condition a processing chamber to increase uniformity of hydrogen radical exposure to a workpiece.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: March 16, 2021
    Assignees: Mattson Technology, Inc., Beijing E-Town Semiconductor Technology Co., Ltd.
    Inventors: Qi Zhang, Xinliang Lu, Hua Chung
  • Patent number: 10892144
    Abstract: A plasma processing apparatus includes a storage unit, an acquisition unit and a monitoring unit. The storage unit stores change information indicating a change in a value for a temperature of a mounting table when a processing condition of plasma processing for a target object mounted on the mounting table is changed. The acquisition unit acquires the value for the temperature of the mounting table in a predetermined cycle. The monitoring unit monitors, based on the change information, a change in the processing condition of the plasma processing from the change in the value for the temperature of the mounting table acquired by the acquisition unit.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: January 12, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Shinsuke Oka
  • Patent number: 10883175
    Abstract: The disclosure relates to a vertical furnace for processing a plurality of substrates and a liner for use therein. The vertical furnace having an outer reaction tube having a central axis; and a liner constructed to extend in the interior of the outer reaction tube. The liner defines an interior space for accommodating substrates and is provided with a gas exhaust hole extending from the interior space to the outside. One of the outer wall of the liner and the inner wall of the reaction tube is provided with a flow deflector that protrudes radially from the respective wall into a gas passage between an outer wall of the liner and an inner wall of the reaction tube.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: January 5, 2021
    Assignee: ASM IP Holding B.V.
    Inventor: Frans Wiegers
  • Patent number: 10879079
    Abstract: The invention is directed to a method for treating an electronic device that is encapsulated in a plastic package, said method comprising the steps of providing a gas stream comprising a hydrogen source; inducing a hydrogen-containing plasma stream from said gas; and directing the hydrogen-containing plasma stream to the plastic package to etch the plastic package.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: December 29, 2020
    Assignee: JIACO Instruments Holding B.V.
    Inventors: Jiaqi Tang, Cornelis Ignatius Maria Beenakker, Willibrordus Gerardus Maria Van Den Hoek
  • Patent number: 10868022
    Abstract: Flash memory devices and fabrication methods thereof are provided. An exemplary method includes providing discrete bit lines on a semiconductor substrate, a first dielectric layer on top surfaces of the bit lines, and a floating gate structure on the first dielectric layer, trenches being formed between adjacent bit lines and on the semiconductor substrate; forming a sacrificial layer with a top surface above the top surfaces of the bit lines in the trenches; forming a second dielectric layer on top and side surfaces of the floating gate structure and the top surface of the sacrificial layer; forming a control gate structure on the second dielectric layer; removing portions of the second dielectric layer, the floating gate structure and the first dielectric layer to expose a portion of the sacrificial layer; and removing the sacrificial layer from the adjacent bit lines and the semiconductor substrate, thereby forming air gaps.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: December 15, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Sheng Fen Chiu, Liang Chen, Chao Feng Zhou, Xiao Bo Li
  • Patent number: 10847417
    Abstract: A method includes forming a first conductive feature and a second conductive feature adjacent the first conductive feature in a first dielectric layer, where the first dielectric layer includes a first dielectric material, and forming a dielectric feature in the first dielectric layer, where the dielectric feature contacts sidewalls of the first and the second conductive features and where the dielectric feature includes a second dielectric material different from the first dielectric material. The method further includes forming a second dielectric layer over the first dielectric layer, where the second dielectric layer includes a third dielectric material different from the second dielectric material, and forming a third conductive feature in the second dielectric layer, where the third conductive feature contacts a sidewall of the dielectric feature and either a top surface of the first conductive feature or a top surface of the second conductive feature.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Chieh Yao, Chung-Ju Lee
  • Patent number: 10804073
    Abstract: An apparatus and method for a large-scale high-throughput quantitative characterization and three-dimensional reconstruction of a material structure. The apparatus having a glow discharge sputtering unit, a sample transfer device, a scanning electron microscope unit and a GPU computer workstation. The glow discharge sputtering unit can achieve large size (cm order), nearly flat and fast sample preparation, and controllable achieve layer-by-layer ablation preparation along the depth direction of the sample surface; rapid scanning electron microscopy (SEM) can achieve large-scale and high-throughput acquisition of sample characteristic maps. The sample transfer device is responsible for transferring the sample between the glow discharge sputtering source and the scanning electron microscope in an accurately positioning manner.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: October 13, 2020
    Assignee: THE NCS TESTING TECHNOLOGY CO., LTD.
    Inventors: Haizhou Wang, Xing Yu, Xuejing Shen, Yunhai Jia, Xiaojia Li, Yuhua Lu, Weihao Wan, Jianqiu Luo, Dongling Li, Lei Zhao
  • Patent number: 10744771
    Abstract: To manufacture a liquid ejection head, a film having a lower surface free energy than a surface free energy of a substrate is first formed on an inner face of a liquid supply port. Next, a dry film to be a flow path forming member is attached to cover the surface of the substrate, and then a member to be an ejection orifice forming member is provided on the surface of the dry film.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: August 18, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Keiji Matsumoto, Seiichiro Yaginuma, Koji Sasaki, Jun Yamamuro, Kunihito Uohashi, Ryotaro Murakami, Tomohiko Nakano, Shingo Nagata
  • Patent number: 10714320
    Abstract: A time period for cleaning performed to remove a deposit formed within a chamber main body can be reduced. A plasma processing method including the cleaning of an inside of the chamber main body of a plasma processing apparatus is provided. The method includes etching including a main etching of etching an etching target film of a processing target object placed on a stage in a low temperature by generating plasma of a processing gas containing a fluorocarbon gas and/or a hydrofluorocarbon gas; carrying-out the processing target object from a chamber; and cleaning the inside of the chamber main body by generating plasma of a cleaning gas in a state that a temperature of an electrostatic chuck is set to be high.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: July 14, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Jin Kudo, Taku Gohira
  • Patent number: 10697063
    Abstract: The present disclosure relates to a corner spoiler designed to decrease high deposition rates on corner regions of substrates by changing the gas flow. In one embodiment, a corner spoiler for a processing chamber includes an L-shaped body fabricated from a dielectric material, wherein the L-shaped body is configured to change plasma distribution at a corner of a substrate in the processing chamber. The L-shaped body includes a first and second leg, wherein the first and second legs meet at an inside corner of the L-shaped body. The length of the first or second leg is twice the distance defined between the first or second leg and the inside corner. In another embodiment, a shadow frame for a depositing chamber includes a rectangular shaped body having a rectangular opening therethrough, and one or more corner spoilers coupled to the rectangular shaped body at corners of the rectangular shaped body.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: June 30, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Lai Zhao, Gaku Furuta, Qunhua Wang, Robin L. Tiner, Beom Soo Park, Soo Young Choi, Sanjay D. Yadav
  • Patent number: 10688538
    Abstract: Implementations described herein generally relate to methods and apparatus for in-situ removal of unwanted deposition buildup from one or more interior surfaces of a semiconductor substrate-processing chamber. In one implementation, the method comprises forming a reactive fluorine species from a fluorine-containing cleaning gas mixture. The method further comprises delivering the reactive fluorine species into a processing volume of a substrate-processing chamber. The processing volume includes one or more aluminum-containing interior surfaces having unwanted deposits formed thereon. The method further comprises permitting the reactive fluorine species to react with the unwanted deposits and aluminum-containing interior surfaces of the substrate-processing chamber to form aluminum fluoride. The method further comprises exposing nitrogen-containing cleaning gas mixture to in-situ plasma to form reactive nitrogen species in the processing volume.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: June 23, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Vivek Bharat Shah, Anup Kumar Singh, Bhaskar Kumar, Ganesh Balasubramanian, Bok Hoen Kim
  • Patent number: 10672592
    Abstract: The present invention provides a Soft Plasma Cleaning (SPC) system (30, 130, 230) including a Guided Soft-Plasma Cleaning (G-SPC) (30). The SPC system is a non-thermal, low temperature process and operable at atmosphere pressure, in both air and liquid medium. In an embodiment, a feedstock gas (40) is supplied to provide a discharging fluid (50) in the cleaning chamber (34). A plasma guiding and amplifying component (52) guides and expands the discharging fluid to cover a large ablation area over the workpiece (32), thereby also suppressing ion and electron bombardment damage or etching. The plasma guiding and amplifying component (52) may be formed with dielectric plates or tubes (37, 56, 58), with each dielectric having an aperture (37a, 56a, 58a). The electric field and ion energy in the cleaning chamber can be additionally controlled via a floating electrode (160, 160a), so as to suppress plasma damage during SPC.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: June 2, 2020
    Inventor: Chia Sern Chan
  • Patent number: 10643854
    Abstract: Multilayered stacks having layers of silicon interleaved with layers of a dielectric, such as silicon dioxide, are plasma etched with non-corrosive process gas chemistries. Etching plasmas of fluorine source gases, such as SF6 and/or NF3 typically only suitable for dielectric layers, are energized by pulsed RF to achieve high aspect ratio etching of silicon/silicon dioxide bi-layers stacks without the addition of corrosive gases, such as HBr or Cl2. In embodiments, a mask open etch and the multi-layered stack etch are performed in a same plasma processing chamber enabling a single chamber, single recipe solution for patterning such multi-layered stacks. In embodiments, 3D NAND memory cells are fabricated with memory plug and/or word line separation etches employing a fluorine-based, pulsed-RF plasma etch.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: May 5, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Daisuke Shimizu, Jong Mun Kim
  • Patent number: 10580616
    Abstract: An ion implantation system has an ion source configured form an ion beam and an angular energy filter (AEF) having an AEF region. A gas source passivates and/or etches a film residing on the AEF by a reaction of the film with a gas. The gas can be an oxidizing gas or a fluorine-containing gas. The gas source can selectively supply the gas to the AEF region concurrent with a formation of the ion beam. The AEF is heated to assist in the passivation and/or etching of the film by the gas. The heat can originate from the ion beam, and/or from an auxiliary heater associated with the AEF. A manifold distributor can be operably coupled to the gas source and configured to supply the gas to one or more AEF electrodes.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: March 3, 2020
    Assignee: Axcelis Technologies, Inc.
    Inventors: Teng-Chao David Tao, David Allen Kirkwood
  • Patent number: 10577688
    Abstract: A method for processing a substrate in a substrate processing system includes flowing reactant gases into a process chamber including a substrate and supplying a first power level sufficient to promote rearrangement of molecules adsorbed from the reactant gases onto a surface of the substrate. The first power level is supplied in a first predetermined period where the reactant gases are flowing into the process chamber and a second power level is not supplied to the process chamber. The method further includes waiting a second predetermined period subsequent to flowing the reactant gases and supplying the first power level and prior to supplying the second power level to the process chamber and, after the second predetermined period, performing plasma-enhanced, pulsed chemical vapor deposition of film on the substrate by supplying one or more precursors while supplying the second power level to the process chamber for a third predetermined period.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: March 3, 2020
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Adrien LaVoie, Hu Kang, Karl Leeser
  • Patent number: 10544483
    Abstract: A method includes providing nanoparticles having a tin coating surrounding a metal nucleus, such as copper. The nucleus forms first and acts as a seed growing into nanoparticles with a tin coating and a nucleus. The nanoparticles are at least partially vaporized, thereby producing vaporized tin ions. An emission of extreme ultraviolet (EUV) radiation is generated from the vaporized tin ions.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: January 28, 2020
    Assignee: Lockheed Martin Corporation
    Inventors: Randall M. Stoltenberg, Alfred A. Zinn
  • Patent number: 10541171
    Abstract: A protective cover for an electrostatic chuck may include a conductive wafer and a plasma resistant ceramic layer on at least one surface of the conductive wafer. The plasma resistant ceramic layer covers a top surface of the conductive wafer, side walls of the conductive wafer and an outer perimeter of a bottom surface of the conductive wafer. Alternatively, a protective cover for an electrostatic chuck may include a plasma resistant bulk sintered ceramic wafer and a conductive layer on a portion of a bottom surface of the plasma resistant bulk sintered ceramic wafer, wherein a perimeter of the bottom surface is not covered. The protective layer may be used to protect an electrostatic chuck during a plasma cleaning process.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: January 21, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Vijay D. Parkhe
  • Patent number: 10490390
    Abstract: A substrate processing device includes a housing connected to ground, a cathode stage that supports a substrate, an anode unit, and a gas feeding unit that feeds gas toward the first plate. The cathode stage is applied with voltage for generating plasma. The anode unit includes a first plate including first through holes and a second plate including second through holes that are larger than the first through holes. The second plate is located between the first plate and the cathode stage. The first plate produces a flow of the gas through the first through holes. The gas that has passed through the first through holes flows through the second through holes into an area between the second plate and the cathode stage. A distance between the first plate and the second plate is 10 mm or greater and 50 mm or less.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: November 26, 2019
    Assignee: ULVAC, INC.
    Inventors: Tetsushi Fujinaga, Atsuhito Ihori, Masahiro Matsumoto, Noriaki Tani, Harunori Iwai, Kenji Iwata, Yoshinao Sato
  • Patent number: 10474033
    Abstract: Embodiments described herein relate to methods and apparatus for performing immersion field guided post exposure bake processes. Embodiments of apparatus described herein include a chamber body defining a processing volume. A pedestal may be disposed within the processing volume and a first electrode may be coupled to the pedestal. A moveable stem may extend through the chamber body opposite the pedestal and a second electrode may be coupled to the moveable stem. In certain embodiments, a fluid containment ring may be coupled to the pedestal and a dielectric containment ring may be coupled to the second electrode.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: November 12, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Viachslav Babayan, Douglas A. Buchberger, Jr., Qiwei Liang, Ludovic Godet, Srinivas D. Nemani, Daniel J. Woodruff, Randy Harris, Robert B. Moore
  • Patent number: 10446713
    Abstract: To remove the mask formed by nanoimprinting after dry etching. A mask is formed by nanoimprinting on a back surface of a substrate. Subsequently, dry etching is performed using chlorine gas. Dry etching is finished with the mask kept remaining. A deteriorated layer is formed on the surface of the remaining mask. The mask is irradiated with plasma generated using a mixture gas of nitrogen and oxygen. Thereby, the deteriorated layer formed on the surface of the mask is removed by evaporation. The mask is removed by dissolving in BHF (buffered hydrofluoric acid).
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: October 15, 2019
    Assignee: TOYODA GOSEI CO., LTD.
    Inventor: Kimiyasu Ide
  • Patent number: 10446373
    Abstract: In an embodiment of the invention there is a cyclotronic actuator utilizing a high-voltage plasma driver connected to a first electrode. A second electrode is grounded and the two are isolated from each other by a dielectric plate. A magnet is positioned beneath the dielectric plate such that a coaxial dielectric barrier discharge plasma is formed outwardly between the first electrode across the dielectric plate. The magnet positioned beneath the dielectric plate introduces a magnetic field transverse to the plasma current path, such that the plasma discharge discharges radially and the local magnetic field is oriented vertically in a direction perpendicular to the dielectric plate to create a Lorentz Force, which forces the plasma discharge to move radially outwardly in a curved radial streamer mode pattern.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: October 15, 2019
    Assignee: CU Aerospace, LLC
    Inventors: Joseph W. Zimmerman, David L. Carroll, Phillip J. Ansell, Georgi Hristov
  • Patent number: 10410845
    Abstract: Embodiments include a plasma processing method for cleaning polymer byproducts from interior surfaces of the plasma chamber. In an embodiment the plasma process may include processing a workpiece in a plasma processing chamber. Thereafter, the method may include removing the workpiece from the processing chamber. After the workpiece is removed, embodiments may include cleaning the plasma processing chamber with a cleaning process that includes a high pressure cleaning process, a first low pressure cleaning process, and a second low pressure cleaning process, wherein the second low pressure cleaning process includes applying a pulsed bias.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: September 10, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Kenny Linh Doan, Usama Dadu, Wonseok Lee, Daisuke Shimizu, Li Ling, Kevin Choi
  • Patent number: 10395915
    Abstract: Provided is a substrate treatment apparatus. The apparatus includes a chuck supporting a substrate and being rotatable, a container surrounding the chuck and collecting chemicals scattered due to rotations of the substrate, and a first spray nozzle spraying the chemicals to the substrate.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: August 27, 2019
    Assignee: Semes Co., Ltd.
    Inventors: Se Won Lee, Yong Hee Lee, Jae Yong Kim
  • Patent number: 10351954
    Abstract: A process for depositing a thin film material on a substrate is disclosed, comprising simultaneously directing a series of gas flows from the output face of a delivery head of a thin film deposition system toward the surface of a substrate, and wherein the series of gas flows comprises at least a first reactive gaseous material, an inert purge gas, and a second reactive gaseous material, wherein the first reactive gaseous material is capable of reacting with a substrate surface treated with the second reactive gaseous material, wherein one or more of the gas flows provides a pressure that at least contributes to the separation of the surface of the substrate from the face of the delivery head. A system capable of carrying out such a process is also disclosed.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: July 16, 2019
    Assignee: EASTMAN KODAK COMPANY
    Inventor: David H. Levy
  • Patent number: 10340125
    Abstract: A system and method for providing pulsed excited species from a remote plasma unit to a reaction chamber are disclosed. The system includes a pressure control device to control a pressure at the remote plasma unit as reactive species from the remote plasma unit are pulsed to the reaction chamber.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: July 2, 2019
    Assignee: ASM IP Holding B.V.
    Inventor: Jereld Lee Winkler
  • Patent number: 10332724
    Abstract: In an embodiment of the invention there is a cyclotronic actuator. The actuator is defined by having a high-voltage plasma driver connected to a first electrode. The first electrode is surrounded by a dielectric material. A second electrode is grounded and placed away from the first electrode, such that a plasma arc is formed between the pair of electrodes when the high-voltage plasma driver is activated. A ring magnet surrounding the second electrode is configured to introduce a magnetic field locally to the plasma arc. The plasma arc will then discharge in a radial direction. The magnet creates a local magnetic field oriented vertically in a direction parallel to the axisymmetric orientation of the first and second electrodes to create a Lorentz Force. The force causes the plasma arc to move in a tangential direction and causes the plasma arc to discharge out in a circular pattern.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: June 25, 2019
    Assignee: CU Aerospace, LLC
    Inventors: Joseph W. Zimmerman, David L. Carroll, Phillip J. Ansell, Georgi Hristov
  • Patent number: 10332850
    Abstract: Provided herein is a method for producing hollow contact areas for insertion bonding, formed on a semiconductor substrate comprising a stack of one or more metallization layers on a surface of the substrate. Openings are etched in a dielectric layer by plasma etching, using a resist layer as a mask. The resist layer and plasma etch parameters are chosen to obtain openings with sloped sidewalls having a pre-defined slope, due to controlled formation of a polymer layer forming on the sidewalls of the resist hole and the hollow contact opening formed during etching. According to a preferred embodiment, metal deposited in the hollow contact areas and on top of the dielectric layer is planarized using chemical mechanical polishing, leading to mutually isolated contact areas. The disclosure is also related to components obtainable by the method and to a semiconductor package comprising such components.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: June 25, 2019
    Assignee: IMEC
    Inventors: Eric Beyne, Wenqi Zhang, Geraldine Jamieson, Bart Swinnen
  • Patent number: 10325956
    Abstract: Some embodiments of the present disclosure relate to a method in which a functional layer is formed over an upper semiconductor surface of a semiconductor substrate, and a capping layer is formed over the functional layer. A first etchant is used to form a recess through the capping layer and through the functional layer. The recess has a first depth and exposes a portion of the semiconductor substrate there through. A protective layer is formed along a lower surface and inner sidewalls of the recess. A second etchant is used to remove the protective layer from the lower surface of the recess and to extend the recess below the upper semiconductor surface to a second depth to form a deep trench. To prevent etching of the functional layer, the protective layer remains in place along the inner sidewalls of the recess while the second etchant is used.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hsien Chou, Shih Pei Chou, Chih-Yu Lai, Sheng-Chau Chen, Chih-Ta Chen, Yeur-Luen Tu, Chia-Shiung Tsai