Monolithic Semiconductor Patents (Class 136/249)
  • Patent number: 10304986
    Abstract: A photovoltaic device and method include a substrate coupled to an emitter side structure on a first side of the substrate and a back side structure on a side opposite the first side of the substrate. The emitter side structure or the back side structure include layers alternating between wide band gap layers and narrow band gap layers to provide a multilayer contact with an effectively increased band offset with the substrate and/or an effectively higher doping level over a single material contact. An emitter contact is coupled to the emitter side structure on a light collecting end portion of the device. A back contact is coupled to the back side structure opposite the light collecting end portion.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoar-Tabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 10304985
    Abstract: A photovoltaic device and method include a doped germanium-containing substrate, an emitter contact coupled to the substrate on a first side and a back contact coupled to the substrate on a side opposite the first side. The emitter includes at least one doped layer of an opposite conductivity type as that of the substrate and the back contact includes at least one doped layer of the same conductivity type as that of the substrate. The at least one doped layer of the emitter contact or the at least one doped layer of the back contact is in direct contact with the substrate, and the at least one doped layer of the emitter contact or the back contact includes an n-type material having an electron affinity smaller than that of the substrate, or a p-type material having a hole affinity larger than that of the substrate.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Bahman Hekmatshoar-Tabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 10297709
    Abstract: A Schottky-barrier-reducing layer is provided between a p-doped semiconductor layer and a transparent conductive material layer of a photovoltaic device. The Schottky-barrier-reducing layer can be a conductive material layer having a work function that is greater than the work function of the transparent conductive material layer. The conductive material layer can be a carbon-material layer such as a carbon nanotube layer or a graphene layer. Alternately, the conductive material layer can be another transparent conductive material layer having a greater work function than the transparent conductive material layer. The reduction of the Schottky barrier reduces the contact resistance across the transparent material layer and the p-doped semiconductor layer, thereby reducing the series resistance and increasing the efficiency of the photovoltaic device.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: May 21, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, EGYPT NANOTECHNOLOGY CENTER
    Inventors: Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana, George S. Tulevski, Ahmed Abou-Kandil, Hisham S. Mohamed, Mohamed Saad, Osama Tobail
  • Patent number: 10290753
    Abstract: Nanoparticles, methods of manufacture, devices comprising the nanoparticles, methods of their manufacture, and methods of their use are provided herein. The nanoparticles and devices having photoabsorptions in the range of 1.7 ?m to 12 ?m and can be used as photoconductors, photodiodes, phototransistors, charge-coupled devices (CCD), luminescent probes, lasers, thermal imagers, night-vision systems, and/or photodetectors.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: May 14, 2019
    Assignee: The University of Chicago
    Inventors: Philippe Guyot-Sionnest, Sean E. Keuleyan, Emmanuel Lhuillier
  • Patent number: 10256357
    Abstract: A method for fabricating a device with integrated photovoltaic cells includes supporting a semiconductor substrate on a first handle substrate and doping the semiconductor substrate to form doped alternating regions with opposite conductivity. A doped layer is formed over a first side the semiconductor substrate. A conductive material is patterned over the doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions to define a plurality of photovoltaic cells connected in series on a monolithic structure.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 10243094
    Abstract: A method for producing a multiple-substrate stack from an, in particular wavelength-sensitive, semiconductor substrate and at least one further, in particular wavelength-sensitive, semiconductor substrate with the following steps: applying a dielectric layer, which is electrically conductive at least in certain sections, onto at least one substrate surface of at least one of the semiconductor substrates, and contacting the semiconductor substrate with the further semiconductor substrate and forming an electrically conductive connection between the semiconductor substrates.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: March 26, 2019
    Assignee: EV GROUP E. THALLNER GMBH
    Inventor: Thorsten Matthias
  • Patent number: 10230015
    Abstract: A photovoltaic device includes a p-type layer. An intrinsic layer is formed directly on the p-type layer and includes an interface region extending into the intrinsic layer that includes a gradually decreasing band gap energy going from the p-type layer into the intrinsic layer formed by a graded deposition temperature. An n-type layer is formed directly on the intrinsic layer.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ahmed Abou-Kandil, Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Mohamed Saad, Devendra K. Sadana
  • Patent number: 10224351
    Abstract: Exemplary embodiments provide a solar cell device, and method for forming the solar cell device by integrating a switch component into a solar cell element. The solar cell element can include a solar cell, a solar cell array and/or a solar cell panel. The integrated solar cell element can be used for a solar sensor, while the solar sensor can also use discrete switches for each solar cell area of the sensor. Exemplary embodiments also provide a connection system for the solar cell elements and a method for super-connecting the solar cell elements to provide a desired connection path or a desired power output through switch settings. The disclosed connection systems and methods can allow for by-passing underperforming solar cell elements from a plurality of solar cell elements. In embodiments, the solar cell element can be extended to include a battery or a capacitor.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: March 5, 2019
    Assignee: INTERSIL AMERICAS LLC
    Inventor: Stephen Joseph Gaul
  • Patent number: 10211354
    Abstract: A monolithically integrated system of silicon solar cells. A system having a silicon substrate and a plurality of solar cells formed on the silicon substrate. Each solar cell can have an emitter portion and a base portion. The system can also have a plurality of intermediate regions, each intermediate region having a polarity and electrically separating at least two portions of adjacent solar cells from one another such that the polarity of the intermediate region is opposite to a polarity of at least one of the separated portions of the adjacent solar cells.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: February 19, 2019
    Assignee: NEWSOUTH INNOVATIONS PTY LIMITED
    Inventors: Catherine Emily Chan, Stuart Ross Wenham, Brett Jason Hallam, Alison Maree Wenham
  • Patent number: 10177266
    Abstract: A photovoltaic device and method include a substrate coupled to an emitter side structure on a first side of the substrate and a back side structure on a side opposite the first side of the substrate. The emitter side structure or the back side structure include layers alternating between wide band gap layers and narrow band gap layers to provide a multilayer contact with an effectively increased band offset with the substrate and/or an effectively higher doping level over a single material contact. An emitter contact is coupled to the emitter side structure on a light collecting end portion of the device. A back contact is coupled to the back side structure opposite the light collecting end portion.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoar-Tabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 10170659
    Abstract: An integrated thin-film lateral multi junction solar device and fabrication method are provided. The device includes, for instance, a substrate, and a plurality of stacks extending vertically from the substrate. Each stack may include layers, and be electrically isolated against another stack. Each stack may also include an energy storage device above the substrate, a solar cell above the energy storage device, a transparent medium above the solar cell, and a micro-optic layer of spectrally dispersive and concentrating optical devices above the transparent medium. Furthermore, the device may include a first power converter connected between the energy storage device and a power bus, and a second power converter connected between the solar cell and the power bus. Further, different solar cells of different stacks may have different absorption characteristics.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Hans-Juergen Eickelmann, Ruediger Kellmann, Hartmut Kuehl, Markus Schmidt
  • Patent number: 10171030
    Abstract: The present invention relates to power supplies and in particular to an electronic power supply that is mounted to a printed circuit board and can be used to power electronic circuits and devices. Disclosed is a power supply which includes a photoluminescent light source. The photoluminescent light source generates light in response to receiving input power. One or more than one photovoltaic device is in optical communication with the photoluminescent light source, and generates output power in response to receiving light from the photoluminescent light source. The amount of output power generated by the one or more than one photovoltaic device is greater than the amount of input power received by the photoluminescent light source. In some embodiments the photoluminescent light source includes a light-emitting device and a photoluminescent material, each of which is embedded in an optical coupling material.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: January 1, 2019
    Assignee: IsoLine Component Company, LLC
    Inventor: Michael Jon Hodges
  • Patent number: 10164567
    Abstract: In one embodiment, harmful solar cell polarization is prevented or minimized by providing a conductive path that bleeds charge from a front side of a solar cell to the bulk of a wafer. The conductive path may include patterned holes in a dielectric passivation layer, a conductive anti-reflective coating, or layers of conductive material formed on the top or bottom surface of an anti-reflective coating, for example. Harmful solar cell polarization may also be prevented by biasing a region of a solar cell module on the front side of the solar cell.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: December 25, 2018
    Assignee: SunPower Corporation
    Inventors: Richard M. Swanson, Denis De Ceuster, Vikas Desai, Douglas H. Rose, David D. Smith, Neil Kaminar
  • Patent number: 10158037
    Abstract: An optical transducer, optoelectronic device, and semiconductor are disclosed. An illustrative optical transducer is disclosed to include a plurality of p-n stacks, where each p-n stack comprises at least a p-layer and an n-layer, and formed therein a built-in photovoltage between the p-layer and the n-layer. The p-layers and n-layers are disclosed to have substantially the same n-type material in substantially the same composition such that each p-n stack in the plurality of p-n stacks has a substantially similar built-in photovoltage. The optical transducer is further disclosed to include a plurality of connecting layers, each connecting layer in the plurality of connecting layers being sandwiched between two adjacent p-n stacks for electrically connecting the two adjacent p-n stacks. The p-n stacks in the plurality of p-n stacks may be arranged such that the built-in photovoltage of each p-n stack additively contributes to an overall electric potential of the transducer.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: December 18, 2018
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Simon Fafard, Denis Masson
  • Patent number: 10158034
    Abstract: An embodiment includes an apparatus comprising: a first photovoltaic cell; a first through silicon via (TSV) included in the first photovoltaic cell and passing through at least a portion of a doped silicon substrate, the first TSV comprising (a)(i) a first sidewall, which is doped oppositely to the doped silicon substrate, and (a)(ii) a first contact substantially filling the first TSV; and a second TSV included in the first photovoltaic cell and passing through at least another portion of the doped silicon substrate, the second TSV comprising (b)(i) a second sidewall, which comprises the doped silicon substrate, and (b)(ii) a second contact substantially filling the second TSV; wherein the first and second contacts each include a conductive material that is substantially transparent. Other embodiments are described herein.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Kinyip Phoa, Nidhi Nidhi, Chia-Hong Jan, Walid M. Hafez, Yi Wei Chen
  • Patent number: 10141461
    Abstract: A method for forming a multi-junction photovoltaic device includes providing a germanium layer and etching pyramidal shapes in the germanium layer such that (111) facets are exposed to form a textured surface. A first p-n junction is formed on or over the textured surface from III-V semiconductor materials. Another p-n junction is formed over the first p-n junction from III-V semiconductor materials and follows the textured surface.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: November 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoartabari, Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 10103281
    Abstract: A thin film amorphous silicon solar cell may have front contact between a hydrogenated amorphous silicon layer and a transparent conductive oxide layer. The cell may include a layer of a refractory metal, chosen among the group composed of molybdenum, tungsten, tantalum and titanium, of thickness adapted to ensure a light transmittance of at least 80%, interposed therebetween, before growing by PECVD a hydrogenated amorphous silicon p-i-n light absorption layer over it. A refractory metal layer of just about 1 nm thickness may effectively shield the oxide from the reactive plasma, thereby preventing a diffused defect when forming the p.i.n. layer that would favor recombination of light-generated charge carriers.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: October 16, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Salvatore Lombardo, Cosimo Gerardi, Sebastiano Ravesi, Marina Foti, Cristina Tringali, Stella Loverso, Nicola Costa
  • Patent number: 10088357
    Abstract: A photovoltaic sensor array for detecting variations in light intensity is disclosed. The array has a plurality of photo voltaic cells which are electrically independent from one another and formed on a common substrate. Each cell has corresponding positive and negative electrical connections and each cell is arranged to detect light intensity so that variations in light intensity between the cells can be obtained.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: October 2, 2018
    Assignee: BIO AMD HOLDINGS LIMITED
    Inventors: Nassr-Eddine Djennati, Andrew Mitchell
  • Patent number: 10090425
    Abstract: A photoelectrode, methods of making and using, including systems for water-splitting are provided. The photoelectrode can be a semiconducting material having a photocatalyst such as nickel or nickel-molybdenum coated on the material. The photoelectrode includes an elongated axially integrated wire having at least two different wire compositions.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: October 2, 2018
    Assignee: California Institute of Technology
    Inventors: Nathan S. Lewis, Shu Hu
  • Patent number: 10066318
    Abstract: A method of disordering a layer of an optoelectronic device including; growing a plurality of lower layers; introducing an isoelectronic surfactant; growing a layer; allowing the surfactant to desorb; and growing subsequent layers all performed at a low pressure of 25 torr.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: September 4, 2018
    Assignee: THE BOEING COMPANY
    Inventors: Christopher M. Fetzer, James H. Ermer, Richard R. King, Peter C. Colter
  • Patent number: 10062793
    Abstract: Photon absorption, and thus current generation, is hindered in conventional thin-film solar cell designs, including quantum well structures, by the limited path length of incident light passing vertically through the device. Optical scattering into lateral waveguide structures provides a physical mechanism to increase photocurrent generation through in-plane light trapping. However, the insertion of wells of high refractive index material with lower energy gap into the device structure often results in lower voltage operation, and hence lower photovoltaic power conversion efficiency. The voltage output of an InGaAs quantum well waveguide photovoltaic device can be increased by employing a III-V material structure with an extended wide band gap emitter heterojunction.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: August 28, 2018
    Assignee: Magnolia Solar, Inc.
    Inventors: Roger E. Welser, Ashok K. Sood
  • Patent number: 10056516
    Abstract: A solar panel of the present invention includes a plurality of solar cells arranged in a substantially circular shape, and a plurality of connection sections which are provided near a center portion where the plurality of solar cells are all close to each other, and electrically connect the plurality of solar cells. Therefore, the plurality of connection sections can be centrally placed near the center portion where the plurality of solar cells are all close to each other. As a result, a decrease in the light-receiving area due to the plurality of connection sections can be reduced, and fluctuations in the light-receiving area due to pointers moving over the solar cells can be reduced.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: August 21, 2018
    Assignee: CASIO COMPUTER CO., LTD.
    Inventor: Yuta Saito
  • Patent number: 10050169
    Abstract: A stacked optocoupler component, having a transmitter component with a transmitting area and a receiver component with a receiving area and a plate-shaped electrical isolator. The isolator is formed between the transmitter component and the receiver component, and the transmitter component and the receiver component and the isolator are arranged one on top of another in the form of a stack. The transmitter component and the receiver component are galvanically separated from one another but optically coupled to one another. The isolator is transparent for the emission wavelengths of the transmitter component and the centroidal axis of the transmitting area and the centroidal axis of the receiving area are substantially or precisely parallel to one another.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: August 14, 2018
    Assignee: Azur Space Solar Power GmbH
    Inventors: Wolfgang Guter, Daniel Fuhrmann, Clemens Waechter
  • Patent number: 10042327
    Abstract: A timepiece has a solar panel including a plurality of solar cells; a dial disposed on the face side of the solar panel and configured to transmit a light; a molding member disposed to the face side of the dial overlapping the outside edge of the dial when seen from the face side of the timepiece; and an opaque light shield disposed on the face side of the dial on the inside side of the molding member; the solar panel having connectors that connect adjacent solar cells in series, and at least part of each connector is covered by the light shield when seen from the face.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: August 7, 2018
    Assignee: Seiko Epson Corporation
    Inventors: Akihiro Sawada, Shuichi Tamura
  • Patent number: 10043929
    Abstract: A method is provided for converting optical energy to electrical energy in a spectrally adaptive manner. The method begins by directing optical energy into a first photovoltaic module that includes non-single crystalline semiconductor layers defining a junction such that a first spectral portion of the optical energy is converted into a first quantity of electrical energy. A second spectral portion of the optical energy unabsorbed by the first module is absorbed by a second photovoltaic module that includes non-single crystalline semiconductor layers defining a junction and converted into a second quantity of electrical energy. The first quantity of electrical energy is conducted from the first module to a first external electrical circuit along a first path. The second quantity of electrical energy is conducted from the second module to a second external electrical circuit along a second path that is in parallel with the first path.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: August 7, 2018
    Assignee: Sunlight Photonics Inc.
    Inventors: Sergey Frolov, Allan James Bruce, Joseph Shmulovich
  • Patent number: 10032942
    Abstract: Methods of fabricating solar cells using a metal-containing thermal and diffusion barrier layer in foil-based metallization approaches, and the resulting solar cells, are described. For example, a method of fabricating a solar cell includes forming a plurality of semiconductor regions in or above a substrate. The method also includes forming a metal-containing thermal and diffusion barrier layer above the plurality of semiconductor regions. The method also includes forming a metal seed layer on the metal-containing thermal and diffusion barrier layer. The method also includes forming a metal conductor layer on the metal seed layer. The method also includes laser welding the metal conductor layer to the metal seed layer. The metal-containing thermal and diffusion barrier layer protects the plurality of semiconductor regions during the laser welding.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: July 24, 2018
    Assignees: SunPower Corporation, Total Marketing Services
    Inventors: Taeseok Kim, Robert Woehl, Gabriel Harley, Nils-Peter Harder, Jens-Dirk Moschner, Matthieu Moors, Michel Arsene Olivier Ngamo Toko
  • Patent number: 10027420
    Abstract: Methods and systems for a silicon-based optical phase modulator with high modal overlap are disclosed and may include, in an optical modulator having a rib waveguide in which a cross-shaped depletion region separates four alternately doped sections: receiving an optical signal at one end of the optical modulator, modulating the received optical signal by applying a modulating voltage, and communicating a modulated optical signal out of an opposite end of the modulator. The modulator may be in a silicon photonically-enabled integrated circuit which may be in a complementary-metal oxide semiconductor (CMOS) die. An optical mode may be centered on the cross-shaped depletion region. The four alternately doped sections may include: a shallow depth p-region, a shallow depth n-region, a deep p-region, and a deep n-region. The shallow depth p-region may be electrically coupled to the deep p-region periodically along the length of the modulator.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: July 17, 2018
    Assignee: Luxtera, Inc.
    Inventors: Subal Sahni, Kam-Yan Hon, Attila Mekis, Gianlorenzo Masini, Lieven Verslegers
  • Patent number: 10020423
    Abstract: A light emitting semiconductor device (401) has an active region (405) formed of Bismuth (Bi) and one or more other group V elements. In a particular embodiment the III-V material comprises Gallium Arsenide (GaAs) in addition to Bismuth. The inclusion of Bismuth in the III-V material raises the spin-orbit splitting energy of the material while reducing the band gap. When the spin-orbit splitting energy exceeds the band gap, Auger recombination processes are inhibited, reducing the sensitivity of the light emitting semiconductor device (401) to changes in ambient temperature.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: July 10, 2018
    Assignee: University of Surrey
    Inventor: Stephen John Sweeney
  • Patent number: 10008608
    Abstract: To provide a liquid crystal display device suitable for a thin film transistor which uses an oxide semiconductor. In a liquid crystal display device which includes a thin film transistor including an oxide semiconductor layer, a film having a function of attenuating the intensity of transmitting visible light is used as an interlayer film which covers at least the oxide semiconductor layer. As the film having a function of attenuating the intensity of transmitting visible light, a coloring layer can be used and a light-transmitting chromatic color resin layer is preferably used. An interlayer film which includes a light-transmitting chromatic color resin layer and a light-blocking layer may be formed in order that the light-blocking layer is used as a film having a function of attenuating the intensity of transmitting visible light.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: June 26, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuji Ishitani, Daisuke Kubota
  • Patent number: 9985076
    Abstract: A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over and in contact with the first metal-chalcogenide layer. The first metal-chalcogenide layer has a first conductivity type and the second metal-chalcogenide layer has a second conductivity type. The plane of contact between the first and second metal-chalcogenide layers creates the p-n junction of the built-in diode. Then a polymer layer is selectively deposited on the second metal-chalcogenide layer. The second metal-chalcogenide layer provides ions to the polymer layer to change its resistivity. A top electrode is then provided over the polymer layer. An exemplary memory cell may have the following stacked structure: first electrode/n-type semiconductor/p-type semiconductor/conjugated polymer/second electrode.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: May 29, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Kristy A. Campbell
  • Patent number: 9972737
    Abstract: Manufacture of multi junction solar cells, and devices thereof, are disclosed. The architectures are also adapted to provide for a more uniform and consistent fabrication of the solar cell structures, leading to improved yields, greater efficiency, and lower costs. Certain solar cells may be from a different manufacturing processes and further include one or more compositional gradients of one or more semiconductor elements in one or more semiconductor layers, resulting in a more optimal solar cell device.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: May 15, 2018
    Assignee: EpiWorks, Inc.
    Inventors: David Ahmari, Swee Lim, Shiva Rai, David Forbes
  • Patent number: 9966485
    Abstract: Disclosed are a solar cell and a method of fabricating the same. The solar cell includes a first back electrode layer on a support substrate; a second back electrode layer on the first back electrode layer; a light absorbing layer on the second back electrode layer; and a front electrode layer on the light absorbing layer.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: May 8, 2018
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Jong Hyun Kim
  • Patent number: 9947823
    Abstract: Device structures, apparatuses, and methods are disclosed for photovoltaic cells that may be a single junction or multijunction solar cells, with at least a first layer comprising a group-IV semiconductor in which part of the cell comprises a second layer comprising a III-V semiconductor or group-IV semiconductor having a different composition than the group-IV semiconductor of the first layer, such that a heterostructure is formed between the first and second layers.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: April 17, 2018
    Assignee: THE BOEING COMPANY
    Inventors: Richard R. King, Christopher M. Fetzer, Nasser H. Karam
  • Patent number: 9941437
    Abstract: A solar cell has a condenser lens and a solar cell element, the solar cell element including an n-type InGaAs layer, an n-type GaAs layer, an n-type InGaP layer, the first InGaAs peripheral part having a thickness (d2), and a width (w2), the second InGaAs peripheral part having a thickness (d3), and a width (w3), the first GaAs peripheral part having a thickness (d5), and a width (w4), the second GaAs peripheral part a thickness (d6), and a width (w5), the first InGaP peripheral part having a thickness (d8), and a width (w6), the second InGaP peripheral part having a thickness (d9), and a width (w7), the following inequation set being satisfied: 1 nm?(d2, d3, d5, and d6)?4 nm, 1 nm?(d8 and d9)?5 nm, 100 nm?(w2, w3, w4, w5, w6, and w7), the InGaAs center part having a thickness (w1), a window layer has a range S irradiated by sunlight having a width (w8); w8?w1.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: April 10, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Akio Matsushita, Akihiro Itoh, Tohru Nakagawa, Hidetoshi Ishida
  • Patent number: 9935212
    Abstract: A solar cell and a method for manufacturing the same are disclosed. The solar cell includes a first conductive type substrate, an emitter layer of a second conductive type opposite the first conductive type, the emitter layer and the substrate forming a p-n junction, a plurality of first electrodes electrically connected to the emitter layer, and a second electrode electrically connected to the substrate. At least one of the plurality of first electrodes includes a first electrode layer, a plurality of first electrode auxiliaries separated from the first electrode layer, and a second electrode layer positioned on an upper surface and a lateral surface of the first electrode layer and on an upper surface and a lateral surface of each of the plurality of first electrode auxiliaries.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: April 3, 2018
    Assignee: LG ELECTRONICS INC.
    Inventors: Junyong Ahn, Younghyun Lee, Jinhyung Lee
  • Patent number: 9935223
    Abstract: A method for fabricating a device with integrated photovoltaic cells includes supporting a semiconductor substrate on a first handle substrate and doping the semiconductor substrate to form doped alternating regions with opposite conductivity. A doped layer is formed over a first side the semiconductor substrate. A conductive material is patterned over the doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions to define a plurality of photovoltaic cells connected in series on a monolithic structure.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 9917220
    Abstract: Methods for forming a photovoltaic device include forming a buffer layer between a transparent electrode and a p-type layer. The buffer layer includes a doped germanium-free silicon base material. The buffer layer has a work function that falls within barrier energies of the transparent electrode and the p-type layer. An intrinsic layer and an n-type layer are formed on the p-type layer. Devices are also provided.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: March 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Augustin J. Hong, Marinus J. Hopstaken, Jeehwan Kim, John A. Ott, Devendra K. Sadana
  • Patent number: 9891597
    Abstract: An electronic device includes a solar panel including a solar cell, the solar cell including a plurality of light receiving regions and a connecting region, the connecting region having a width narrower than widths of the plurality of light receiving regions and connecting the plurality of light receiving regions, wherein a conductive reinforcing material made of a conductive material is provided in the connecting region and is electrically connected to the plurality of light receiving regions.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: February 13, 2018
    Assignee: CASIO COMPUTER CO., LTD.
    Inventors: Kazuaki Abe, Masakuni Iwanaga, Junro Yano, Yuta Saito
  • Patent number: 9859455
    Abstract: A photovoltaic device includes a crystalline substrate having a first dopant conductivity, an interdigitated back contact and a front surface field structure. The front surface field structure includes a crystalline layer formed on the substrate and a noncrystalline layer formed on the crystalline layer. The crystalline layer and the noncrystalline layer are doped with dopants having an opposite dopant conductivity from that of the substrate. Methods are also disclosed.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, Bahman Hekmatshoartabari, Devendra K. Sadana, Davood Shahrjerdi
  • Patent number: 9846412
    Abstract: An electronic device includes a solar panel including a solar cell, the solar cell including a plurality of light receiving regions and a connecting region, the connecting region having a width narrower than widths of the plurality of light receiving regions and connecting the plurality of light receiving regions, wherein a conductive reinforcing material made of a conductive material is provided in the connecting region and is electrically connected to the plurality of light receiving regions.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: December 19, 2017
    Assignee: CASIO COMPUTER CO., LTD.
    Inventors: Kazuaki Abe, Masakuni Iwanaga, Junro Yano, Yuta Saito
  • Patent number: 9829726
    Abstract: An electro-optical modulator includes a substrate 201; an optical waveguide formed of a silicon-containing i-type amorphous semiconductor 204 on the substrate; and a silicon-containing p-type semiconductor layer 203 and a silicon-containing n-type semiconductor layer 205 arranged apart from each other with the silicon-containing optical waveguide formed of an i-type amorphous semiconductor 204 interposed therebetween and constituting optical waveguides together with the silicon-containing optical waveguide formed of an i-type amorphous semiconductor. The silicon-containing p-type semiconductor layer 203 and/or silicon-containing n-type semiconductor layer 205 area crystalline semiconductor layer.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: November 28, 2017
    Assignees: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Toshihiro Kamei, Ryohei Takei, Masahiko Mori, Youichi Sakakibara, Junichi Fujikata
  • Patent number: 9818901
    Abstract: A photovoltaic device and method for fabrication include multijunction cells, each cell having a material grown independently from the other and including different band gap energies. An interface is disposed between the cells and configured to wafer bond the cells wherein the cells are configured to be adjacent without regard to lattice mismatch.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: November 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Cheng-Wei Cheng, Jeehwan Kim, Devendra K. Sadana, Kuen-Ting Shiu, Norma E. Sosa Cortes
  • Patent number: 9818902
    Abstract: Disclosed are a solar cell and a method for manufacturing the same. The solar cell includes a substrate, a back electrode layer on the substrate, a light absorbing layer on the back electrode layer, a buffer layer on the light absorbing layer, and a window layer on the buffer layer. The buffer layer is formed through a chemical equation of (AxZn1-x)O(0?x?1), in which the A represents a metallic element.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: November 14, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Chin Woo Lim
  • Patent number: 9806211
    Abstract: A photosensitive device and method includes a top cell having an N-type layer, a P-type layer and a top intrinsic layer therebetween. A bottom cell includes an N-type layer, a P-type layer and a bottom intrinsic layer therebetween. The bottom intrinsic layer includes a Cu—Zn—Sn containing chalcogenide.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: October 31, 2017
    Assignee: International Business Machines Corporation
    Inventors: Oki Gunawan, Jeehwan Kim, David B. Mitzi, Devendra K. Sadana, Teodor K. Todorov
  • Patent number: 9799852
    Abstract: Provided is an organic light emitting diode including a substrate, a light scattering structure including nano-structures on the substrate, a thin film on the nano-structures, and an air gap between the nano-structures, a planarizing layer covering the thin film and thicker than the thin film, a first electrode on the planarizing layer, an organic emission layer on the first electrode, and a second electrode on the organic emission layer.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: October 24, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jin Wook Shin, Jonghee Lee, Jeong Ik Lee, Hyunsu Cho, Jun-Han Han, Jaehyun Moon, Nam Sung Cho, Doo-Hee Cho
  • Patent number: 9786800
    Abstract: In various embodiments a solar cell may include a solar cell wafer substrate made of silicon having a major share of mono crystalline structure with {111} crystal plane parallel to one wafer edge; a dielectric layer disposed over the backside of solar cell wafer substrate; a plurality of contact openings extending through the dielectric layer to the solar cell wafer substrate; a plurality of metal contacts formed in the plurality of contact openings; and a metal layer disposed over the dielectric layer; wherein the metal layer is electrically coupled to the solar cell wafer substrate by means of the plurality of metal contacts; wherein at least one contact opening of the plurality of contact openings extends non parallel to {111} crystal plane.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: October 10, 2017
    Assignee: SolarWorld Americas Inc.
    Inventors: Harald Hahn, Josh Yaskoff, Chris Stapelmann, Thomas Kranke, Roman Schiepe
  • Patent number: 9780235
    Abstract: A solar cell of the present invention includes a collecting electrode extending in one direction on a first principal surface of a photoelectric conversion section. The collecting electrode includes first and second electroconductive layers in this order from the photoelectric conversion section side, and further includes an insulating layer provided with openings between the electroconductive layers. The first electroconductive layer is covered with the insulating layer, and the second electroconductive layer is partially in conduction with the first electroconductive layer through the openings of the insulating layer. The first electroconductive layer has non-central portions within a range from both ends of the first electroconductive layer, and a central portion between the two non-central portions, in a direction orthogonal to an extending direction of the first electroconductive layer. A density of openings at the central portion is higher than a density of openings at the non-central portion.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: October 3, 2017
    Assignee: KANEKA CORPORATION
    Inventor: Daisuke Adachi
  • Patent number: 9768465
    Abstract: A battery module includes a battery assembly having battery structures arranged side by side, the battery structures each having a battery body and a battery holder, and a pressure application member. Each battery holder has a first surface, a second surface, a projecting portion, which projects from the first surface and has a distal end face, and a receptacle portion recessed in the second surface. The projecting portion of each battery holder is inserted into the receptacle portion of the adjacent battery holder in a state in which the distal end face is free of contact with the adjacent battery holder. Each battery body contacts the adjacent battery body such that at least one of the first and second surfaces of the battery holder, which holds a battery body, is free from contact with the adjacent battery holder.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: September 19, 2017
    Assignee: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Kazuki Maeda, Takayuki Kato, Shintaro Watanabe, Hidefumi Oishi, Takashi Sakai, Hiromi Ueda, Naoto Morisaku
  • Patent number: 9768339
    Abstract: Optoelectronic detectors having one or more dilute nitride layers on substrates with lattice parameters matching or nearly matching GaAs are described herein. A semiconductor can include a substrate with a lattice parameter matching or nearly matching GaAs and a first doped III-V layer over the substrate. The semiconductor can also include an absorber layer over the first doped III-V layer, the absorber layer having a bandgap between approximately 0.7 eV and 0.95 eV and a carrier concentration less than approximately 1×1016 cm?3 at room temperature. The semiconductor can also include a second doped III-V layer over the absorber layer.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: September 19, 2017
    Assignee: IQE, plc
    Inventors: Robert Yanka, Seokjae Chung, Kalyan Nunna, Rodney Pelzel, Howard Williams
  • Patent number: RE46739
    Abstract: To provide a photoelectric conversion device having a high photoelectric conversion efficiency, a photoelectric conversion device 21 includes a substrate 1, a plurality of lower electrodes 2 on the substrate 1 comprising a metal element, a plurality of photoelectric conversion layers 33 comprising a chalcogen compound semiconductor formed on the plurality of lower electrodes 2 and separated from one another on the lower electrodes 2, a metal-chalcogen compound layer 8 comprising the metal element and a chalcogen element included in the chalcogen compound semiconductor formed between the lower electrode 2 and the photoelectric conversion layer 33, an upper electrode 5 formed on the photoelectric conversion layer 33, and a connection conductor 7 electrically connecting, in a plurality of the photoelectric conversion layers 33, the upper electrode 5 to the lower electrode 2 without interposition of the metal-chalcogen compound layer 8.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: February 27, 2018
    Assignee: KYOCERA CORPORATION
    Inventors: Daisuke Nishimura, Toshifumi Sugawara, Ken Nishiura, Norihiko Matsushima, Yosuke Inomata, Hisao Arimune, Tsuyoshi Uesugi