Monolithic Semiconductor Patents (Class 136/249)
  • Patent number: 9613814
    Abstract: A solar cell has a metal contact formed to electrically contact a surface of semiconductor material forming a photovoltaic junction. The solar cell includes a surface region or regions of heavily doped material and the contact comprises a contact metallisation formed over the heavily doped regions to make contact thereto. Surface keying features are located in the semiconductor material into which the metallisation extends to assist in attachment of the metallisation to the semiconductor material.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: April 4, 2017
    Assignee: NEWSOUTH INNOVATIONS PTY LIMITED
    Inventors: Alison Maree Wenham, Martin Andrew Green, Stuart Ross Wenham
  • Patent number: 9608131
    Abstract: A silicon solar cell has doped amorphous silicon contacts formed on a tunnel silicon oxide layer on a surface of a silicon substrate. High temperature processing is unnecessary in fabricating the solar cell.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: March 28, 2017
    Assignee: SunPower Corporation
    Inventor: Peter John Cousins
  • Patent number: 9583668
    Abstract: The invention provides a method for increasing the usable surface area of a semiconductor wafer having a substantially planar surface and a thickness dimension at right angles to said substantially planar surface, the method including the steps of selecting a strip thickness for division of the wafer into a plurality of strips, selecting a technique for cutting the wafer into the strips at an angle to the substantially planar surface, in which the combined strip thickness and width of wafer removed by the cutting is less than the thickness of the wafer, cutting the wafer into strips using the selected technique and separating the strips from each other.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: February 28, 2017
    Assignee: The Australian National University
    Inventors: Klaus Johannes Weber, Andrew William Blakers
  • Patent number: 9581742
    Abstract: The disclosure is directed to an element that is capable of acting as both an optical polarizer and an optical attenuator, thus integrating both functions into a single element. The element comprises a monolithic or one piece glass polarizer (herein also call the “substrate”), a multilayer “light attenuation or light attenuating” (“LA”) coating that has been optimized for use at selected wavelengths and attenuations deposited on at least one polarizer facial surface, and a multilayer anti-reflective (AR) coating on top of the LA coating. The disclosure is further directed to an integrated optical isolator/attenuator comprising a first and a second polarizing elements and a Faraday rotator for rotating light positioned after the first polarizing element and before the second polarizing element, the integrated optical isolator/attenuator both polarizing and attenuation a light beam from a light source.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: February 28, 2017
    Assignee: Corning Incorporated
    Inventors: Rachid Gafsi, Jue Wang
  • Patent number: 9559228
    Abstract: Solar cells with doped groove regions separated by ridges and methods of fabricating solar cells are described. In an example, a solar cell includes a substrate having a surface with a plurality of grooves and ridges. A first doped region of a first conductivity type is disposed in a first of the grooves. A second doped region of a second conductivity type, opposite the first conductivity type, is disposed in a second of the grooves. The first and second grooves are separated by one of the ridges.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: January 31, 2017
    Assignee: SunPower Corporation
    Inventors: Steven Edward Molesa, Thomas Pass, Steve Kraft
  • Patent number: 9548409
    Abstract: A silicon solar cell has doped amorphous silicon contacts formed on a tunnel silicon oxide layer on a surface of a silicon substrate. High temperature processing is unnecessary in fabricating the solar cell.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: January 17, 2017
    Assignee: SunPower Corporation
    Inventor: Peter John Cousins
  • Patent number: 9530920
    Abstract: A photoelectric conversion device which is a semiconductor device comprising a first conductive layer having a first conductivity type; a second conductive layer formed on the first conductive layer and having a second conductivity type; and a photosensitizing layer formed between the first conductive layer and the second conductive layer, wherein charge carriers generated by photoelectric conversion in the photosensitizing layer are freely movable to at least one of the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: December 27, 2016
    Assignee: National University Corporation Chiba University
    Inventors: Akihiko Yoshikawa, Yoshihiro Ishitani, Kazuhide Kusakabe
  • Patent number: 9530911
    Abstract: In one aspect, optoelectronic devices are described herein. In some implementations, an optoelectronic device comprises a photovoltaic cell. The photovoltaic cell comprises a space-charge region, a quasi-neutral region, and a low bandgap absorber region (LBAR) layer or an improved transport (IT) layer at least partially positioned in the quasi-neutral region of the cell.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 27, 2016
    Assignee: THE BOEING COMPANY
    Inventors: Richard R. King, Christopher M. Fetzer, Daniel C. Law, Xing-Quan Liu, William D. Hong, Kenneth M. Edmondson, Dimitri D. Krut, Joseph C. Boisvert, Nasser H. Karam
  • Patent number: 9530915
    Abstract: A solar panel of the present invention, above which pointers mounted on a pointer shaft inserted into a through hole provided at the center of the solar panel move, includes a center cell circularly formed around the through hole and a plurality of outer-circumferential cells formed around the outer periphery of the center cell in a manner to have substantially same light-receiving areas. The center cell is formed to have a light-receiving area larger than the light-receiving area of each outer-circumferential cell, taking into consideration a light-shielding area where the pointers overlap with the center cell. Therefore, even though the pointers always overlap with the center cell and part of the pointers overlaps with one of the plurality of outer-circumferential cells, the fluctuation of each light-receiving area of the center cell and the plurality of outer-circumferential cells due to this overlap can be minimized.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: December 27, 2016
    Assignee: CASIO COMPUTER CO., LTD.
    Inventor: Yuta Saito
  • Patent number: 9529331
    Abstract: A solar cell module includes a first segment as a first solar cell segment and a second segment as a second solar cell segment disposed adjacent to each other, and each having electrodes respectively on both of obverse and reverse sides, and a conductive member including a base member having flexibility, a first conductive layer disposed on one surface of the base member, and a second conductive layer disposed on the other surface of the base member, and the base member is bent so as to connect the first conductive layer to the obverse side electrode of the first segment, and connect the second conductive layer to the reverse side electrode of the first segment and the obverse side electrode of the second segment.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: December 27, 2016
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Daisuke Nagano
  • Patent number: 9523880
    Abstract: A transparent conductive film includes a transparent substrate, an undercoat layer, and a transparent conductive layer. The undercoat layer has a refractive index of from 1.5 to 2.0, which is higher than a refractive index of the transparent substrate and lower than a refractive index of the transparent conductive layer. The undercoat layer includes a refractive material having a refractive index of 2.0 or greater in an amount of 40 wt. % or less. The undercoat layer satisfies: X (Si30)/X (C30)?0.28??(1) X (Si40)/X (C40)?0.23??(2) where X (Si30) and X (C30) are silicon and carbon atom contents in a portion of 30 nm or less in thickness from the transparent conductive layer. X (Si40) and X (C40) are silicon and carbon atom contents in a portion of 40 nm or more in thickness from the transparent conductive layer.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: December 20, 2016
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventors: Seiji Takizawa, Yutaka Ito
  • Patent number: 9508881
    Abstract: A microsystems-enabled multi-junction photovoltaic (MEM-PV) cell includes a first photovoltaic cell having a first junction, the first photovoltaic cell including a first semiconductor material employed to form the first junction, the first semiconductor material having a first bandgap. The MEM-PV cell also includes a second photovoltaic cell comprising a second junction. The second photovoltaic cell comprises a second semiconductor material employed to form the second junction, the second semiconductor material having a second bandgap that is less than the first bandgap, the second photovoltaic cell further comprising a first contact layer disposed between the first junction of the first photovoltaic cell and the second junction of the second photovoltaic cell, the first contact layer composed of a third semiconductor material having a third bandgap, the third bandgap being greater than or equal to the first bandgap.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: November 29, 2016
    Assignee: Sandia Corporation
    Inventors: Anna Tauke-Pedretti, Jeffrey Cederberg, Gregory N. Nielson, Murat Okandan, Jose Luis Cruz-Campa
  • Patent number: 9508888
    Abstract: A solar cell is provided with: a semiconductor substrate; an insulating layer formed of a silicon compound or a metal compound, and having a predetermined pattern over the substrate; and a surface covering layer formed of an amorphous semiconductor, having a same pattern as the insulating layer, and that directly contacts the insulating layer.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: November 29, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Sumito Shimizu, Tomohiro Saitou
  • Patent number: 9493358
    Abstract: A photovoltaic module and its manufacturing method. The module includes a sintered silicon support including several integrated photovoltaic cells.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: November 15, 2016
    Assignee: STile
    Inventors: Alain Straboni, Emmanuel Turlot
  • Patent number: 9496296
    Abstract: The present disclosure is directed to optically-tuned electronic components including one or more layers of photosensitive semiconductive materials. In some embodiments, an optically-tuned electronic component includes a plurality of device layers have different bandgap characteristics. One or more selected layers can be optically activated (i.e. made substantially conductive) by illuminating at least a portion of each selected layer with illumination having a wavelength shorter than or substantially equal to the activation wavelength of each selected layer. Accordingly, various parameters can be tuned or a circuit can be switched between alternative paths by providing one or more selected wavelengths of illumination.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: November 15, 2016
    Assignee: Rockwell Collins, Inc.
    Inventors: Don L. Landt, Bryan S. McCoy
  • Patent number: 9484198
    Abstract: A method for physical vapor deposition of an aluminum nitride film, comprising: positioning a substrate and an aluminum target in a chamber; vacuuming the chamber so that a chamber pressure is at a base pressure between 7.1×10?7-5×10?6 torr; conducting a working gas composed of argon gas and nitrogen gas into the chamber so that the chamber pressure is at a working pressure between 3-7 mtorr; and depositing the aluminum nitride film on the substrate by applying a high power impulse power supply to the aluminum target and applying a direct current bias power supply to the substrate under the working pressure and a substrate temperature between room temperature (25° C.) to 200° C.; wherein a power of the high power impulse power supply is between 500-600 W and a frequency thereof is between 750-1250 Hz, and a bias of the direct current bias power supply is between ?50-0 V.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: November 1, 2016
    Assignee: Ming Chi University of Technology
    Inventors: Chen-Te Chang, Yung-Chin Yang, Jyh-Wei Lee
  • Patent number: 9468993
    Abstract: A method for producing a semiconductor device includes laser welding to bond an upper terminal and a lower terminal as internal wiring members of the semiconductor device. When the upper terminal is fixed to the lower terminal by the laser welding, a gap between an upper surface of the lower terminal and a lower surface of the upper terminal is equal to or more than 20 ?m and equal to or less than 400 ?m.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: October 18, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Toshiyuki Miyasaka, Yuta Tamai
  • Patent number: 9455242
    Abstract: A semiconductor optoelectronic device comprises a growth substrate; a semiconductor epitaxial stack formed on the growth substrate comprising a sacrificial layer with electrical conductivity formed on the growth substrate; a first semiconductor material layer having a first electrical conductivity formed on the sacrificial layer, and a second semiconductor material layer having a second electrical conductivity formed on the first semiconductor material layer; and a first electrode directly formed on the growth substrate and electrically connected to the semiconductor epitaxial stack via the growth substrate.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: September 27, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Hsin-Ying Wang, Yi-Ming Chen, Tzu-Chieh Hsu, Chi-Hsing Chen, Chien-Kai Chung, Min-Hsun Hsieh, Chia-Liang Hsu, Chao-Hsing Chen, Chiu-Lin Yao, Chien-Fu Huang, Hsin-Mao Liu, Hsiang-Ling Chang
  • Patent number: 9450132
    Abstract: An object is to increase conversion efficiency of a photoelectric conversion device without increase in the manufacturing steps. The photoelectric conversion device includes a first semiconductor layer formed using a single crystal semiconductor having one conductivity type which is formed over a supporting substrate, a buffer layer including a single crystal region and an amorphous region, a second semiconductor layer which includes a single crystal region and an amorphous region and is provided over the butler layer, and a third semiconductor layer having a conductivity type opposite to the one conductivity type, which is provided over the second semiconductor layer. A proportion of the single crystal region is higher than that of the amorphous region on the first semiconductor layer side in the second semiconductor layer, and the proportion of the amorphous region is higher than that of the single crystal region on the third semiconductor layer side.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: September 20, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Sho Kato, Yoshikazu Hiura, Akihisa Shimomura, Takashi Ohtsuki, Satoshi Toriumi, Yasuyuki Arai
  • Patent number: 9450123
    Abstract: A design of a quantum well region that allows faster and more efficient carrier collection in quantum well solar cells. It is shown that for a quantum well material system displaying a negligible valence band offset, the conduction band confinement energies and barrier thicknesses can be designed to favor a sequential thermionic promotion and resonant tunneling of electrons to the conduction band continuum resulting in faster carrier collection rates than for a conventional design. An evaluation of the proposed design in the context of devices incorporating GaAs/GaAsN quantum wells shows a collection of all photo-generated carriers within several to tenths of ps (10?12 s) from deep quantum wells rather than several ns, as it is the case for conventional designs. The incorporation of the proposed design in single and multijunction solar cells is evaluated with efficiency enhancements.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: September 20, 2016
    Assignee: The University of Houston System
    Inventors: Alexandre Freundlich, Andenet Alemu
  • Patent number: 9444000
    Abstract: A solar cell is provided with: a first conductivity layer comprising a first conductivity type material; a sensitizer layer formed on the first conductivity layer; and a second conductivity layer comprising a second conductivity type material and formed on the sensitizer layer. At least one of the first conductivity layer, the second conductivity layer and the sensitizer layer has a first semiconductor of a first film thickness and a second semiconductor of a second film thickness.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: September 13, 2016
    Assignee: NATIONAL UNIVERSITY CORPORATION CHIBA UNIVERSITY
    Inventors: Akihiko Yoshikawa, Yoshihiro Ishitani, Kazuhide Kusakabe
  • Patent number: 9437753
    Abstract: A device includes a conductive surface (12) and electrical contacts (14) by which an electric current is able to be passed. The electrical contacts (14) include conductive seeds (16) deposited on the conductive surface (12), an electrically insulating layer (18), which covers discontinuously the conductive seeds (16) in order to form openings leaving access to the conductive seeds (16), and a plating layer (22) recovering the discontinuous insulating layer (18) and deposited on conductive seeds (16) which are accessible through the openings and form points from which the deposit of the plating layer (22) can start. The rest of the conductive surface (12), which doesn't include any electrical contacts (14), is continuously covered by the electrically insulating layer (18).
    Type: Grant
    Filed: October 11, 2010
    Date of Patent: September 6, 2016
    Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL) EPFL-TTO
    Inventor: Christophe Ballif
  • Patent number: 9425420
    Abstract: Tandem electro-optic devices and active materials for electro-optic devices are disclosed. Tandem devices include p-type and n-type layers between the active layers, which are doped to achieve carrier tunneling. Low bandgap conjugated polymers are also disclosed.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: August 23, 2016
    Assignee: The Regents of the University of California
    Inventors: Yang Yang, Letian Dou, Jing-Bi You
  • Patent number: 9418844
    Abstract: A multi-junction solar cell is provided and includes multiple semiconducting layers and an interface layer disposed between the multiple semiconducting layers. The interface layer is made from an interface bonding material that has a refractive index such that a ratio of a refractive index of each of the multiple semiconducting layers to the refractive index of the interface bonding material is less than or equal to 1.5.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: August 16, 2016
    Assignee: United States of America as Represented by the Administrator of National Aeronautics and Space Administration
    Inventor: Geoffrey A. Landis
  • Patent number: 9397242
    Abstract: The present invention addresses the problem of providing a novel silicon substrate having a textured surface by dry-etching the surface of a silicon substrate having (111) orientation and thereby forming a texture thereon. The present invention provides a silicon substrate having (111) orientation, said silicon substrate having a textured surface that includes multiple protrusions which each comprise three slant faces and have heights of 100 to 8000 nm. This process for producing a silicon substrate includes: a step of preparing a silicon substrate having (111) orientation; and a step of blowing an etching gas onto the surface of the silicon substrate, said etching gas containing one or more gases selected from the group consisting of ClF3, XeF2, BrF3, BrF5 and NF3.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: July 19, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yasushi Taniguchi, Shigeru Sankawa, Sr., Kouji Arai, Hiroshi Tanabe, Ichiro Nakayama, Naoshi Yamaguchi
  • Patent number: 9391180
    Abstract: Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. An interfacial intrinsic non-crystalline semiconductor material layer is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. The presence of the interfacial intrinsic non-crystalline semiconductor material layer improves the surface passivation of the crystalline semiconductor material by reducing the interface defect density at the heterojunction.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: July 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Bahman Hekmatshoar-Tabari, Tak H. Ning, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 9373741
    Abstract: A photovoltaic device that includes an upper cell that absorbs a first range of wavelengths of light and a bottom cell that absorbs a second range of wavelengths of light. The bottom cell includes a heterojunction comprising a crystalline germanium containing (Ge) layer. At least one surface of the crystalline germanium (Ge) containing layer is in contact with a silicon (Si) containing layer having a larger band gap than the crystalline (Ge) containing layer.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: June 21, 2016
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 9373729
    Abstract: Provided is a solar cell. The solar cell includes: a substrate including through lines opposing to each other; a semiconductor layer on a top side of the substrate; bus lines at both edges of a top side of the semiconductor layer; and bus bars connected electrically to the bus lines, respectively, and extending to a rear side of the substrate through the through lines.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: June 21, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Myoung Seok Sung, Se Han Kwon
  • Patent number: 9368671
    Abstract: A method of fabricating on a semiconductor substrate bifacial tandem solar cells with semiconductor subcells having a lower bandgap than the substrate bandgap on one side of the substrate and with subcells having a higher bandgap than the substrate on the other including, first, growing a lower bandgap subcell on one substrate side that uses only the same periodic table group V material in the dislocation-reducing grading layers and bottom subcells as is present in the substrate and after the initial growth is complete and then flipping the substrate and growing the higher bandgap subcells on the opposite substrate side which can be of different group V material.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: June 14, 2016
    Assignee: MASIMO SEMICONDUCTOR, INC.
    Inventors: Steven J. Wojtczuk, Philip T. Chiu, Xuebing Zhang, Edward Gagnon, Michael Timmons
  • Patent number: 9356176
    Abstract: A multijunction solar cell having at least four solar subcells includes a first solar subcell having a first band gap. A first graded interlayer adjacent to the first solar subcell and has a second band gap greater than the first band gap and that is constant at 1.5 eV throughout the thickness of the first graded interlayer. A second solar subcell is adjacent to the first graded interlayer and has a third band gap smaller than the first band gap of the first solar subcell. The second solar subcell is lattice mismatched with respect to the first solar subcell. A second graded interlayer is adjacent to the second solar subcell and has a fourth band gap greater than the third band gap of the second solar subcell and that is constant at 1.1 eV throughout the thickness of the second graded interlayer. A third solar subcell is adjacent to the second graded interlayer and has a fifth band gap smaller than the third band gap of the second solar subcell.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: May 31, 2016
    Assignee: SolAero Technologies Corp.
    Inventors: Arthur Cornfeld, Pravin Patel, Mark A. Stan, Benjamin Cho, Paul R. Sharps, Daniel J. Aiken, John Spann
  • Patent number: 9343602
    Abstract: The present invention provides a solar cell unit, which comprises a semiconductor plate of first-type doping or second-type doping; wherein the semiconductor plate has a first surface and a second surface opposite to the first surface; the semiconductor plate comprises a first-type doping region and second-type doping region, both the first-type doping region and the second-type doping region are located on the first surface of the semiconductor plate; a first sheet is provided on the side surface of the semiconductor plate that is adjacent to the first-type doping region, and a second sheet is provided on the side surface of the semiconductor plate that is adjacent to the second type doping region.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: May 17, 2016
    Inventors: Zhijiong Luo, Huilong Zhu, Haizhou Yin
  • Patent number: 9324886
    Abstract: A solar cell and a method of manufacturing the same are disclosed. The solar cell includes a substrate, at least one emitter layer on the substrate, at least one first electrode electrically connected to the at least one emitter layer, and at least one second electrode electrically connected to the substrate. At least one of the first electrode and the second electrode is formed using a plating method.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: April 26, 2016
    Assignee: LG ELECTRONICS INC.
    Inventors: Sunho Kim, Heonmin Lee, Kwangsun Ji, Youngjoo Eo, Junghoon Choi, Sehwon Ahn
  • Patent number: 9287431
    Abstract: Voltage-matched thin film multijunction solar cell and methods of producing cells having upper CdTe pn junction layers formed on a transparent substrate which in the completed device is operatively positioned in a superstate configuration. The solar cell also includes a lower pn junction formed independently of the CdTe pn junction and an insulating layer between CdTe and lower pn junctions. The voltage-matched thin film multijunction solar cells further include a parallel connection between the CdTe pn junction and lower pn junctions to form a two-terminal photonic device. Methods of fabricating devices from independently produced upper CdTe junction layers and lower junction layers are also disclosed.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: March 15, 2016
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Angelo Mascarenhas, Kirstin Alberi
  • Patent number: 9276163
    Abstract: Disclosed is a method for manufacturing a crystalline silicon-based photoelectric conversion device having a first intrinsic silicon-based layer, a p-type silicon-based layer and a first transparent electroconductive layer, positioned in this order on one surface of a conductive single-crystal silicon substrate, and having a second intrinsic silicon-based layer, an n-type silicon-based layer and a second transparent electroconductive layer, positioned in this order on the other surface of the conductive single-crystal silicon substrate. In the present invention, a heat treatment is carried out after at least one of the transparent electroconductive layers is formed. This heat treatment is carried out at a temperature of less than 200° C. under a hydrogen-containing atmosphere.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: March 1, 2016
    Assignee: KANEKA CORPORATION
    Inventors: Toshihiko Uto, Takashi Kuchiyama, Daisuke Adachi, Kenji Yamamoto
  • Patent number: 9249016
    Abstract: This disclosure relates to structures for the conversion of light into energy. More specifically, the disclosure describes devices for conversion of light to electricity using photovoltaic cells comprising graphene.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: February 2, 2016
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Adrianus I. Aria, Morteza Gharib
  • Patent number: 9251965
    Abstract: A wet-type solar battery including a support composed of a light transmissive material and a stack in which a conductive layer, a photoelectric conversion layer containing a porous semiconductor, a porous insulating layer, and a counter electrode conductive layer are stacked in this order is provided. The conductive layer is divided into a first region including a portion where the photoelectric conversion layer is to be formed on a surface thereof and a second region where the photoelectric conversion layer is not to be formed. A protection film for preventing internal short-circuiting, which is not greater in film thickness than the photoelectric conversion layer, is formed in at least a part around the photoelectric conversion layer on the surface of the first region.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: February 2, 2016
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kei Ogiya, Atsushi Fukui, Ryoichi Komiya, Ryohsuke Yamanaka
  • Patent number: 9246033
    Abstract: A photovoltaic device and method include a substrate coupled to an emitter side structure on a first side of the substrate and a back side structure on a side opposite the first side of the substrate. The emitter side structure or the back side structure include layers alternating between wide band gap layers and narrow band gap layers to provide a multilayer contact with an effectively increased band offset with the substrate and/or an effectively higher doping level over a single material contact. An emitter contact is coupled to the emitter side structure on a light collecting end portion of the device. A back contact is coupled to the back side structure opposite the light collecting end portion.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: January 26, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoar-Tabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 9240499
    Abstract: A solar cell is discussed. The solar cell includes a substrate of a first conductive type, an emitter region which is positioned at a front surface of the substrate and has a second conductive type different from the first conductive type, a front passivation region including a plurality of layers which are sequentially positioned on the emitter region, a back passivation region which is positioned on a back surface opposite the front surface of the substrate and includes three layers, a plurality of front electrodes which pass through the front passivation region and are connected to the emitter region, and at least one back electrode which passes through the back passivation region and is connected to the substrate.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: January 19, 2016
    Assignee: LG ELECTRONICS INC.
    Inventors: Juhwa Cheong, Yiyin Yu, Youngsung Yang, Yongduk Jin, Manhyo Ha, Seongeun Lee
  • Patent number: 9236610
    Abstract: Disclosed is a lithium secondary battery, which is low in capacity loss after overdischarge, having excellent capacity restorability after overdischarge and shows an effect of preventing a battery from swelling at a high temperature.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: January 12, 2016
    Assignee: LG CHEM, LTD.
    Inventors: Sung Kyun Chang, Seung Tae Hong, Hyeong Jin Kim, Duk Hyun Ryu, Eun Young Goh, Ho Chun Lee, Jun Yong Jeong, Jin Hee Yeon, Hyung Keun Lee
  • Patent number: 9231135
    Abstract: Low bandgap, monolithic, multi-bandgap, optoelectronic devices (10), including PV converters, photodetectors, and LED's, have lattice-matched (LM), double-heterostructure (DH), low-bandgap GaInAs(P) subcells (22, 24) including those that are lattice-mismatched (LMM) to InP, grown on an InP substrate (26) by use of at least one graded lattice constant transition layer (20) of InAsP positioned somewhere between the InP substrate (26) and the LMM subcell(s) (22, 24). These devices are monofacial (10) or bifacial (80) and include monolithic, integrated, modules (MIMs) (190) with a plurality of voltage-matched subcell circuits (262, 264, 266, 270, 272) as well as other variations and embodiments.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: January 5, 2016
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Mark W. Wanlass, Jeffrey J. Carapella
  • Patent number: 9231130
    Abstract: Provided is a photoelectric conversion element that has an nip structure formed of amorphous silicon and that is improved in energy conversion efficiency by a structure in which an n+-type a-Si layer is in contact with a transparent electrode formed by an n+-type ZnO layer. This makes it possible to realize photoelectric conversion elements and a solar cell module or facility with large area and high power with an influence on the global resources minimized.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: January 5, 2016
    Assignee: National University Corporation Tohoku University
    Inventor: Tadahiro Ohmi
  • Patent number: 9214588
    Abstract: The present invention is directed toward a dual junction photodiode semiconductor devices with improved wavelength sensitivity. The photodiode employs a high quality n-type layer with relatively lower doping concentration and enables high minority carrier lifetime and high quantum efficiency with improved responsivity at multiple wavelengths. In one embodiment, the photodiode comprises a semiconductor substrate of a first conductivity type, a first impurity region of a second conductivity type formed epitaxially in the semiconductor substrate, a second impurity region of the first conductivity type shallowly formed in the epitaxially formed first impurity region, a first PN junction formed between the epitaxially formed first impurity region and the second impurity region, a second PN junction formed between the semiconductor substrate and the epitaxially formed first impurity region, and at least one passivated V-groove etched into the epitaxially formed first impurity region and the semiconductor substrate.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: December 15, 2015
    Assignee: OSI Optoelectronics, Inc.
    Inventors: Peter Steven Bui, Narayan Dass Taneja, Manoocher Mansouri Aliabadi
  • Patent number: 9214587
    Abstract: A photoelectric conversion module in which an output voltage defect is suppressed is obtained by forming in parallel over a substrate n number (n is a natural number) of integrated photoelectric conversion devices each including a plurality of cells that are connected in series, and electrically connecting in parallel n?1 number or less of integrated photoelectric conversion devices with normal electrical characteristics and excluding an integrated photoelectric conversion device with a characteristic defect such as a short-circuit between top and bottom electrodes or a leak current due to a structural defect or the like formed in a semiconductor layer or the like.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: December 15, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuo Nishi, Yasushi Maeda, Ryosuke Motoyoshi, Yuji Oda, Kei Takahashi, Yoshiaki Ito, Tatsuji Nishijima
  • Patent number: 9209335
    Abstract: A solar cell system includes two solar cells. The two solar cells are located in contact with each other and connected in parallel. Each of the two solar cells includes a first electrode layer, a P-type silicon layer, an N-type silicon layer, and a second electrode layer. The first electrode layer, the P-type silicon layer, the N-type silicon layer, and the second electrode layer are arranged in series side by side along a first direction and in contact with each other, thereby cooperatively forming a integrated structure. A P-N junction is formed near an interface between the P-type silicon layer and the N-type silicon layer. The integrated structure has a first surface substantially parallel to the first direction and a second surface opposite to the first surface. The first surface is used as a photoreceptive surface to directly receive incident light.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: December 8, 2015
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yuan-Hao Jin, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 9209345
    Abstract: Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor layer having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor layer and positioned to interact with electromagnetic radiation. The textured region can be formed from a series of shallow trench isolation features.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: December 8, 2015
    Assignee: SiOnyx, Inc.
    Inventors: Homayoon Haddad, Jutao Jiang
  • Patent number: 9203052
    Abstract: An organic light emitting diode (OLED) device is disclosed. In one embodiment, the OLED device includes: i) a substrate and ii) a first thin film formed on the substrate, wherein the first thin film comprises first and second surfaces opposing each other, wherein the first surface contacts the substrate, and wherein a plurality of protrusions and depressions are alternately formed on the second surface of the first thin film. The OLED device may further include a second thin film formed on the protrusions and depressions of the first thin film, a first electrode formed on the second thin film, a light emitting member formed on the first electrode and a second electrode formed on the organic light emitting member.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: December 1, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sung-Hun Lee, Gwan-Hyoung Lee, Chang-Woong Chu, Young-Gu Ju
  • Patent number: 9190561
    Abstract: A semiconductor light emitting element includes an n-type semiconductor layer containing n-type impurities, a light emitting layer stacked on the n-type semiconductor layer, and a p-type semiconductor layer stacked on the light emitting layer and containing p-type impurities. The light emitting layer includes three or more well layers, and four or more barrier layers composed of a group-III nitride semiconductor having a larger band gap than that of the well layers, and each of the three or more well layers is sandwiched from both sides by neighboring two of the barrier layers. The three or more well layers include plural n-side well layers each having a first thickness to emit light of a common wavelength, and one or plural p-side well layers each having a second thickness larger than the first thickness and having a different composition from the n-side well layers to emit light of the common wavelength.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: November 17, 2015
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Shunsuke Teranishi, Hisao Sato
  • Patent number: 9190542
    Abstract: The efficiency of a photovoltaic cell is enhanced by light trapping using Mie-scattering nanostructures. In one embodiment, an array of nanocylinders is formed on the front surface of a silicon film to enhance forward scattering into the film, and an array of nanocylinders is formed on the back surface to enhance backscattering so that more light is absorbed within the silicon film. In an alternate embodiment, a mirror layer is formed on the back surface of the silicon film to reflect light within the film back toward the front-surface nanocylinder array.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: November 17, 2015
    Assignee: Sandia Corporation
    Inventors: Igal Brener, Nche Tumasang Fofang, Ting S. Luk
  • Patent number: 9184329
    Abstract: A photoelectric conversion device is disclosed. The photoelectric conversion device includes an electrode layer and a semiconductor layer. The semiconductor layer is located on the electrode layer and contains a group I-III-VI compound. In the semiconductor layer, an atomic ratio of a group I-B element to a group III-B element decreases from one principal surface side of the semiconductor layer on the electrode layer side to a central portion in a thickness direction and increases from the central portion to another principal surface side on a side opposite to the electrode layer.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: November 10, 2015
    Assignee: KYOCERA Corporation
    Inventors: Shinichi Abe, Akio Yamamoto, Seiji Oguri, Kazumasa Umesato
  • Patent number: 9171979
    Abstract: A solar battery according to the embodiment of the present invention includes a rear electrode formed on a substrate and separated by a first through-hole; a light absorbing layer formed on the rear electrode including the first through-hole; a second through-hole exposing the rear electrode through the light absorbing layer; a buffer layer formed on the upper surface and the side surface of the light absorbing layer; a front electrode layer formed on the buffer layer; and a connection wiring extending from the front electrode layer and formed within the second through-hole.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: October 27, 2015
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Chin Woo Lim