Schottky, Graded Doping, Plural Junction Or Special Junction Geometry Patents (Class 136/255)
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Patent number: 12132058Abstract: A method for manufacturing a data line includes: forming a conductive layer on a substrate; forming a photoresist layer on a side of the conductive layer away from the substrate; exposing and then developing the photoresist layer to form a groove penetrating the photoresist layer, thus obtaining a patterned photoresist layer; and depositing a functional material electrochemically on the patterned photoresist layer, then removing the patterned photoresist layer to obtain the conductive layer with the patterned functional material layer, thereby obtaining the data line.Type: GrantFiled: July 23, 2021Date of Patent: October 29, 2024Assignees: BEIHAI HKC OPTOELECTRONICS TECHNOLOGY CO., LTD., HKC CORPORATION LIMITEDInventors: Yuming Xia, En-Tsung Cho, Lidan Ye
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Patent number: 12132129Abstract: Disclosed herein are methods for using cracked film lithography (CFL) for patterning transparent conductive metal grids. CFL can be vacuum- and Ag-free, and it forms more durable grids than nanowire approaches.Type: GrantFiled: February 15, 2021Date of Patent: October 29, 2024Assignee: Alliance for Sustainable Energy, LLCInventors: Christopher Paul Muzzillo, Matthew Owen Reese
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Patent number: 12100753Abstract: Gated MIS tunnel diode devices having a controllable negative transconductance behavior are provided. In some embodiments, a device includes a substrate, a tunnel diode dielectric layer on a surface of the substrate, and a gate dielectric layer on the surface of the substrate and adjacent to the tunnel diode dielectric layer. A tunnel diode electrode is disposed on the tunnel diode dielectric layer, and a gate electrode is disposed on the gate dielectric layer. A substrate electrode is disposed on the surface of the substrate, and the tunnel diode electrode is positioned between the gate electrode and the substrate electrode.Type: GrantFiled: July 28, 2023Date of Patent: September 24, 2024Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan UniversityInventors: Jenn-Gwo Hwu, Chien-Shun Liao
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Patent number: 12094946Abstract: A device includes a nanostructure, a gate dielectric layer, a gate electrode, and a gate contact. The nanostructure is over a substrate. The gate dielectric layer laterally surrounds the nanostructure. The gate electrode laterally surrounds the gate dielectric layer. The gate electrode has a bottom surface and a top surface both higher than a bottom end of the nanostructure. The gate electrode has a horizontal dimension decreasing from the bottom surface to the top surface. The gate contact is electrically coupled to the gate electrode.Type: GrantFiled: April 11, 2022Date of Patent: September 17, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yung-Chih Wang, Yu-Chieh Liao, Tai-I Yang, Hsin-Ping Chen
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Patent number: 12087872Abstract: Embodiments of the present disclosure provide a photovoltaic cell, a method for manufacturing the photovoltaic cell, and a photovoltaic module. The photovoltaic cell includes a substrate, and an emitter and a first passivation structure that are located on a first surface of the substrate, where the emitter is located between the substrate and the first passivation structure; a first electrode, penetrating through the first passivation structure and being in contact with the emitter; and a first eutectic, located between the first electrode and the emitter, where the first eutectic includes a material of the first electrode and a material of the emitter, and a part of the first electrode penetrates through the first eutectic and is in contact with the emitter.Type: GrantFiled: August 16, 2022Date of Patent: September 10, 2024Assignees: ZHEJIANG JINKO SOLAR CO., LTD., JINKO SOLAR CO., LTD.Inventors: Bike Zhang, Xinyu Zhang, Jingsheng Jin
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Patent number: 12080820Abstract: Device structures, apparatuses, and methods are disclosed for photovoltaic cells that may be a single-junction or multijunction solar cells, with at least a first layer comprising a group-IV semiconductor in which part of the cell comprises a second layer comprising a III-V semiconductor or group-IV semiconductor having a different composition than the group-IV semiconductor of the first layer, such that a heterostructure is formed between the first and second layers.Type: GrantFiled: March 28, 2022Date of Patent: September 3, 2024Assignee: THE BOEING COMPANYInventors: Richard R. King, Christopher M. Fetzer, Nasser H. Karam
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Patent number: 12074241Abstract: A photovoltaic cell includes a semiconductor element (20) formed from a direct semiconductor and a transparent biasing agent (28) overlying a first portion of the front face (22) of the semiconductor, the biasing agent producing a first depletion region (30) in the semiconductor element. A collector (40) directly contacts a second portion of the front face. The collector produces a second depletion region (44) in the semiconductor element. The collector (40) is out of direct conductive contact with the biasing agent (28) but in proximity to the biasing agent. A continuous region at least partially depleted of majority carriers extends between the first and second depletion regions at the front face of the semiconductor element. The continuous region may include overlapping portions of the first and second depletion regions (30,44), or may include an additional depletion region (160) formed by a charged dielectric (147).Type: GrantFiled: July 13, 2020Date of Patent: August 27, 2024Assignee: Columbus Photovoltaics LLCInventors: Ian Ferguson, Corey E. Lerner, Chuanle Zhou
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Patent number: 12074232Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type architectures and incorporating a multi-purpose passivation and contact layer, and resulting solar cells, are described. In an example, a solar cell includes a substrate having a light-receiving surface and a back surface. A P-type emitter region is disposed on the back surface of the substrate. An N-type emitter region is disposed in a trench formed in the back surface of the substrate. An N-type passivation layer is disposed on the N-type emitter region. A first conductive contact structure is electrically connected to the P-type emitter region. A second conductive contact structure is electrically connected to the N-type emitter region and is in direct contact with the N-type passivation layer.Type: GrantFiled: November 28, 2016Date of Patent: August 27, 2024Assignee: Maxeon Solar Pte. Ltd.Inventors: Staffan Westerberg, Seung Bum Rim
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Patent number: 12068426Abstract: Device structures, apparatuses, and methods are disclosed for photovoltaic cells that may be a single-junction or multijunction solar cells, with at least a first layer comprising a group-IV semiconductor in which part of the cell comprises a second layer comprising a III-V semiconductor or group-IV semiconductor having a different composition than the group-IV semiconductor of the first layer, such that a heterostructure is formed between the first and second layers.Type: GrantFiled: December 17, 2020Date of Patent: August 20, 2024Assignee: THE BOEING COMPANYInventors: Richard R. King, Christopher M. Fetzer, Nasser H. Karam
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Patent number: 12051669Abstract: A semiconductor device package includes a package substrate having a die attach region, a silicon carbide (SiC) substrate having a first surface including a semiconductor device layer thereon and a second surface that is opposite the first surface, and a die attach metal stack. The die attach metal stack includes a sputtered die attach material layer that attaches the second surface of the SiC substrate to the die attach region of the package substrate, where the sputtered die attach material layer comprises a void percent of about 15% or less. The sputtered die attach material layer may be formed using a sputter gas including at least one of krypton (Kr), xenon (Xe), or radon (Rn). The die attach metal stack may further include a metal interlayer that prevent contacts with a first barrier metal layer during a phase transition of the die attach material layer.Type: GrantFiled: October 6, 2021Date of Patent: July 30, 2024Assignee: Wolfspeed, Inc.Inventors: Alexander Komposch, Kevin Schneider, Scott Sheppard
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Patent number: 12051760Abstract: A multijunction solar cell including an upper first solar subcell having an emitter and base layers forming a photoelectric junction; a second solar subcell disposed under and adjacent to the upper first solar subcell, and having an emitter and base layers forming a photoelectric junction; and a third solar subcell disposed under and adjacent to the second solar subcell and having an emitter and base layers forming a photoelectric junction; wherein at least one of the base and emitter layers of at least a particular solar subcell from among the upper first solar subcell, the second solar subcell, and the third solar subcell has a graded band gap throughout at least a portion of thickness of its active layer adjacent to the photoelectric junction and being in a range of 20 to 300 MeV greater than a band gap in the active layer away from the photoelectric junction.Type: GrantFiled: July 13, 2023Date of Patent: July 30, 2024Assignee: SolAero Technologies Corp.Inventors: John Hart, Daniel Derkacs, Zachary Bittner, Andrew Espenlaub
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Patent number: 12046696Abstract: An optoelectronic semiconductor device comprises an active zone comprising sub-layers for forming a quantum well structure. Differences in energy levels of the quantum well structure are smaller in a central region of the optoelectronic semiconductor device than in an edge region of the optoelectronic semiconductor device. According to further embodiments, an optoelectronic semiconductor device comprises an active zone comprising a sub-layer which is suitable for forming a quantum well structure. In the active zone, quantum dot structures are formed in a central region of the optoelectronic semiconductor device. No quantum dot structures are formed in an edge region of the optoelectronic semiconductor device.Type: GrantFiled: December 18, 2019Date of Patent: July 23, 2024Assignee: OSRAM OPTO SEMICONDUCTORS GMBHInventors: Martin Behringer, Alexander Tonkikh, Tansen Varghese
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Patent number: 12046687Abstract: A method for manufacturing a solar cell, including the steps of: forming unevenness on both of main surfaces of a semiconductor substrate of a first conductivity type; forming a base layer on a first main surface of the semiconductor substrate; forming a diffusion mask on the base layer; removing the diffusion mask in a pattern; forming an emitter layer on the portion of the first main surface where the diffusion mask have been removed; removing the remaining diffusion mask; forming a dielectric film on the first main surface; forming a base electrode on the base layer; and forming an emitter electrode on the emitter layer. This provides a method for manufacturing a solar cell that can bring high photoelectric conversion efficiency while decreasing the number of steps.Type: GrantFiled: October 25, 2016Date of Patent: July 23, 2024Assignee: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Takenori Watabe, Ryo Mitta, Hiroshi Hashigami, Hiroyuki Ohtsuka
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Patent number: 12033811Abstract: The present invention is related to a solar cell comprising a first electrode; a second electrode; and a stack of layers provided between the first electrode and the second electrode; wherein the stack of layers comprises one light absorbing layer provided with a perovskite crystal structure; and at least one dopant layer, wherein the dopant layer consists of one or more n-dopant material(s); or one or more p-dopant material(s).Type: GrantFiled: July 2, 2019Date of Patent: July 9, 2024Assignee: Novaled GmbHInventors: Kay Lederer, Steffen Runge, Hendrik Bolink, Michele Sessolo, Jorge Avila, Maria Grazia La Placa, Pablo B. Boix
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Patent number: 12027639Abstract: A multijunction solar cell including an upper first solar subcell having a first band gap and positioned for receiving an incoming light beam; and a second solar subcell disposed below and adjacent to and lattice matched with said upper first solar subcell, and having a second band gap smaller than said first band gap; wherein at least one of the solar subcells has a graded band gap throughout the thickness of at least a portion of its emitter layer and base layer.Type: GrantFiled: February 8, 2022Date of Patent: July 2, 2024Assignee: SolAero Technologies Corp.Inventors: John Hart, Daniel Derkacs, Zachary Bittner, Andrew Espenlaub
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Patent number: 12009441Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a solar cell can include a substrate having a light-receiving surface and a back surface. A first doped region of a first conductivity type, wherein the first doped region is disposed in a first portion of the back surface. A first thin dielectric layer disposed over the back surface of the substrate, where a portion of the first thin dielectric layer is disposed over the first doped region of the first conductivity type. A first semiconductor layer disposed over the first thin dielectric layer. A second doped region of a second conductivity type in the first semiconductor layer, where the second doped region is disposed over a second portion of the back surface. A first conductive contact disposed over the first doped region and a second conductive contact disposed over the second doped region.Type: GrantFiled: January 20, 2023Date of Patent: June 11, 2024Assignee: Maxeon Solar Pte. Ltd.Inventors: Seung Bum Rim, Michael C. Johnson
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Patent number: 11990555Abstract: The present disclosure provide a solar cell, including: a substrate, an interface passivation layer covering a rear surface of the substrate, and an electrode disposed at a side of the interface passivation layer facing away from the substrate, the interface passivation layer including a first interface passivation sub-layer corresponding to a portion of the interface passivation layer between adjacent electrodes and a second interface passivation sub-layer corresponding to a portion of the interface passivation layer where disposed between the substrate and the electrode; a field passivation layer, at least partially disposed between the interface passivation layer and the electrode; and a conductive enhancement layer, at least partially disposed at a side of the first interface passivation sub-layer away from the substrate to enable carriers in the first interface passivation sub-layer to flow to the electrode, where a resistivity of the conductive enhancement layer is smaller than a resistivity of the fielType: GrantFiled: September 23, 2021Date of Patent: May 21, 2024Assignees: Jinko Green Energy (Shanghai) Management Co., LTD., Zhejiang Jinko Solar Co., Ltd.Inventors: Jingsheng Jin, Bike Zhang, Xinyu Zhang
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Patent number: 11984274Abstract: A three-tandem (3T) perovskite/silicon (PVT)-based tandem solar cell (TSC) includes an antireflection coating (ARC), a first transparent conductive oxide layer (TCO), a hole transport layer (HTL), a perovskite (PVT) layer, a second transparent conductive oxide layer (TCO), an electron transport layer (ETL), a plurality of buried contacts, a p-type Si layer, a p-type wafer-based homo-junction silicon solar cell, a n+ silicon layer, a back contact layer. The solar cell further includes a top sub-cell, a bottom sub-cell and a middle contact-based tandem. The top sub-cell includes the PVT layer. The bottom sub-cell includes the silicon solar cell. The middle contact-based tandem includes the second TCO layer to be used as the middle contact-based tandem, as well as a recombination layer for current collection. Further, a conduction and a valence band edge are employed at a front surface of the ETL.Type: GrantFiled: May 12, 2023Date of Patent: May 14, 2024Assignee: KING FAHD UNIVERSITY OF PETROLEUM AND MINERALSInventor: Firoz Khan
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Patent number: 11973073Abstract: A photovoltaic device includes a first group of photovoltaic cells of a first cell type, the first group of photovoltaic cells operable to produce a first current and a first voltage, and a second group of photovoltaic cells of a second cell type that is different than the first cell type, the second group of photovoltaic cells operable to produce a second current and a second voltage. A first power electronics unit is connected to the first group of photovoltaic cells, and a second power electronics unit is connected to the second group of photovoltaic cells. The second power electronics unit is separate from and not communicating with the first power electronics unit. A control device is operable to vary a first property of the first power electronics unit to vary the first current and the first voltage and to vary a second property of the second power electronics unit to vary the second voltage and the second current independent of the first voltage and the first current.Type: GrantFiled: July 19, 2022Date of Patent: April 30, 2024Assignee: Siemens Energy Global GmbH & Co. KGInventors: Maximilian Fleischer, Armin Schnettler
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Patent number: 11949372Abstract: The present disclosure relates to a transparent luminescent solar concentrator (LSC). The LSC according to an embodiment of the present disclosure includes a polymer resin panel uniformly doped with phosphors. Accordingly, it is possible to greatly improve the transmittance and optical haze compared to the existing LSC manufactured by physically mixing or coating phosphors on the front side of the panel. In addition, it is possible to greatly improve the light collection efficiency of the LSC through the arrangement structure of the solar cells embedded in the polymer resin panel. The polymer resin panel according to an embodiment may be manufactured with flexibility or rigidity according to the purpose of use, and thus can be widely applied to curved structures, for example, building windows, automobile glasses and greenhouse roofs.Type: GrantFiled: May 28, 2020Date of Patent: April 2, 2024Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Gumin Kang, Hyungduk Ko, Ho Seong Jang, Cho-long Jung
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Patent number: 11943941Abstract: The solar cell of the present disclosure includes: a first substrate having light-transmitting properties; a second substrate having light-transmitting properties; a third substrate disposed such that the second substrate is located between the first and third substrates; a first photoelectric conversion layer disposed between the first substrate and the second substrate and containing a perovskite material; a second photoelectric conversion layer disposed between the second substrate and the third substrate; and a pair of electrodes disposed so as to sandwich the first photoelectric conversion layer therebetween in a direction perpendicular to the arrangement direction of the first substrate, the second substrate, and the third substrate.Type: GrantFiled: November 18, 2021Date of Patent: March 26, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hiroko Okumura, Akio Matsushita
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Patent number: 11916159Abstract: A multijunction solar cell including an upper first solar subcell having a first band gap and positioned for receiving an incoming light beam; and a second solar subcell disposed below and adjacent to and lattice matched with said upper first solar subcell, and having a second band gap smaller than said first band gap; wherein at least one of the solar subcells has a graded band gap throughout the thickness of at least a portion of its emitter layer and base layer.Type: GrantFiled: November 14, 2022Date of Patent: February 27, 2024Assignee: SolAero Technologies Corp.Inventors: John Hart, Daniel Derkacs, Zachary Bittner, Andrew Espenlaub
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Patent number: 11908970Abstract: A process for manufacturing a multilayered thin film, includes: forming a photovoltaic conversion layer, comprising Cu2O as a main component, on a first transparent electrode; and placing, under a first atmosphere at an oxygen level of from 5.0×10?8 [g/L] to 5.0×10?5 [g/L] for 1 h to 1600 h, a member having the photovoltaic conversion layer formed on the first transparent electrode.Type: GrantFiled: August 30, 2021Date of Patent: February 20, 2024Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ENERGY SYSTEMS & SOLUTIONS CORPORATIONInventors: Yuya Honishi, Soichiro Shibasaki, Naoyuki Nakagawa, Mutsuki Yamazaki, Yoshiko Hiraoka, Kazushige Yamamoto
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Patent number: 11869992Abstract: A solar cell can include a built-in bypass diode. In one embodiment, the solar cell can include an active region disposed in or above a first portion of a substrate and a bypass diode disposed in or above a second portion of the substrate. The first and second portions of the substrate can be physically separated with a groove. A metallization structure can couple the active region to the bypass diode.Type: GrantFiled: October 21, 2022Date of Patent: January 9, 2024Assignee: Maxeon Solar Pte. Ltd.Inventors: Seung Bum Rim, Gabriel Harley
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Patent number: 11871648Abstract: This application relates to preparation of organic photomultiplication photodetectors, and more particularly to an organic photomultiplication photodetector with bi-directional bias response and a method for producing the same. The photodetector includes an anode layer, an anode modification layer, an interfacial modification layer, an active layer and a cathode layer arranged in sequence. The interfacial modification layer is made of Al2O3. The anode layer is made of indium tin oxide (ITO). The anode modification layer is made of poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate)(PEDOT:PSS). The active layer is made of poly(3-hexylthiophene-2,5-diyl):[6,6]-phenyl-C70-butyric acid methyl ester (P3HT:PC70BM). The cathode layer is made of aluminum, silver or gold.Type: GrantFiled: December 6, 2021Date of Patent: January 9, 2024Assignee: Taiyuan University of TechnologyInventors: Linlin Shi, Yanxia Cui, Guohui Li, Ye Zhang, Wenyan Wang, Ting Ji
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Patent number: 11869998Abstract: Strings of interconnected PV cells within a PV laminate or module are themselves connected by one or more cross-ties. These cross-tied strings can be oriented in a straight or serpentine fashion and spacings between adjacent strings may differ depending upon whether a cross-tie connection is present or not. The PV cells may be multi-diode PV cells having a shared substrate. PV cells connected by a cross-tie are connected in parallel and have a shared voltage potential.Type: GrantFiled: March 24, 2022Date of Patent: January 9, 2024Assignee: MAXEON SOLAR PTE. LTD.Inventors: Tamir Lance, Hoi Hong Ng, David Okawa, Adam Rothschild Hoffman
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Patent number: 11843153Abstract: The present invention relates to use of an enhanced performance ultraconductive copper composite cylindrical conduit. The ultraconductive copper composite cylindrical conduit has enhanced RF conductivity.Type: GrantFiled: March 12, 2020Date of Patent: December 12, 2023Assignee: TE CONNECTIVITY SOLUTIONS GMBHInventors: Martin W. Bayes, Gokce Gulsoy, Ting Gao, David Bruce Sarraf, Chad William Morgan, Rodney Ivan Martens
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Patent number: 11799041Abstract: The present invention relates to a double sided solar cell assembly, including at least one carbon-based perovskite solar cell unit, which has been included in a sandwich structure together with a second solar cell unit, which is a dye-sensitized photoelectrode.Type: GrantFiled: December 19, 2019Date of Patent: October 24, 2023Assignee: Aalto University Foundation srInventor: Syed Ghufran Hashmi
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Patent number: 11799039Abstract: The present invention relates to devices comprising metal halide perovskites and organic passivating agents. In particular, the invention relates to photovoltaic and optoelectronic devices comprising passivated metal halide perovskites. The device according to the invention comprises: (a) a metal halide perovskite; and (b) a passivating agent which is an organic compound; wherein molecules of the passivating agent are chemically bonded to anions or cations in the metal halide perovskite.Type: GrantFiled: October 26, 2020Date of Patent: October 24, 2023Assignee: OXFORD UNIVERSITY INNOVATION LIMITEDInventors: Henry J. Snaith, Antonio Abate, Nakita K. Noel
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Patent number: 11791427Abstract: Provided are structures and methods for doping polycrystalline thin film semiconductor materials in photovoltaic devices. Embodiments include methods for forming and treating a photovoltaic semiconductor absorber layer.Type: GrantFiled: October 25, 2021Date of Patent: October 17, 2023Assignee: First Solar, Inc.Inventors: Sachit Grover, Stuart Irvine, Xiaoping Li, Roger Malik, Shahram Seyedmohammadi, Gang Xiong, Wei Zhang
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Patent number: 11784272Abstract: A multijunction solar cell including a substrate and a top (or light-facing) solar subcell having an emitter layer, a base layer, and a window layer adjacent to the emitter layer, the window layer composed of a material that is optically transparent, has a band gap of greater than 2.6 eV, and includes an appropriately arranged multilayer antireflection coating on the top surface thereof.Type: GrantFiled: April 28, 2022Date of Patent: October 10, 2023Assignee: SolAero Technologies Corp.Inventors: Daniel Derkacs, Andrew Colin Espenlaub
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Patent number: 11784274Abstract: A multijunction solar cell including an upper first solar subcell having a first band gap and positioned for receiving an incoming light beam; a second solar subcell disposed below and adjacent to and lattice matched with said upper first solar subcell, and having a second band gap smaller than said first band gap; wherein at least one of the solar subcells has a graded band gap throughout the thickness of at least a portion of the active layer of the one solar subcell.Type: GrantFiled: January 13, 2022Date of Patent: October 10, 2023Assignee: SolAero Technologies CorpInventors: John Hart, Daniel Derkacs, Zachary Bittner, Andrew Espenlaub
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Patent number: 11769840Abstract: A schottky barrier diode element having a silicon (Si) substrate, an oxide semiconductor layer and a schottky electrode layer, wherein the oxide semiconductor layer includes a polycrystalline and/or amorphous oxide semiconductor having a band gap of 3.0 eV or more and 5.6 eV or less.Type: GrantFiled: May 25, 2017Date of Patent: September 26, 2023Assignee: IDEMITSU KOSAN CO., LTD.Inventors: Shigekazu Tomai, Masatoshi Shibata, Emi Kawashima, Koki Yano, Hiromi Hayasaka
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Patent number: 11764235Abstract: The present invention relates to a colored tandem solar cell module, and more particularly, a high-efficiency thin-film colored tandem solar cell module which does not require separate photocurrent matching, implements a color without a separate color filter, and generates power with high efficiency. According to the present invention, it is possible to provide a colored tandem solar cell module including solar cells, which each include a bottom electrode having an inverse diode structure formed by sequentially stacking a first electrode, a first semiconductor layer, a second semiconductor layer, and a second electrode on a substrate, a light absorption layer formed on the bottom electrode, and a top electrode formed on the light absorption layer, thereby eliminating the need for photocurrent matching, implementing a color without a separate color filter, and improving efficiency.Type: GrantFiled: March 3, 2021Date of Patent: September 19, 2023Assignee: Korea Institute of Science and TechnologyInventors: Hyeong Geun Yu, Jeung Hyun Jeong, Gee Yeong Kim, Yoon Hee Jang
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Patent number: 11758810Abstract: A photoelectric device is disclosed. The photoelectric device includes a first electrode, a second electrode, and an electrolyte disposed between the first electrode and the second electrode. The second electrode includes a transparent layer for allowing light to penetrate into the second electrode, an electron transport layer coupled to the transparent layer, and a genetically hybridized fluorescent silk layer as a photo-sensitizer coupled to the electron transport layer.Type: GrantFiled: January 18, 2018Date of Patent: September 12, 2023Assignee: Purdue Research FoundationInventors: Jung Woo Leem, Seung Ho Choi, Young L. Kim
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Patent number: 11742448Abstract: A multijunction solar cell including an upper first solar subcell having a first band gap and positioned for receiving an incoming light beam; and a second solar subcell disposed below and adjacent to and lattice matched with said upper first solar subcell, and having a second band gap smaller than said first band gap; wherein at least one of the solar subcells has a graded band gap throughout the thickness of at least a portion of its emitter layer and base layer.Type: GrantFiled: January 27, 2022Date of Patent: August 29, 2023Inventors: John Hart, Daniel Derkacs, Zachary Bittner, Andrew Espenlaub
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Patent number: 11744089Abstract: There is disclosed an organic photovoltaic device comprising at least one first subcell comprising at least one first small molecular weight material deposited by solution processing, and at least one second subcell comprising a weight at least one second small molecular material deposited by vacuum evaporation. Also disclosed herein is a method for preparing an organic photovoltaic device comprising at least one first subcell comprising at least one first small molecular weight material and at least one second subcell comprising at least one second small molecular weight material, the method comprising depositing at least one first small weight material by solution processing; and depositing at least one second small weight material by vacuum evaporation.Type: GrantFiled: July 19, 2013Date of Patent: August 29, 2023Assignee: The Regents of the University of MichiganInventors: Stephen R. Forrest, Brian Lassiter
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Patent number: 11728098Abstract: There is provided a method of producing a photovoltaic device comprising a photoactive region comprising a layer of perovskite material, wherein the layer of perovskite material is disposed on a surface that has a roughness average (Ra) or root mean square roughness (Rrms) of greater than or equal to 50 nm. The method comprises using vapour deposition to deposit a substantially continuous and conformal solid layer comprising one or more initial precursor compounds of the perovskite material, and subsequently treating the solid layer with one or more further precursor compounds to form a substantially continuous and conformal solid layer of the perovskite material on the rough surface. There is also provided a photovoltaic device comprising a photoactive region comprising a layer of perovskite material disposed using the method.Type: GrantFiled: June 10, 2016Date of Patent: August 15, 2023Assignee: OXFORD PHOTOVOLTAICS LIMITEDInventors: Brett Akira Kamino, Laura Miranda Perez
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Patent number: 11721777Abstract: A four junction solar cell and its method of manufacture including an upper first solar subcell composed of a semiconductor material having a first band gap; a second solar subcell adjacent to said first solar subcell and composed of a semiconductor material having a second band gap smaller than the first band gap and being lattice matched with the upper first solar subcell; a third solar subcell adjacent to said second solar subcell and composed of a semiconductor material having a third band gap smaller than the second band gap and being lattice matched with the second solar subcell; a graded interlayer adjacent to the third solar subcell and having a fourth band gap greater than the third band gap; and a bottom solar subcell adjacent to the graded interlayer and being lattice mismatched from the third solar subcell and having a fifth band gap smaller than the fifth band gap, wherein the selection of composition of the subcells and their band gaps maximizes the efficiency of the solar cell at a predetermineType: GrantFiled: April 5, 2022Date of Patent: August 8, 2023Inventor: Daniel Derkacs
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Patent number: 11715807Abstract: A multijunction solar cell including an upper first solar subcell having a first band gap and positioned for receiving an incoming light beam; a second solar subcell disposed below and adjacent to and lattice matched with said upper first solar subcell, and having a second band gap smaller than said first band gap; wherein at least one of the solar subcells has a graded band gap throughout the thickness of at least a portion of the active layer.Type: GrantFiled: September 6, 2022Date of Patent: August 1, 2023Assignee: SolAero Technologies Corp.Inventors: John Hart, Daniel Derkacs, Zachary Bittner, Andrew Espenlaub
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Patent number: 11665640Abstract: A microcomputer performs a power supply operation to a wireless communication module at a first time interval set based on a power generation amount at a lowest day power generation amount of a temperature differential power generation module. In addition, the microcomputer performs the power supply operation to a sensor at a second time interval set based on the power generation amount at the lowest day power generation amount of the temperature differential power generation module.Type: GrantFiled: February 17, 2021Date of Patent: May 30, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shiro Kamohara, Akira Tanabe, Kazuya Uejima, Jun Uehara, Kazuya Okuyama
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Patent number: 11661550Abstract: A quantum dot comprising a core comprising a first semiconductor nanocrystal comprising zinc, selenium, and optionally tellurium; and a shell disposed on the core and comprising a second semiconductor nanocrystal having a different composition from the first semiconductor nanocrystal, and comprising zinc and at least one of sulfur and selenium, wherein the shell comprises at least three branches extending from the core, wherein at least one of the branches has a length of greater than or equal to about 2 nm, the quantum dot emits blue light comprising a maximum emission peak at a wavelength of less than or equal to about 470 nm, a full width at half maximum (FWHM) of the maximum emission peak is less than about 35 nm, and the quantum dot does not comprise cadmium.Type: GrantFiled: December 6, 2021Date of Patent: May 30, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung Woo Kim, Jin A Kim, Tae Hyung Kim, Jeong Hee Lee, Eun Joo Jang
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Patent number: 11665917Abstract: An energy harvesting system for generating electrical energy, includes a first substrate, a perovskite layer formed on the first substrate, a charge transport layer disposed on the perovskite layer, and the charge transport layer being configured to slide over the perovskite layer, and a second substrate formed on the charge transport layer.Type: GrantFiled: August 18, 2021Date of Patent: May 30, 2023Assignee: Research & Business Foundation Sungkyunkwan UniversityInventors: Nam-Gyu Park, Ma Chunqing, Yeon Woo Choi
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Patent number: 11658255Abstract: A metamorphic multijunction solar cell having a growth semiconductor substrate with a top surface having a doping in the range of 1x1018 to 1x1020 charge carriers/cm3; a window layer for a top (light facing) subcell formed directly on the top surface of the growth substrate; a sequence of layers of semiconductor material forming a solar cell directly on the window layer; a surrogate substrate on the top surface of the sequence of layers of semiconductor material, wherein a portion of the semiconductor substrate is removed so that only the high doped surface portion of the substrate, having a thickness in the range of 0.5 ?m to 10 ?m, remains.Type: GrantFiled: November 10, 2020Date of Patent: May 23, 2023Assignee: SolAero Technologies Inc.Inventors: Daniel Derkacs, Christopher Kerestes, Steven Whipple
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Patent number: 11658061Abstract: A method of fabricating a semiconductor substrate includes the following steps. A carrier substrate is provided, and a plasma treatment is performed on the surface of the carrier substrate. A polycrystalline semiconductor layer is formed on the surface of the carrier substrate. A rapid thermal treatment is then performed on the polycrystalline semiconductor layer. A buried dielectric layer is then formed on the polycrystalline semiconductor layer. Afterwards, a single crystalline semiconductor layer is formed on the buried dielectric layer.Type: GrantFiled: July 15, 2021Date of Patent: May 23, 2023Assignee: Wafer Works CorporationInventors: Ping-Hai Chiao, Wen-Chung Li
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Patent number: 11646388Abstract: Device structures, apparatuses, and methods are disclosed for photovoltaic cells that may be a single junction or multijunction solar cells, with at least one layer comprising a group-IV semiconductor in which part of the cell comprises a second layer comprising a III-V semiconductor or group-IV semiconductor having a different composition than the group-IV semiconductor of the first layer, such that a heterostructure is formed between the first and second layers.Type: GrantFiled: September 14, 2012Date of Patent: May 9, 2023Assignee: THE BOEING COMPANYInventors: Richard R. King, Christopher M. Fetzer, Nasser H. Karam
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Patent number: 11621358Abstract: A solar cell in which performance degradation caused by an alkali component is suppressed. A solar cell is a back-contact solar cell that comprises a semiconductor substrate; a p-type semiconductor layer, and a first electrode layer corresponding thereto, layered sequentially on one part of the rear side of the semiconductor substrate; an n-type semiconductor layer, and a second electrode layer corresponding thereto, layered sequentially on another part of the rear side of the semiconductor substrate. One part of the n-type semiconductor layer lies directly atop one part of the adjacent p-type semiconductor layer. The first electrode layer is separate from the n-type semiconductor layer and covers the p-type semiconductor layer. The second electrode layer covers the entirety of an overlapping portion where the n-type semiconductor layer lies atop the p-type semiconductor layer.Type: GrantFiled: March 3, 2020Date of Patent: April 4, 2023Assignee: KANEKA CORPORATIONInventors: Kunta Yoshikawa, Hisashi Uzu
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Patent number: 11588124Abstract: Photovoltaic module comprising a plurality of multijunction photovoltaic cells, at least one of said multijunction photovoltaic cells comprising: a first photovoltaic sub-cell extending over a first predetermined area; a second photovoltaic sub-cell provided on said first photovoltaic sub-cell and in electrical connection therewith, said second photovoltaic sub-cell extending over a second predetermined area which is smaller than said first predetermined area so as to define at least one zone in which said first photovoltaic sub-cell is uncovered by said second photovoltaic sub-cell; an electrically-insulating layer situated upon said first photovoltaic sub-cell in at least a part of said zone; and an electrically-conductive layer situated upon at least part of said electrically-insulating layer and in electrical connection with a surface of said second photovoltaic sub-cell, wherein at least one of said multijunction photovoltaic cells is electrically connected to at least one other of said multijunctionType: GrantFiled: November 21, 2019Date of Patent: February 21, 2023Inventors: Brett Kamino, Björn Niesen, Christophe Alsadat Ballif, Nicolas Badel, Antonin Faes, Jonas Geissbühler, Matthieu Despeisse
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Patent number: 11581443Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type architectures and incorporating dotted diffusion, and resulting solar cells, are described. In an example, a solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed in a plurality of non-continuous trenches in the back surface of the substrate.Type: GrantFiled: October 12, 2020Date of Patent: February 14, 2023Assignee: SunPower CorporationInventors: Staffan Westerberg, Gabriel Harley
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Patent number: 11569381Abstract: The invention relates to a deep depletion MIS transistor (100), comprising: a source region (S) and a drain region (D) made of doped semiconductor diamond of a first conductivity type; a channel region (C) made of doped semiconductor diamond of the first conductivity type, arranged between the source region and the drain region; a drift region (DR) made of doped semiconductor diamond of the first conductivity type, arranged between the channel region and the drain region; and a conductive gate (111) arranged on the channel region and separated from the channel region by a dielectric layer (113).Type: GrantFiled: July 18, 2018Date of Patent: January 31, 2023Assignees: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, INSTITUT POLYTECHNIQUE DE GRENOBLE, UNIVERSITE GRENOBLE ALPESInventors: Julien Pernot, Nicolas Rouger, David Eon, Etienne Gheeraert, Gauthier Chicot, Toan Thanh Pham, Florin Udrea