Polycrystalline Or Amorphous Semiconductor Patents (Class 136/258)
  • Patent number: 10727258
    Abstract: This application provides a display device and an active array switch substrate thereof. The active array switch substrate includes: a substrate; active array switches, formed on the substrate, where the active array switch includes a source electrode; at least one solar structure, disposed on the source electrode, where the solar structure includes a solar cell; and a transparent electrode, covered on the solar cell. The solar cell includes an N-type layer, an I-type layer of a microcrystalline silicon structure, and a P-type layer sequentially stacked in a direction away from the source electrode.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: July 28, 2020
    Assignees: HKC Corporation Limited, Chongqing HKC Optoelectronics Technology Co., Ltd.
    Inventor: Yu-Jen Chen
  • Patent number: 10680114
    Abstract: A thin film transistor includes a substrate, a gate electrode disposed on the substrate, an active pattern disposed on the gate electrode, a source electrode electrically coupled to the active pattern and a drain electrode electrically coupled to the active pattern. The active pattern includes a first channel layer overlapping the source electrode and the drain electrode and a second channel layer overlapping the gate electrode. The second channel layer includes a plurality of high electron mobility regions. An electron mobility of each of the high electron mobility regions is greater than an electron mobility of the first channel layer.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: June 9, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Su-Hyoung Kang, Hyun-Gue Kim, Jong-Jun Baek
  • Patent number: 10593552
    Abstract: The invention relates to a method for doping semiconductor substrates by means of a co-diffusion process. First, semiconductor substrates are coated at least on one side with a layer containing at least one first dopant. Two of said substrates in each case are arranged in a process chamber in such a way that two of the coated sides thereof are brought in direct contact.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: March 17, 2020
    Assignee: Fraunhofer-Gesellschaft Zur Förderung der Angewandten Forschung E.V
    Inventors: Philip Rothhardt, Andreas Wolf, Sebastian Meier, Daniel Biro, Sabrina Lohmüller
  • Patent number: 10593550
    Abstract: This application relates to the technical field of semiconductors, and teaches methods for manufacturing a semiconductor structure. One implementation of a method includes: forming a semiconductor layer at a surface of a to-be-etched material layer on a substrate; forming an amorphous carbon layer on the semiconductor layer; forming a patterned mask layer on the amorphous carbon layer; and etching the amorphous carbon layer, the semiconductor layer, and the to-be-etched material layer using the patterned mask layer as a mask. This application may improve uniformity of the amorphous carbon layer, so that a position of a pattern that is formed after the to-be-etched material layer is etched does not deviate from an expected position, and a shape of the pattern is an expected shape.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: March 17, 2020
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Erhu Zheng, Jinhe Qi
  • Patent number: 10566601
    Abstract: An imaging element has a laminated structure including a first electrode, a light-receiving layer formed on the first electrode, and a second electrode formed on the light-receiving layer. The second electrode is made of a transparent amorphous oxide having a conductive property.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: February 18, 2020
    Assignee: Sony Corporation
    Inventor: Toshiki Moriwaki
  • Patent number: 10559771
    Abstract: A process for producing a stack of a first electrode/active layer/second electrode, which stack is intended for an electronic device, in particular an organic photodetector or an organic solar cell, the process comprises the following steps: (a) depositing a first conductor layer on the front side of a substrate, in order to form the first electrode; and (b) depositing an active layer taking the form of a thin organic semiconductor layer, this layer including discontinuous zones; wherein this process further comprises the following steps: (d) depositing a resist layer on that side of the stack which is opposite the substrate, which is at least partially transparent; (e) exposing the resist layer via the back side of the substrate; (f) developing the resist layer; and (g) depositing a second conductor layer in order to form the conductive second electrode.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: February 11, 2020
    Inventors: Jean-Marie Verilhac, Simon Charlot
  • Patent number: 10553738
    Abstract: A solar cell module includes serially connected solar cells. A solar cell includes a carrier that is attached to the backside of the solar cell. Solar cells are attached to a top cover, and vias are formed through the carriers of the solar cells. A solar cell is electrically connected to an adjacent solar cell in the solar cell module with metal connections in the vias.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: February 4, 2020
    Assignee: SunPower Corporation
    Inventors: Seung Rim, Sung Dug Kim
  • Patent number: 10535827
    Abstract: An optical sensor includes a semiconductor layer including a first region, a second region, and a third region between the first region and the second region, a first electrode, a photoelectric conversion layer between the third region and the first electrode, and voltage supply circuitry applying a voltage between the first electrode and the first region to apply a bias voltage to the photoelectric conversion layer. The photoelectric conversion layer has a characteristic showing how a density of current flowing through the photoelectric conversion layer varies with the bias voltage applied to the photoelectric conversion layer. The characteristic includes a third voltage range where an absolute value of a rate of change of the current density relative to the bias voltage is less than in a first voltage range and a second voltage range, the third voltage range being between the first voltage range and the second voltage range.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: January 14, 2020
    Inventor: Tokuhiko Tamaki
  • Patent number: 10514509
    Abstract: An optical coupler has a waveguide coupled to a grating of multiple scattering units, each scattering unit having a first scattering element formed of a shape in a polysilicon gate layer and a second scattering element formed of a shape in a body silicon layer of a metal-oxide-semiconductor (MOS) integrated circuit (IC). The couplers may be used in a system having a coupler on each of a first and second IC, infrared light being formed into a beam passing between the couplers. Vias may be interposed in third ICs between the first and second ICs. The couplers may be configured with nonuniform width of scattering elements to produce Gaussian or focused beams.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: December 24, 2019
    Assignees: The Regents of the University of Colorado, a Body Corporate, Massachusetts Institute of Technology
    Inventors: Milos Popovic, Vladimir Marko Stojanovic, Jason Scott Orcutt
  • Patent number: 10509288
    Abstract: A liquid crystal display device includes a first substrate formed with a first gate line, a first source line, a first thin film transistor including a first channel region and a first semiconductor layer, and a second semiconductor layer electrically insulated from the first semiconductor layer, a second substrate disposed opposite to the first substrate, and a first liquid crystal layer disposed between the first substrate and the second substrate. The second semiconductor layer is disposed between the first thin film transistor and the first liquid crystal layer, and overlaps at least a part of the first channel region of the first thin film transistor in planar view.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: December 17, 2019
    Assignee: Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Daisuke Kajita, Genshirou Kawachi, Teruhisa Nakagawa
  • Patent number: 10505055
    Abstract: A photoelectric conversion element includes an n-type semiconductor substrate, a p-type amorphous semiconductor film on the side of a first surface and side surface of the semiconductor substrate, an n-type amorphous semiconductor film on the first surface side of the semiconductor substrate, a p-electrode on the p-type amorphous semiconductor film, and an n-electrode on the n-type amorphous semiconductor film. The p-electrode is located on the p-type amorphous semiconductor film, which is placed on the first surface side and side surface of the semiconductor substrate.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: December 10, 2019
    Inventors: Naoki Asano, Masamichi Kobayashi
  • Patent number: 10461160
    Abstract: This invention relates to an electronic semiconductive component comprising at least one layer (2,3) of a p-type or n-type material, wherein the layer of a said p- or n-type material is constituted by a metal hydride having a chosen dopant. The invention also relates to methods for producing the component.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: October 29, 2019
    Inventors: Alexander G. Ulyashin, Smagul Karazhanov, Arve Holt
  • Patent number: 10435813
    Abstract: The present invention provides a method of epitaxial growth of an SiC thin film by the thermal CVD process wherein it is possible to improve the in-plane uniformity of the doping density and possible to grow an SiC thin film by a uniform thickness. This method is an epitaxial growth method for silicon carbide characterized by comprising adjusting a ratio of the hydrocarbon gas and silicon feedstock gas so as to become, by C/Si ratio, 0.5 to 1.5 in range, making the hydrocarbon gas contact a hydrocarbon decomposition catalyst heated to 1000° C. to 1200° C. so as to make at least part of the hydrocarbon gas break down into carbon and hydrogen, and supplying carbon contained in the hydrocarbon gas and silicon contained in the silicon feedstock gas to the silicon carbide single crystal substrate.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: October 8, 2019
    Assignee: SHOWA DENKO K.K.
    Inventors: Wataru Ito, Takashi Aigo, Tatsuo Fujimoto
  • Patent number: 10395849
    Abstract: An electrode plate, a manufacturing method thereof, and an energy storage device are disclosed. The method for manufacturing an electrode plate includes: forming a germanium film on a metal substrate; carrying out a topology treatment on the germanium film by using a functionalization element, to obtain the electrode plate with a topological semiconductor characteristic. The electrode plate prepared by the above method has a high conductivity and a low internal resistance.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: August 27, 2019
    Inventors: Long Wang, Yanzhao Li, Yong Qiao, Yongchun Lu
  • Patent number: 10377636
    Abstract: A polycrystalline silicon rod is synthesized by the Siemens method (S101). After the polycrystalline silicon rod is covered from above with a plastic bag whose inner surface has been washed, and housed in the plastic bag in a reactor (S103), the polycrystalline silicon rod is removed out of the reactor (S104), and heat-sealed and stored in an enclosed state (S105). According to the present invention, steps conventionally considered as essential, such as washing, etching, and water washing, are not always necessary, and therefore the concentrations of fluorine ions, nitrate ions, and nitrogen dioxide ions remaining on the surface can each be less than 0.2 ppbw. In addition, by covering with the plastic bag, the metal contamination levels decrease significantly. Moreover, when the handling according to the present invention is performed, surface contamination hardly proceeds even if the polycrystalline silicon rod is stored for a long period.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: August 13, 2019
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shuichi Miyao, Junichi Okada, Shigeyoshi Netsu
  • Patent number: 10355148
    Abstract: The invention discloses nanocrystalline (NC) FeS2 thin films as the back contact for CdTe solar cells. In one example, the FeS2 NC layer is prepared from a solution directly on the CdTe surface using spin-casting and chemical treatment at ambient temperature and pressure, without a thermal treatment step. Solar cells prepared by applying the NC FeS2 back contact onto CdTe yield efficiencies of about 95% to 100% that of standard Cu/Au back contact devices. In another example, FeS2 is interposed between Cu and Au to form a Cu/FeS2 NC/Au back contact configuration yielding an efficiency improvement of 5 to 9 percent higher than standard Cu/Au devices.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: July 16, 2019
    Assignee: The University of Toledo
    Inventors: Khagendra Bhandari, Randy J. Ellingson, Rajendra R. Khanal
  • Patent number: 10283658
    Abstract: Photovoltaic (PV) and photodetector (PD) devices, comprising a plurality of interband cascade (IC) stages, wherein the IC stages comprise an absorption region with a type-I superlattice and/or a bulk semiconductor material having a band gap, the absorption region configured to absorb photons, an intraband transport region configured to act as a hole barrier, and an interband tunneling region configured to act as an electron barrier, wherein the absorption region, the intraband transport region, and the interband tunneling region are positioned such that electrons will flow from the absorption region to the intraband transport region to the interband tunneling region.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: May 7, 2019
    Assignee: The Board of Regents of the University of Oklahoma
    Inventor: Rui Q. Yang
  • Patent number: 10283366
    Abstract: A laser system includes a nonlinear optical (NLO) crystal, wherein the NLO crystal is annealed within a selected temperature range. The NLO crystal is passivated with at least one of hydrogen, deuterium, a hydrogen-containing compound or a deuterium-containing compound to a selected passivation level. The system further includes at least one light source, wherein at least one light source is configured to generate light of a selected wavelength and at least one light source is configured to transmit light through the NLO crystal. The system further includes a crystal housing unit configured to house the NLO crystal.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: May 7, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Yung-Ho Chuang, Vladimir Dribinski
  • Patent number: 10283665
    Abstract: Various embodiments of a compensated photonic device structure and fabrication method thereof are described herein. A photonic device may include a silicon-on-insulator (SOI) substrate with a buried oxide (BOX) layer therein, a Si waveguide and an n-type contact layer formed on the BOX layer, a Si multiplication layer disposed on the n-type contact layer, a p-type Si charge layer disposed on the Si multiplication layer, a germanium (Ge) absorption layer disposed on the p-type Si charge layer, a p-type contact layer disposed on the Ge absorption layer, and a metal layer disposed on the p-type contact layer. A compensated region may be formed between the p-type Si charge layer and the Ge absorption layer with a portion of the compensated region in the p-type Si charge layer and another portion of the compensated region in the Ge absorption layer.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: May 7, 2019
    Assignee: SiFotonics Technologies Co., Ltd.
    Inventors: Mengyuan Huang, Su Li, Tzung-I Su, Pengfei Cai, Wang Chen, Ching-yin Hong, Dong Pan
  • Patent number: 10273403
    Abstract: The present disclosure relates to a composition that includes a particle and a surface species, where the particle has a characteristic length between greater than zero nm and 100 nm inclusively, and the surface species is associated with a surface of the particle such that the particle maintains a crystalline form when the composition is at a temperature between ?180° C. and 150° C.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: April 30, 2019
    Assignees: Alliance for Sustainable Energy, LLC, University of Washington, Regents of the University of Colorado, a body corporate
    Inventors: Joseph Matthew Luther, Abhishek Swarnkar, Ashley Rae Marshall, Erin Mariko Sanehira
  • Patent number: 10249531
    Abstract: A method for forming a metal wiring according to embodiments includes forming a first insulating layer on a substrate; forming a catalyst adsorption layer by bringing a surface of the first insulating layer into contact with a solution containing a compound having a triazine skeleton, a first functional group of one of a silanol group and an alkoxysilyl group, and a second functional group of at least one selected from the group consisting of an amino group, a thiol group, a carboxyl group, and an azide group; forming a second insulating layer different from the first insulating layer on the catalyst adsorption layer; patterning the second insulating layer to form a mask pattern; etching the first insulating layer by a wet etching method; selectively forming a catalyst layer; and forming a metal layer on the catalyst layer by an electroless plating method.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: April 2, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Atsushi Hieno, Tsutomu Nakanishi, Yusuke Tanaka, Yasuhito Yoshimizu, Akihiko Happoya
  • Patent number: 10236563
    Abstract: A solar panel array structure is used in network communications that comprises at least one support structure configured to support a solar panel array, wherein the at least one support structure comprises a metal portion. The metal portion comprises antenna connections that are configured to allow the metal portion to be used as a radio antenna. In some cases, a radio transceiver is connected to the antenna connections. A separate radio antenna may also be connected to the support structure or to the solar panel array. The radio transceiver may be used to transmit data through a wireless communication network.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: March 19, 2019
    Assignee: Vivint, Inc.
    Inventor: Maha Achour
  • Patent number: 10224441
    Abstract: A solar cell includes a semiconductor substrate of a first conductive type and includes a first side and a second side, the second side having a textured structure formed on the entire second side; a first doped region of the first conductive type and a second doped region of a second conductive type on the first side; a first passivation layer on the first doped region and the second doped region and exposing a portion of a back surface of each of the first and second doped regions, the first passivation layer being formed of silicon nitride (SiNx), silicon dioxide (SiOx), or a combination thereof; a second passivation layer on the second side; an anti-reflection layer on the second passivation layer; and a first electrode electrically connected to the first doped region and a second electrode electrically connected to the second doped region.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: March 5, 2019
    Inventors: Sungeun Lee, Youngho Choe
  • Patent number: 10219325
    Abstract: Methods and apparatus for measuring the melt depth of a substrate during pulsed laser melting are provided. The apparatus can include a heat source, a substrate support with an opening formed therein, and an interferometer positioned to direct coherent radiation toward the toward the substrate support. The method can include positioning the substrate with a first surface in a thermal processing chamber, heating a portion of the first surface with a heat source, directing infrared spectrum radiation at a partially reflective mirror creating control radiation and interference radiation, directing the interference radiation to a melted surface and directing the control radiation to a control surface, and measuring the interference between the reflected radiation. The interference fringe pattern can be used to determine the precise melt depth during the melt process.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: February 26, 2019
    Assignee: Applied Materials, Inc.
    Inventor: Jiping Li
  • Patent number: 10210964
    Abstract: Ion beam modification of noble metal electrical contact coatings can achieve suitable friction and wear behavior with inherently stable low ECR. For example, this method of producing Au electrical contact coatings can produce wear properties similar to electroplated hard Au, but without the environmental concerns due to stringent OSHA regulations on the use and disposal of toxic chemicals associated with Au electroplating baths. Integration of physical vapor deposition techniques with ion implantation can produce noble metal coatings with surfaces modified to achieve the desired balance between adhesion/friction/wear and electrical contact resistance on a commercial scale.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: February 19, 2019
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Khalid Mikhiel Hattar, Jon-Erik Mogonye, Somuri V. Prasad
  • Patent number: 10211427
    Abstract: A display device and an apparatus and method for manufacturing the same are disclosed. The display device includes: a substrate; a display unit formed on the substrate; and an inorganic layer formed on the display unit, wherein a water vapor transmission rate (WVTR) of the inorganic layer is 5×10?5 g/m2 day or less. The apparatus for manufacturing a display device includes: a chamber; a shower head for spraying a mixed gas into the chamber; a plasma generation unit for forming plasma from the mixed gas; a susceptor facing the shower head and on which a substrate is seated; and a power supply unit electrically connected to the plasma generation unit, wherein a frequency of a current supplied from the power supply unit to the plasma generation unit is between about 27 MHz and about 42 MHz.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: February 19, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Myungsoo Huh, Sunghun Key, Sungchul Kim, Cheollae Roh, Sukwon Jung, Hyunwoo Joo, Jaihyuk Choi
  • Patent number: 10211343
    Abstract: The present invention provides a thin film transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer, which are laminated on a substrate. The semiconductor layer is a polysilicon thin film. The polysilicon thin film in regions corresponding to the source electrode and the drain electrode has a smaller crystal grain size than that of the polysilicon thin film in a channel region between the source electrode and the drain electrode.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: February 19, 2019
    Assignee: V TECHNOLOGY CO., LTD.
    Inventors: Michinobu Mizumura, Makoto Hatanaka, Tetsuya Kiguchi
  • Patent number: 10202283
    Abstract: A cyclic silane having high purity, a composition containing a polysilane obtained by polymerization of the cyclic silane, and a silicon thin film are disclosed. A method for producing a cyclic silane of the formula (SiH2)n, where n is an integer of 4 to 6, includes reacting a cyclic silane compound of the formula (SiR1R2)n (where R1 and R2 are each a hydrogen atom, a C1-6 alkyl group, or a substituted or unsubstituted phenyl group) with a hydrogen halide in the presence of an aluminum halide to obtain a cyclic silane of the formula (SiR3R4)n (where R3 and R4 are each a halogen atom), and then distilling the solution, and reducing the cyclic silane of the formula (SiR3R4)n with hydrogen or lithium aluminum hydride. The distillation may be carried out at a temperature of 40° C. to 80° C. under a reduced pressure of 0 to 30 Torr.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: February 12, 2019
    Assignee: Thin Film Electronics ASA
    Inventors: Yuichi Goto, Kentaro Nagai, Masahisa Endo, Gun Son
  • Patent number: 10204831
    Abstract: Embodiments of the invention generally relate to apparatuses and methods for producing epitaxial thin films and devices by epitaxial lift off (ELO) processes. In one embodiment, a method for forming thin film devices during an ELO process is provided which includes coupling a plurality of substrates to an elongated support tape, wherein each substrate contains an epitaxial film disposed over a sacrificial layer disposed over a wafer, exposing the substrates to an etchant during an etching process while moving the elongated support tape, and etching the sacrificial layers and peeling the epitaxial films from the wafers while moving the elongated support tape. Embodiments also include several apparatuses, continuous-type as well as a batch-type apparatuses, for forming the epitaxial thin films and devices, including an apparatus for removing the support tape and epitaxial films from the wafers on which the epitaxial films were grown.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: February 12, 2019
    Assignee: ALTA DEVICES, INC.
    Inventors: Thomas Gmitter, Gang He, Melissa Archer, Andreas Hegedus
  • Patent number: 10205045
    Abstract: A solar cell and a method of manufacturing the same are provided. The method comprises: forming a first electrode layer on a substrate; forming a semiconductor film of first conduction type on the first electrode layer; forming a germanium film on the semiconductor film of first conduction type, and topologizing the germanium film by using a functionalization element so as to obtain a semiconductor film of second conduction type having characteristics of topological insulator, the semiconductor film of first conduction type mating with the semiconductor film of second conduction type having characteristics of topological insulator to form a p-n junction; and forming a second electrode layer on the semiconductor film of second conduction type. The solar cell manufactured according this method has higher electric energy conversion efficiency.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: February 12, 2019
    Inventors: Yanzhao Li, Yong Qiao, Long Wang, Yongchun Lu
  • Patent number: 10196297
    Abstract: CTE-matched silicate glasses and more particularly to low-alkali CTE-matched silicate glasses that are useful in semiconductor-based applications, such as photovoltaics are described along with methods of making such glasses.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: February 5, 2019
    Inventors: Bruce Gardiner Aitken, Carlo Anthony Kosik Williams
  • Patent number: 10199528
    Abstract: A mesoscopic solar cell, including: a conductive substrate, a hole blocking layer, a mesoporous nanocrystalline layer, an insulation separating layer, and a hole collecting layer, and perovskite light absorption materials. The hole blocking layer, the mesoporous nanocrystalline layer, the insulation separating layer, and the hole collecting layer are sequentially laminated on the conductive substrate. The perovskite semiconductor materials are filled in the mesoporous nanocrystalline layer, the insulation separating layer, and the hole collecting layer, which enables the mesoporous nanocrystalline layer to be an active light absorption layer operating as a photoanode, and enables the insulation separating layer to be a hole transporting layer.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: February 5, 2019
    Inventors: Hongwei Han, Zhiliang Ku
  • Patent number: 10155248
    Abstract: Described herein are improved dewetting methods and improved patterned articles produced using such methods. The improved methods and articles generally implement continuous ultra-thin metal-containing films or film stacks as the materials to be dewetted. For example, a method can involve the steps of providing a substrate that has a continuous ultra-thin metal-containing film or film stack disposed on a surface thereof, and dewetting at least a portion of the continuous ultra-thin metal-containing film or film stack to produce a plurality of discrete metal-containing dewetted islands on the surface of the substrate.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: December 18, 2018
    Inventors: David Eugene Baker, Carme Gomez Carbonell, David Francis Dawson-Elli, Prantik Mazumder, Valerio Pruneri, Lili Tian
  • Patent number: 10153386
    Abstract: A multilayered structure may include a doped buffer layer on a transparent conductive oxide layer.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: December 11, 2018
    Assignee: First Solar, Inc.
    Inventors: Benyamin Buller, Akhlesh Gupta
  • Patent number: 10128396
    Abstract: A photovoltaic cell may include a hydrogenated amorphous silicon layer including a n-type doped region and a p-type doped region. The n-type doped region may be separated from the p-type doped region by an intrinsic region. The photovoltaic cell may include a front transparent electrode connected to the n-type doped region, and a rear electrode connected to the p-type doped region. The efficiency may be optimized for indoor lighting values by tuning the value of the H2/SiH4 ratio of the hydrogenated amorphous silicon layer.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: November 13, 2018
    Inventors: Cosimo Gerardi, Cristina Tringali, Sebastiano Ravesi, Marina Foti, NoemiGraziana Sparta′, Corrado Accardi, Stella Loverso
  • Patent number: 10119069
    Abstract: The present invention provides a functional material and a method for preparing the same, as well as a color filter material and a color filter substrate. The present invention belongs to the display technical field and can solve the problem that existing color filter films are environmentally unfriendly and have poor heat resistance and unsatisfactory colors. The functional material of the present invention includes an inorganic powder whose surface has a modified layer, wherein the inorganic powder includes any one or more of aluminum oxide, magnesium oxide, zinc oxide, zirconium oxide, silicon dioxide, titanium dioxide, boron oxide, diiron trioxide, calcium oxide, potassium oxide, sodium oxide and lithium oxide; and the modified layer is generated by a reaction of a dianhydride and a diamine. The color filter material of the present invention includes the above functional material and a quantum dot.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: November 6, 2018
    Inventors: Jiuxia Yang, Feng Bai, Jiantao Liu
  • Patent number: 10121602
    Abstract: This metal substrate for a dye-sensitized solar cell includes a clad material including a nonporous first metal layer, arranged on an anode side of a dye-sensitized solar cell element, made of a metal having corrosion resistance against an electrolyte of the dye-sensitized solar cell element and a second metal layer made of a metal having lower electrical resistance than the first metal layer and bonded to a side of the first metal layer opposite to the dye-sensitized solar cell element.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: November 6, 2018
    Assignee: HITACHI METALS, LTD.
    Inventors: Ryouji Inoue, Shinji Yamamoto, Keita Watanabe, Masaaki Ishio
  • Patent number: 10094988
    Abstract: The disclosed embodiments relate to an integrated circuit structure and methods of forming them in which photonic devices are formed on the back end of fabricating a CMOS semiconductor structure containing electronic devices. Doped regions associated with the photonic devices are formed using microwave annealing for dopant activation.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: October 9, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej Sandhu
  • Patent number: 10096736
    Abstract: A photodetector comprising a region of a p-type phase-change chalcogenide material forming a heterojunction with a region of n-type Silicon; wherein the p-type phase-change chalcogenide material comprises one of GeTe and SbTe.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: October 9, 2018
    Assignee: HRL Laboratories, LLC
    Inventors: Jeong-Sun Moon, Hwa Chang Seo
  • Patent number: 10072345
    Abstract: The present disclosure provides methods and systems for electrorefining high-purity materials, for example, silicon. An exemplary system includes at least one cathode, an anode, and a reference electrode. At least one controller, for example a potentiostat, is used to control the potential difference between a reference electrode and a cathode or anode. The system can be operated in a single phase or multiple phase operation to produce high-purity materials, such as solar-grade silicon.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: September 11, 2018
    Assignee: Arizona Board of Regents on behalf of Arizona State University
    Inventor: Meng Tao
  • Patent number: 10069031
    Abstract: One embodiment of the present invention relates to a method of manufacturing polycrystalline silicon thin-film solar cell by a method of crystallizing a large-area amorphous silicon thin film using a linear electron beam, and the technical problem to be solved is to crystallize an amorphous silicon thin film, which is formed on a low-priced substrate, by means of an electron beam so as for same to easily be of high quality by having high crystallization yield and to be processed at a low temperature.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: September 4, 2018
    Inventors: Chae Hwan Jeong, Sun Hwa Lee, Sang Ryu, Ho Sung Kim, Seong Jae Boo
  • Patent number: 10065864
    Abstract: Provided is a method of preparing trichlorosilane, more particularly, a method of preparing trichlorosilane which trichlorosilane can be obtained with an improved yield using a catalyst-supported silicon.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: September 4, 2018
    Inventors: Gil Ho Kim, Joon Hwan Kim, Kyu Hak Park, Dong Ho Lee
  • Patent number: 10056511
    Abstract: A device and method of making an amorphous-silicon/inorganic thin film tandem solar cell including the steps of depositing a textured oxide buffer layer on an amorphous substrate, depositing a crystalline inorganic semiconductor film from a eutectic alloy on the buffer layer, and depositing an amorphous film on the crystalline inorganic film, the amorphous film forming a p-n junction with the crystalline inorganic semiconductor for a solar cell device.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: August 21, 2018
    Assignee: Solar-Tectic LLC
    Inventor: Ashok Chaudhari
  • Patent number: 10026861
    Abstract: An improved photovoltaic device and methods of manufacturing the same that includes an interface layer adjacent to a semiconductor absorber layer, where the interface layer includes a material in the semiconductor layer which decreases in concentration from the side of the interface layer contacting the absorber layer to an opposite side of the interface layer.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: July 17, 2018
    Assignee: First Solar, Inc.
    Inventors: Igor Sankin, Markus Gloeckler, Benyamin Buller, Kieran Tracy
  • Patent number: 9994456
    Abstract: The invention relates to a process and an apparatus for preparation of polychlorosilanes from monomeric chlorosilanes, by subjecting the chlorosilanes to a thermal plasma.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: June 12, 2018
    Assignee: Evonik Degussa GmbH
    Inventors: Juergen Erwin Lang, Hartwig Rauleder, Ekkehard Mueh, Imad Moussallem
  • Patent number: 9960302
    Abstract: A solar module is provided. The solar module includes a number of photovoltaic structures. Each photovoltaic structure has an interdigitated back contact, and the photovoltaic structures are cascaded, wherein any two adjacent structures are electrically coupled by overlapping their edges.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: May 1, 2018
    Assignee: Tesla, Inc.
    Inventors: Jiunn Benjamin Heng, Peter J. Rive, Zhigang Xie, Bobby Yang
  • Patent number: 9947821
    Abstract: A silicon device, has a plurality of crystalline silicon regions. One crystalline silicon region is a doped crystalline silicon region. Deactivating some or all of the dopant atoms in the doped crystalline silicon region is achieved by introducing hydrogen atoms into the doped 5 crystalline silicon region, whereby the hydrogen coulombicly bonds with some or all of the dopant atoms to deactivate the respective dopant atoms. Deactivated dopant atoms may be reactivated by heating and illuminating the doped crystalline silicon region to break at least some of the dopant-hydrogen bonds while maintaining conditions to create a high concentration of neutral hydrogen atoms whereby 10 some of the hydrogen atoms diffuse from the doped crystalline silicon region without rebinding to the dopant atoms.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: April 17, 2018
    Assignee: Newsouth Innovations PTY Limited
    Inventors: Brett Jason Hallam, Matthew Bruce Edwards, Stuart Ross Wenham, Phillip George Hamer, Catherine Emily Chan, Chee Mun Chong, Pei Hsuan Lu, Ly Mai, Li Hui Song, Adeline Sugianto, Alison Maree Wenham, Guang Qi Xu
  • Patent number: 9935219
    Abstract: It is an object of the present invention to improve photoelectric conversion efficiency in a photoelectric conversion device. The photoelectric conversion device 11 according to the present invention uses a polycrystalline semiconductor layer including a plurality of semiconductor particles 3a coupled together as a light-absorbing layer 3, each of the semiconductor particles 3a including a group I-III-VI compound, each of the semiconductor particles 3a having a higher composition ratio PI of a group I-B element to a group III-B element in a surface portion thereof than that in a central portion thereof.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: April 3, 2018
    Assignee: KYOCERA Corporation
    Inventors: Shintaro Kubo, Michimasa Kikuchi, Hideaki Asao, Shinnosuke Ushio
  • Patent number: 9922821
    Abstract: Provided is a technique of forming a film containing a first element and a second element on a substrate by performing a cycle a predetermined number of times. The cycle includes: (a) supplying a hydro-based precursor containing the first element and a halogen-based precursor containing the second element into a process chamber accommodating a substrate to confine the hydro-based precursor and the halogen-based precursor in the process chamber; (b) maintaining a state where the hydro-based precursor and the halogen-based precursor are confined in the process chamber; and (c) exhausting the process chamber.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: March 20, 2018
    Inventor: Tsuyoshi Takeda
  • Patent number: 9911873
    Abstract: Methods of hydrogenation of passivated contacts using materials having hydrogen impurities are provided. An example method includes applying, to a passivated contact, a layer of a material, the material containing hydrogen impurities. The method further includes subsequently annealing the material and subsequently removing the material from the passivated contact.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: March 6, 2018
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: William Nemeth, Hao-Chih Yuan, Vincenzo LaSalvia, Pauls Stradins, Matthew R. Page