Polycrystalline Or Amorphous Semiconductor Patents (Class 136/258)
  • Patent number: 11563170
    Abstract: A laminated seed layer stack with a smooth top surface having a peak to peak roughness of 0.5 nm is formed by sequentially sputter depositing a first seed layer, a first amorphous layer, a second seed layer, and a second amorphous layer where each seed layer may be Mg and has a resputtering rate 2 to 30X that of the amorphous layers that are TaN, SiN, or a CoFeM alloy. A template layer that is NiCr or NiFeCr is formed on the second amorphous layer. As a result, perpendicular magnetic anisotropy in an overlying magnetic layer that is a reference layer, free layer, or dipole layer is substantially maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The laminated seed layer stack may include a bottommost Ta or TaN buffer layer.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: January 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian Zhu, Guenole Jan, Yuan-Jen Lee, Huanlong Liu, Ru-Ying Tong, Po-Kang Wang
  • Patent number: 11563134
    Abstract: Systems and methods of three-terminal tandem solar cells are described. Three-terminal metal electrodes can be formed to contact subcells of the tandem solar cell. The three-terminal tandem cell can improve the device efficiency to at least 30%.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: January 24, 2023
    Assignee: California Institute of Technology
    Inventors: Harry A. Atwater, Phillip R. Jahelka
  • Patent number: 11562902
    Abstract: Exemplary methods of semiconductor processing may include flowing a silicon-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region, and the substrate may be maintained at a temperature below or about 450° C. The methods may include striking a plasma of the silicon-containing precursor. The methods may include forming a layer of amorphous silicon on a semiconductor substrate. The layer of amorphous silicon may be characterized by less than or about 3% hydrogen incorporation.
    Type: Grant
    Filed: July 19, 2020
    Date of Patent: January 24, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Rui Cheng, Diwakar Kedlaya, Karthik Janakiraman, Gautam K. Hemani, Krishna Nittala, Alicia J. Lustgraaf, Zubin Huang, Brett Spaulding, Shashank Sharma, Kelvin Chan
  • Patent number: 11557687
    Abstract: A solar cell device includes a light-transmissive substrate, a solar cell module, an optical composite film assembly, and a light-transmissive top plate. The solar cell module is disposed on the light-transmissive substrate and includes a solar cell unit. The optical composite film assembly is light-transmissive, and includes a light diffusion layer and a fiber layer. The optical composite film assembly and the solar cell module are disposed on each other. The light-transmissive top plate is disposed spaced apart from the light-transmissive substrate and cooperates with the light-transmissive substrate to sandwich the solar cell module and the optical composite film assembly.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: January 17, 2023
    Assignee: SOUTHERN TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Ruei-Tang Chen, Fong-Lang Wu
  • Patent number: 11545590
    Abstract: A solar cell, a method for producing a solar cell, and a solar module are provided. The solar cell includes: an N-type substrate and a P-type emitter formed on a front surface of the substrate; a first passivation layer, a second passivation layer and a third passivation layer sequentially formed over the front surface of the substrate and in a direction away from the P-type emitter, and a passivated contact structure disposed on a rear surface of the substrate. The first passivation layer includes a first Silicon oxynitride (SiOxNy) material, where x>y. The second passivation layer includes a first silicon nitride (SimNn) material, where m>n. The third passivation layer includes a second silicon oxynitride (SiOiNj) material, where a ratio of i/j?[0.97, 7.58].
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: January 3, 2023
    Assignees: ZHEJIANG JINKO SOLAR CO., LTD., JINKO SOLAR CO., LTD.
    Inventors: Wenqi Li, Jie Yang, Xinyu Zhang, Hao Jin
  • Patent number: 11505866
    Abstract: According to one embodiment, film formation apparatus includes: a carrying unit that includes a rotation table which circulates and carries a workpiece; a film formation process unit which includes a target formed of a silicon material, and a plasma producer that produces plasma of a sputter gas introduced between the target and the rotation table, and which forms a silicon film on the workpiece by sputtering; and a hydrogenation process unit which includes a process gas introducing unit that introduces a process gas containing a hydrogen gas, and a plasma producer that produces plasma of the process gas, and which performs hydrogenation on the silicon film formed on the workpiece. The carrying unit carries the workpiece so as to alternately pass through the film formation process unit and through the hydrogenation process unit.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: November 22, 2022
    Inventors: Daisuke Ono, Akihiko Ito
  • Patent number: 11495452
    Abstract: A method for preparing a silicon nitride film with a high deposition rate and a reduced damage to the substrate and/or the underlying layer formed under the silicon nitride film. The method for preparing a silicon nitride film contains the steps of irradiating a nitride with an ultraviolet light, and contacting the nitride irradiated with the ultraviolet light and a hydrogenated cyclic silane represented by a general formula SinH2n, wherein n is 5, 6, or 7.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: November 8, 2022
    Assignees: TOHKU UNIVERSITY, NIPPON SHOKUBAI CO., LTD.
    Inventors: Akinobu Teramoto, Yoshinobu Shiba, Takashi Abe, Akira Nishimura
  • Patent number: 11482672
    Abstract: A solid junction-type photoelectric conversion element (10) including a first conductive layer (2), an electric power generation layer (4), and a second conductive layer (6), which are laminated in this order, wherein the electric power generation layer (4) comprises: a perovskite compound represented by a composition formula ABX3, formed of an organic cation A, a metal cation B and a halide anion X, and a compound Z having no perovskite structure.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: October 25, 2022
    Assignee: SEKISUI CHEMICAL CO., LTD.
    Inventors: Naohiro Fujinuma, Junichiro Anzai, Sachiko Satou
  • Patent number: 11482630
    Abstract: The invention relates to a method for improving the ohmic-contact behaviour between a contact grid and an emitter layer of a silicon solar cell. The object of the invention is to propose a method for improving the ohmic-contact behaviour between a contact grid and an emitter layer of a silicon solar cell, in which the effects on materials caused by irradiation of the sun-facing side are further minimized. In addition, the method should also be applicable to silicon solar cells in which the emitter layer has a high sheet resistance.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: October 25, 2022
    Assignee: CE CELL ENGINEERING GMBH
    Inventor: Hongming Zhao
  • Patent number: 11450775
    Abstract: The present disclosure provides a solar cell and a method for producing same. The solar cell includes: a substrate; a first passivation film, an anti-reflection layer and at least one first electrode formed on a front surface of the substrate; and a tunneling layer, a field passivation layer and at least one second electrode formed on a rear surface. The field passivation layer includes a first field passivation sub-layer and a second field passivation sub-layer; a conductivity of the first field passivation sub-layer is greater than a conductivity of the second field passivation sub-layer, and a thickness of the second field passivation sub-layer is smaller than a thickness of the first field passivation sub-layer; either the at least one first electrode or the at least one second electrode includes a silver electrode, a conductive adhesive and an electrode film that are sequentially formed in a direction away from the substrate.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: September 20, 2022
    Assignees: Jinko Green Energy (Shanghai) Management Co., LTD., ZHEJIANG JINKO SOLAR CO., LTD.
    Inventors: Jingsheng Jin, Xinyu Zhang
  • Patent number: 11437535
    Abstract: A voltage-matched solar module for converting incident solar radiation into electricity consisting of a plurality of wafer-sized multi-junction solar devices and wiring circuitry adjacent to a module-sized bottom substrate. Each solar device has at least two photovoltaic (PV) cells separated by electrically insulating transparent layers. The PV cells are aligned so as to overlap and are electrically connected to the wiring circuitry by conducting vias. The wiring circuitry includes a multiplicity of serial strings electrically connected in parallel and having substantially the same voltage. A method of producing the solar module is disclosed which utilizes an ALD/LPCVD tool for van der Waals epitaxy of 2D materials.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: September 6, 2022
    Inventor: Moshe Einav
  • Patent number: 11431280
    Abstract: One embodiment can provide a photovoltaic roof tile. The photovoltaic roof tile can include a transparent front cover, a transparent back cover, and a plurality of polycrystalline-Si-based photovoltaic structures positioned between the front cover and the back cover. A respective polycrystalline-Si-based photovoltaic structure has a front surface facing the front cover and a back surface facing the back cover. The photovoltaic roof tile can further include a paint layer positioned on a back surface of the back cover facing away from the front cover. A color of the paint layer substantially matches a color of the front surface of the respective polycrystalline-Si-based photovoltaic structure.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: August 30, 2022
    Assignee: Tesla, Inc.
    Inventors: John Liu, Yangsen Kang, Anh N. Duong, Yongkee Chae, Milan Padilla, Chen Wang, Remy D. Labesque
  • Patent number: 11398567
    Abstract: In a method of manufacturing a negative capacitance structure, a ferroelectric dielectric layer is formed over a first conductive layer disposed over a substrate, and a second conductive layer is formed over the ferroelectric dielectric layer. The ferroelectric dielectric layer includes an amorphous layer and crystals.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: July 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wilman Tsai, Ling-Yen Yeh
  • Patent number: 11393996
    Abstract: The present application relates to an organic electronic device comprising a first electrode; a second electrode provided opposite to the first electrode; a photoactive layer provided between the first electrode and the second electrode; and an electron transfer layer provided between the photoactive layer and the first electrode, wherein the electron transfer layer comprises a zinc oxide (ZnO) nanoparticle having one or more amine groups bonding to a surface thereof, and a method for manufacturing the same.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: July 19, 2022
    Assignee: LG CHEM, LTD.
    Inventors: Younshin Kim, Songrim Jang, Doowhan Choi, Jung Ha Park, Seung Jun Yoo
  • Patent number: 11335893
    Abstract: A manufacturing method of OLED microcavity structure is provided. The manufacturing method includes: forming a reflective anode on a substrate; forming a transparent conductive film layer having a thickness corresponding to a required pixel on the reflective anode; patterning the transparent conductive film layer and the reflective anode with a pixel mask corresponding to the required pixel to form a pattern of the required pixel; and repeating the above steps on a resultant structure surface according to display requirements until a pixel display structure required by a display device is obtained.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 17, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ying Han, Wei Liu, Jianye Zhang, Fengjuan Liu, Xing Zhang
  • Patent number: 11328876
    Abstract: A light-absorbing material contains a compound represented by the composition formula HC(NH2)2SnI3 and having a perovskite structure. A solid-state 1H-NMR spectrum, which is obtained by 1H-14N HMQC measurement in two-dimensional NMR at 25° C., of the compound includes a first peak at 6.9 ppm and a second peak at 7.0 ppm. A peak intensity of the first peak is equal to 80% or more of a peak intensity of the second peak.
    Type: Grant
    Filed: July 14, 2018
    Date of Patent: May 10, 2022
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Takeyuki Sekimoto, Michio Suzuka, Tomoyasu Yokoyama, Yoshiko Miyamoto, Taisuke Matsui
  • Patent number: 11309441
    Abstract: Discussed is a solar cell including a semiconductor substrate, a first tunneling layer entirely formed over a surface of the semiconductor substrate, a first conductive type area disposed on the surface of the semiconductor substrate, and an electrode including a first electrode connected to the first conductive type area.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: April 19, 2022
    Assignee: LG ELECTRONICS INC.
    Inventors: Jaewon Chang, Kyungjin Shim, Hyunjung Park, Junghoon Choi
  • Patent number: 11289327
    Abstract: Methods and precursors for depositing silicon nitride films by atomic layer deposition (ALD) are provided. In some embodiments the silicon precursors comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%).
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: March 29, 2022
    Assignee: ASM IP Holding B.V.
    Inventors: Antti J. Niskanen, Shang Chen, Viljami Pore
  • Patent number: 11257978
    Abstract: A photovoltaic device and a method of forming a contact stack of the photovoltaic device are disclosed. The photovoltaic device may include a first layer deposited on a semiconductor layer including a compound semiconductor material. The photovoltaic device may also include a dopant layer comprising tin (Sn) deposited on the first layer. The photovoltaic device may further include a conductive layer deposited or provided over the dopant layer to form a contact stack with the first layer and the dopant layer.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: February 22, 2022
    Assignee: UTICA LEASECO, LLC
    Inventors: Abraham Saldivar-Valdes, Octavi Santiago Escala Semonin
  • Patent number: 11257758
    Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. A first recess cavity is formed over a gate electrode, and a second recess cavity is formed over the epitaxial semiconductor material portion. The second recess cavity is vertically recessed to form a connector via cavity. A metallic cap structure is formed on the gate electrode in the first recess cavity, and a connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Li-Zhen Yu, Chia-Hao Chang, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
  • Patent number: 11257975
    Abstract: A photovoltaic cell may include a hydrogenated amorphous silicon layer including a n-type doped region and a p-type doped region. The n-type doped region may be separated from the p-type doped region by an intrinsic region. The photovoltaic cell may include a front transparent electrode connected to the n-type doped region, and a rear electrode connected to the p-type doped region. The efficiency may be optimized for indoor lighting values by tuning the value of the H2/SiH4 ratio of the hydrogenated amorphous silicon layer.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: February 22, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Cosimo Gerardi, Cristina Tringali, Sebastiano Ravesi, Marina Foti, NoemiGraziana Sparta', Corrado Accardi, Stella Loverso
  • Patent number: 11257974
    Abstract: The present invention relates to a solar cell comprising a heterojunction photoelectric device comprising, a front electrode layer, a back electrode layer comprising a metallic contact layer, a light-absorbing silicon layer arranged between said front electrode and said back electrode layers and a doped silicon-based layer arranged between said light-absorbing silicon layer and said back electrode layer, characterized in that said heterojunction photoelectric device further comprises a wide band gap material layer having an electronic band gap greater than 1.4 eV, said wide band gap material layer being applied on a surface of the light-absorbing silicon layer between said light-absorbing silicon layer and said doped silicon-based layer. The present heterojunction layer or stack of layers is compatible with thermal annealing and firing processes at T above 600° C.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: February 22, 2022
    Assignee: ECOLE POLYTECHNIQUE FÉDÉRALE DE LAUSANNE (EPFL)
    Inventors: Philipp Löper, Andrea Ingenito, Christophe Ballif, Gizem Nogay
  • Patent number: 11232914
    Abstract: A photovoltaic device, comprises (1) a first conductive layer, (2) an optional blocking layer, on the first conductive layer, (3) a semiconductor layer, on the first conductive layer, (4) n light-harvesting material, on the semiconductor layer, (5) a hole transport material, on the light-harvesting material, and (6) a second conductive layer, on the hole transport material. The light harvesting material comprises, a pervoskite absorber, and the second conductive layer comprises nickel. The semiconductor layer tray comprise TiO2 nanowires. The light-harvesting material may comprise a pervoskite absorber containing a psuedohalogen.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: January 25, 2022
    Assignee: Board of Trustees of Northern Illinois University
    Inventor: Tao Xu
  • Patent number: 11233162
    Abstract: The present disclosure is directed to a method of processing a solar cell device. The method comprises detecting at least one inconsistency at a surface of a semiconductor substrate having a solar cell active region formed therein. A deposition pattern is determined based on the location of the at least one inconsistency. A material is selectively deposited on the substrate according to the deposition pattern.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: January 25, 2022
    Assignee: The Boeing Company
    Inventor: Eric Rehder
  • Patent number: 11211537
    Abstract: Various embodiments of light emitting devices, assemblies, and methods of manufacturing are described herein. In one embodiment, a method for manufacturing a lighting emitting device includes forming a light emitting structure, and depositing a barrier material, a mirror material, and a bonding material on the light emitting structure in series. The bonding material contains nickel (Ni). The method also includes placing the light emitting structure onto a silicon substrate with the bonding material in contact with the silicon substrate and annealing the light emitting structure and the silicon substrate. As a result, a nickel silicide (NiSi) material is formed at an interface between the silicon substrate and the bonding material to mechanically couple the light emitting structure to the silicon substrate.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: December 28, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Michael J. Bernhardt
  • Patent number: 11201257
    Abstract: According to the embodiments provided herein, a method for doping an absorber layer can include contacting the absorber layer with an annealing compound. The annealing compound can include cadmium chloride and a group V salt comprising an anion and a cation. The anion, the cation, or both can include a group V element. The method can include annealing the absorber layer, whereby the absorber layer is doped with at least a portion of the group V element of the annealing compound.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: December 14, 2021
    Assignee: First Solar, Inc.
    Inventors: Sachit Grover, Dingyuan Lu, Roger Malik, Gang Xiong
  • Patent number: 11189739
    Abstract: The present disclosure provide a solar cell, including: a substrate, an interface passivation layer covering a rear surface of the substrate, and an electrode disposed at a side of the interface passivation layer facing away from the substrate, the interface passivation layer including a first interface passivation sub-layer corresponding to a portion of the interface passivation layer between adjacent electrodes, and a second interface passivation sub-layer corresponding to a portion of the interface passivation layer where disposed between the substrate and the electrode; a field passivation layer, at least partially disposed between the interface passivation layer and the electrode; and a conductive enhancement layer, at least partially disposed at a side of the first interface passivation sub-layer away from the substrate to enable carriers in the first interface passivation sub-layer to flow to the electrode, where a resistivity of the conductive enhancement layer is smaller than a resistivity of the fie
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: November 30, 2021
    Assignees: Jinko Green Energy (Shanghai) Management Co., LTD., ZHEJIANG JINKO SOLAR CO., LTD.
    Inventors: Jingsheng Jin, Bike Zhang, Xinyu Zhang
  • Patent number: 11180660
    Abstract: Photovoltaic devices such as solar cells, hybrid solar cell-batteries, and other such devices may include an active layer disposed between two electrodes. The active layer may have perovskite material and other material such as mesoporous material, interfacial layers, thin-coat interfacial layers, and combinations thereof. The perovskite material may be photoactive. The perovskite material may be disposed between two or more other materials in the photovoltaic device. Inclusion of these materials in various arrangements within an active layer of a photovoltaic device may improve device performance. Other materials may be included to further improve device performance, such as, for example: additional perovskites, and additional interfacial layers.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: November 23, 2021
    Assignee: CUBIC PEROVSKITE LLC
    Inventors: Michael D. Irwin, Jerred A. Chute, Vivek V. Dhas, Kamil Mielczarek
  • Patent number: 11180855
    Abstract: The present invention relates to a semiconductor manufacturing component for manufacturing a semiconductor device by using a substrate such as a wafer in a dry etching process, and a manufacturing method thereof. The semiconductor manufacturing component comprising a deposition layer covering an interlayer boundary according to the present invention comprises: a base material containing carbon; a first deposition layer formed on the base material; a second deposition layer formed on the first deposition layer; and a third deposition layer formed on the first deposition layer and the second deposition layer, and formed to cover at least one portion of a boundary line between the first deposition layer and the second deposition layer.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: November 23, 2021
    Assignee: TOKAI CARBON KOREA CO., LTD.
    Inventor: Sang Chul Lee
  • Patent number: 11177405
    Abstract: A thin film solar cell including a substrate, an insulating layer, a first electrode layer, a photovoltaic conversion layer and a second electrode layer is provided. The insulating layer is disposed on the substrate and includes a plurality of microstructures. An orthographic projection of the plurality of microstructures is a regular geometric shape or an irregular geometric shape regarding to a normal direction of the substrate. The first electrode layer is disposed on the insulating layer. A thickness of the first electrode layer is less than 1 ?m or is equal to 1 ?m. The photovoltaic conversion layer is disposed on the first electrode layer. The second electrode layer is disposed on the photovoltaic conversion layer.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: November 16, 2021
    Assignee: GIANTPLUS TECHNOLOGY CO., LTD
    Inventor: Che-Yao Wu
  • Patent number: 11145776
    Abstract: A multijunction solar cell assembly and its method of manufacture including first and second discrete semiconductor body subassemblies, each semiconductor body subassembly including first, second and third lattice matched subcells; a graded interlayer adjacent to the third solar subcell and functioning as a lateral conduction layer; and a fourth solar subcell adjacent to said graded interlayer being lattice mismatched with respect to the third solar subcell; wherein the average band gap of all four cells is greater than 1.44 eV.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: October 12, 2021
    Assignee: SolAero Technologies Corp.
    Inventor: Daniel Derkacs
  • Patent number: 11069737
    Abstract: Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor layer having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor layer and positioned to interact with electromagnetic radiation. The textured region can be formed from a series of shallow trench isolation features.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: July 20, 2021
    Assignee: SiOnyx, LLC
    Inventors: Homayoon Haddad, Jutao Jiang
  • Patent number: 11069527
    Abstract: A heterojunction device is provided. The heterojunction device includes a silicon (Si) substrate; and a film of silicon carbide (SiC) deposited on a surface of the Si substrate. The SiC has a Si:C ratio that increases or decreases from a SiC surface in contact with the Si substrate to an opposing SiC surface that is not in contact with the Si substrate.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: July 20, 2021
    Assignee: Board of Trustees of Michigan State University
    Inventors: Premjeet Chahal, Tim Hogan, Amanpreet Kaur
  • Patent number: 11069522
    Abstract: Methods and precursors for depositing silicon nitride films by atomic layer deposition (ALD) are provided. In some embodiments the silicon precursors comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%).
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: July 20, 2021
    Assignee: ASM IP HOLDING B.V.
    Inventors: Antti J. Niskanen, Shang Chen, Viljami Pore, Atsuki Fukazawa, Hideaki Fukuda, Suvi P. Haukka
  • Patent number: 11038069
    Abstract: A semiconductor substrate (1) having an active region (2) and a first surface and a second surface facing each other. A first type of passivating layer (5) is present for providing an electrical contact of a first conductivity type on a part of the first surface of the semiconductor substrate (1). A dielectric layer (4) is provided between the first type of passivating layer (5) and an active region (2) of the semiconductor substrate (1). Doping of the first conductivity type is provided in a layer (3) of the active region (2) of the semiconductor substrate (1) near the first surface. The lateral dopant level in the layer (3) of the active region (2) near the first surface is substantially uniform.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: June 15, 2021
    Assignee: Nederlandse Organisatie voor toegepast-natuurwetenschappeliik Onderzoek TNO
    Inventors: Maciej Krzyszto Stodolny, Lambert Johan Geerligs, Evert Eugène Bende, John Anker
  • Patent number: 11031520
    Abstract: The present disclosure provides methodologies for manufacturing photovoltaic devices. In particular, the disclosure relates to the use of hydrogen during manufacturing of photovoltaic devices for passivating defects in the silicon and addressing light-induced degradation. The methodologies in the present disclosures take advantage of generation and manipulation of hydrogen in the neutral or charged state to optimise defect passivation. Some of the methodologies disclose use thermal treatments, illumination with sub-bandgap photons, electric fields or defects in the silicon to control the state of charge or hydrogen, move hydrogen to different locations in the device or retain hydrogen at specific locations.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: June 8, 2021
    Assignee: NEWSOUTH INNOVATIONS PTY LIMITED
    Inventors: Stuart Ross Wenham, Alison Ciesla, Darren Bagnall, Ran Chen, Malcolm David Abbott, Brett Jason Hallam, Catherine Emily Chan, Chee Mun Chong, Daniel Chen, David Neil Payne, Ly Mai, Moonyong Kim, Tsun Hang Fung, Zhengrong Shi
  • Patent number: 10964486
    Abstract: The present invention relates to a dye-sensitized solar cell unit (1?) comprising a working electrode comprising a light-absorbing layer (10), a porous first conducting layer (12?) for extracting photo-generated electrons from the light-absorbing layer (10), wherein the light-absorbing layer (10) is arranged on top of the first conducting layer (12?), a porous insulating layer (105c) made of an insulating material, wherein the porous first conducting layer (12?) is arranged on top of the porous insulating layer (105c). The dye-sensitized solar cell unit (1?) further comprises a counter electrode comprising a second conducting layer (16) including conducting material, and a porous third conducting layer (106c) disposed between the porous insulating layer (105c) and the second conducting layer (16), and in electrical contact with the second conducting layer.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: March 30, 2021
    Assignee: Exeger Operations AB
    Inventors: Henrik Lindström, Giovanni Fili
  • Patent number: 10950740
    Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type region architectures, and the resulting solar cells, are described herein. In an example, a solar cell includes an N-type semiconductor substrate having a light-receiving surface and a back surface. A plurality of N-type polycrystalline silicon regions is disposed on a first thin dielectric layer disposed on the back surface of the N-type semiconductor substrate. A plurality of P-type polycrystalline silicon regions is disposed on a second thin dielectric layer disposed in a corresponding one of a plurality of trenches interleaving the plurality of N-type polycrystalline silicon regions in the back surface of the N-type semiconductor substrate.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: March 16, 2021
    Assignee: SunPower Corporation
    Inventors: David D. Smith, Ann Waldhauer, Venkatasubramani Balu, Kieran Mark Tracy
  • Patent number: 10900678
    Abstract: The present teachings relate to various embodiments of an hermetically-sealed gas enclosure assembly and system that can be readily transportable and assemblable and provide for maintaining a minimum inert gas volume and maximal access to various devices and apparatuses enclosed therein. Various embodiments of an hermetically-sealed gas enclosure assembly and system of the present teachings can have a gas enclosure assembly constructed in a fashion that minimizes the internal volume of a gas enclosure assembly, and at the same time optimizes the working space to accommodate a variety of footprints of various OLED printing systems. Various embodiments of a gas enclosure assembly so constructed additionally provide ready access to the interior of a gas enclosure assembly from the exterior during processing and readily access to the interior for maintenance, while minimizing downtime.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: January 26, 2021
    Assignee: KATEEVA, INC.
    Inventors: Justin Mauck, Alexander Sou-Kang Ko, Eliyahu Vronsky, Shandon Alderson
  • Patent number: 10825940
    Abstract: A polycrystalline silicon wafer is provided. The polycrystalline silicon wafer, includes a plurality of silicon grains, wherein the carbon content of the polycrystalline silicon wafer is greater than 4 ppma, and the resistivity of the polycrystalline silicon wafer is greater than or equal to 1.55 ?-cm.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: November 3, 2020
    Assignee: Sino-American Silicon Products Inc.
    Inventors: Cheng-Jui Yang, Huang Wei Lin, Yu-Min Yang, Kuo-Wei Chuang, Ming-Kung Hsiao, Yuan Hsiao Chang, Bo-Kai Wang, Wen-Huai Yu, Sung Lin Hsu, I-Ching Li, Wen-Ching Hsu
  • Patent number: 10794771
    Abstract: The present invention generally relates to composition and methods for downconverting light. In some embodiments, the composition and methods comprise an organic material, a nanocrystal, and a ligand capable of facilitating energy transfer between the organic material and the nanocrystal. In certain embodiments, the nanocrystal has a first excited energy state with an energy less than a triplet energy state of the organic material. The organic material, in some embodiments, may be aromatic and/or include one or more pi-conjugated carbon-carbon double bonds. In some cases, incident light may be absorbed by the organic material to produce two triplet excitons. The triplet excitons may then transfer to the nanocrystal via the ligand, where they can undergo recombination, resulting in the formation low energy photons.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: October 6, 2020
    Assignee: Massachusetts Institute of Technology
    Inventors: Daniel N. Congreve, Nicholas John Thompson, Mark W. B. Wilson, Mengfei Wu, Marc A. Baldo, Moungi G. Bawendi, Vladimir Bulovic
  • Patent number: 10770239
    Abstract: A thin film for an optoelectronic device includes a layered 2D perovskite material. The thin film including the layered 2D perovskite material forms a substantially or nearly single-crystalline highly uniform thin film with strongly preferential out-of-plane alignment of the inorganic perovskite layers. This single-crystalline, highly uniform, and highly aligned thin film of the layered 2D perovskite material may thereby facilitate efficient charge transport in an optoelectronic device.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: September 8, 2020
    Assignee: TRIAD NATIONAL SECURITY, LLC
    Inventors: Aditya Mohite, Hsinhan Tsai, Wanyi Nie, Mercouri Kanatzidis, Konstantinos Stoumpos
  • Patent number: 10770605
    Abstract: A photodiode comprising a photoactive spinel oxide layer is described. This photoactive spinel oxide layer forms a contact with both a light absorption layer of quantum dots, quantum wires, or quantum rods, and an inorganic substrate layer. In some embodiments, the inorganic substrate layer and the photoactive spinel oxide layer form an isotype junction. Methods of characterizing the photodiode are provided and demonstrate commercially relevant electrical and optoelectronic properties, particularly the ability to operate as a photodetector with a high photosensitivity. An economical process for preparing the photodiode is provided as well as applications.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: September 8, 2020
    Assignee: King Abdulaziz University
    Inventors: Wageh Swelm, Fahrettin Yakuphanoglu, Ahmed A. Al-Ghamdi, Yusuf Abdulaziz Al-Turki
  • Patent number: 10746614
    Abstract: A stretchable multimode sensor and a method of fabricating the same are provided. The stretchable multimode sensor may include a substrate which is formed of a flexible material and includes a pressure sensor area, an optical sensor area, a temperature sensor area and a switching element area, a pressure sensor which is disposed on the pressure sensor area and includes an amorphous metal, an optical sensor which is disposed on the optical sensor area and includes an amorphous metal, and a temperature sensor which is disposed on the temperature sensor area and includes an amorphous metal, and a switching element which is disposed on the switching element area and includes an amorphous metal.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: August 18, 2020
    Assignee: Korea University Research and Business Foundation, Sejong Campus
    Inventors: Sang Hun Jeon, Min Hyun Jung, Kung Won Rhie, Chang Jin Yun
  • Patent number: 10745797
    Abstract: According to the present disclosure, a process includes transporting of a foil structure in a coating region in a vacuum chamber, wherein the foil structure has a thickness of less than 40 ?m; and coating the foil structure by physical vapor deposition, which includes forming a gaseous coating material in the coating region; wherein the gaseous coating material includes carbon, such that a protective layer is formed that includes a carbon microstructure covering more than about 50% of the foil structure and having a fraction of pores or voids less than about 50%.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: August 18, 2020
    Assignee: VON ARDENNE ASSET GMBH & CO. KG
    Inventor: Maik Vieluf
  • Patent number: 10741782
    Abstract: A light-emitting device is optimized for radiative recombination and minimizes non-radiative recombination. The light-emitting device includes an emissive layer, a first electrode and a second electrode from which charges are generated, a first charge transport layer that injects charges from the first electrode into the emissive layer, and a second charge transport layer that injects charges from the second electrode into the emissive layer. At least one of the charge transport layers includes a mixture of a first nanoparticle population and a second nanoparticle population, and the first nanoparticle population and the second nanoparticle population are conductive nanoparticles that are energetically non-aligned as between the first nanoparticle population and the second nanoparticle population.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: August 11, 2020
    Assignee: Sharp Kabushiki Kaisha
    Inventors: James Andrew Robert Palles-Dimmock, Edward Andrew Boardman, Tim Michael Smeeton
  • Patent number: 10741706
    Abstract: A photovoltaic device includes a substrate layer having a plurality of three-dimensional structures formed therein providing a textured profile. A first electrode is formed over the substrate layer and extends over the three-dimensional structures including non-planar surfaces. The first electrode has a thickness configured to maintain the textured profile, and the first electrode includes a transparent conductive material having a dopant metal activated within the transparent conductive material. A continuous photovoltaic stack is conformally formed over the first electrode, and a second electrode is formed on the photovoltaic stack.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
  • Patent number: 10727258
    Abstract: This application provides a display device and an active array switch substrate thereof. The active array switch substrate includes: a substrate; active array switches, formed on the substrate, where the active array switch includes a source electrode; at least one solar structure, disposed on the source electrode, where the solar structure includes a solar cell; and a transparent electrode, covered on the solar cell. The solar cell includes an N-type layer, an I-type layer of a microcrystalline silicon structure, and a P-type layer sequentially stacked in a direction away from the source electrode.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: July 28, 2020
    Assignees: HKC Corporation Limited, Chongqing HKC Optoelectronics Technology Co., Ltd.
    Inventor: Yu-Jen Chen
  • Patent number: 10680114
    Abstract: A thin film transistor includes a substrate, a gate electrode disposed on the substrate, an active pattern disposed on the gate electrode, a source electrode electrically coupled to the active pattern and a drain electrode electrically coupled to the active pattern. The active pattern includes a first channel layer overlapping the source electrode and the drain electrode and a second channel layer overlapping the gate electrode. The second channel layer includes a plurality of high electron mobility regions. An electron mobility of each of the high electron mobility regions is greater than an electron mobility of the first channel layer.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: June 9, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Su-Hyoung Kang, Hyun-Gue Kim, Jong-Jun Baek
  • Patent number: 10593550
    Abstract: This application relates to the technical field of semiconductors, and teaches methods for manufacturing a semiconductor structure. One implementation of a method includes: forming a semiconductor layer at a surface of a to-be-etched material layer on a substrate; forming an amorphous carbon layer on the semiconductor layer; forming a patterned mask layer on the amorphous carbon layer; and etching the amorphous carbon layer, the semiconductor layer, and the to-be-etched material layer using the patterned mask layer as a mask. This application may improve uniformity of the amorphous carbon layer, so that a position of a pattern that is formed after the to-be-etched material layer is etched does not deviate from an expected position, and a shape of the pattern is an expected shape.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: March 17, 2020
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Erhu Zheng, Jinhe Qi