Abstract: A BiCMOS process where a base region is formed in a relatively highly doped n-type substrate region. Boron is implanted at two different energy levels to form the base region and a counter doped n region near the base collector junction to prevent impact ionization.

Abstract: A bipolar fabrication process, illustratively suited for integration into a conventional CMOS process to thereby form a BiCMOS integrated circuits is disclosed. The collector and base are formed through multiple implants and a single masking step to thereby provide a continuous low resistance collector region.

Abstract: In a semiconductor device manufacturing method for forming first and second bipolar transistors on a semiconductor substrate 1, a link base layer 5 for connecting a graft base layer (graft base layer 8) of the first bipolar transistor and an intrinsic base layer 12 to each other, and at least a part of a base layer 6 of the second bipolar transistor are formed simultaneously with each other, and then the link base layer 5 in a region where the intrinsic base layer 12 will be formed is removed by an etching treatment, and then by a selective epitaxial growth method, the intrinsic base layer 12 is formed in the region where the link base layer 5 is removed.

Abstract: A polysilicon emitter of a bipolar device is formed utilizing a self-aligned Damascene technique. An oxide mask is patterned over epitaxial silicon implanted to form the intrinsic base. The oxide mask is then etched to form a window. Polysilicon is uniformly deposited over the oxide mask and into the window. The polysilicon is then polished to remove polysilicon outside of the window. Etching of the oxide mask follows, with good selectivity of oxide over silicon. This selectivity produces a polysilicon emitter atop an intrinsic base, the base flush with the silicon surface rather than recessed because of overetching associated with conventional processes.

Abstract: A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.

Abstract: An embodiment of the present invention is a process for semiconductor device having a silicon substrate. The process comprises positioning at least one field implant mask and field implanting a silicon substrate around a bipolar active region in a substrate such that boron atoms are blocked out of an active region, and only the field region surrounding the active area is implanted, the implanting such that a predetermined layout area of a semiconductor device does not need to be increased to compensate for a BV.sub.bso problem.

Abstract: A two masking level process for a dual buried region epitaxial architecture forms a first masking layer on a surface of a P type substrate. The first masking layer exposes first and second surface portions of the substrate for N+ and P+ buried regions. N type impurities are introduced into the substrate through the first masking layer, so as to form N+ doped regions. A second masking layer is then selectively formed on the first masking layer, such that the second masking layer masks the first aperture, but exposes a second portion of the first masking layer that both includes and surrounds the second aperture. Boron impurities are then introduced through the exposed second aperture of the first masking layer, to a P+ doping concentration.

Abstract: A bipolar transistor has a performance and high reliability, which are by enhancing a withstand voltage between an emitter and a base. The bipolar transistor includes a first impurity diffusion layer in a semiconducting substrate, a first conductive film connected to the first diffusion layer, and an opening disposed in the first conductive film. A second impurity diffusion layer is formed in a portion, exposed from the opening portion, of the semiconducting substrate and is connected to the first impurity diffusion layer. A third impurity diffusion layer is formed so as to contain the second diffusion layer and side walls are formed on the side walls of the opening. A fourth impurity diffusion layer is formed in the third impurity diffusion layer in the opening surrounded by the side walls.

Abstract: A method for producing an electronic component with a plurality of layers fabricating in a laminated composite, comprising laterally structuring at least one of the layers having a p or n conductivity characteristic by forming one of the layers in a sieve shape with a multiplicity of openings therein on a second layer of a different p or n conductivity characteristic than that of the one of the layers so that a space charge zone is formed in the second of the layers at boundaries of the one of the layers along the openings in the one of the layers.

Abstract: A heterejunction bipolar transistor and a method for fabricating an HBT with self-aligned base metal contacts using a double photoresist, which requires fewer process steps than known methods, while minimizing damage to the active emitter contact region. In particular, a photoresist is used to form the emitter mesa. The emitter mesa photoresist is left on and a double polymethylmethacrylate (PMMA) and photoresist layer is then applied. The triple photoresist combination is patterned to create a non-critical lateral alignment for the base metal contacts to the emitter mesa, which permits selective base ohmic metal deposition and lift-off. By utilizing the double photoresist as opposed to a metal or dielectric for masking, an additional photolithography step and etching step is eliminated. By eliminating the need for an additional etching step, active regions of the semiconductors are prevented from being exposed to the etching step and possibly damaged.

Abstract: A bipolar transistor is provided whose emitter surrounds the base. The transistor has in some embodiments a high ratio of the emitter area to the base area and low collector and emitter resistances. Further, a transistor is provided in which a collector contact region is surrounded by the base. Consequently, a low collector resistance is obtained in some embodiments.

Abstract: Methods of forming bipolar junction transistors include the steps of forming a first insulating layer on a face of a semiconductor substrate containing a collector region of first conductivity type therein and then forming an opening in the first insulating layer to expose the collector region at the face. An extrinsic base region contact layer of second conductivity type is then formed on the first insulating layer and in the opening and then an extrinsic base region of second conductivity type is formed in the collector region, at the opening in the first insulating layer. Next, a second insulating layer is formed on the extrinsic base region contact layer and first insulating layer, using the first insulating layer as a mask to prevent contact between the second insulating layer and the collector region at the face.

Abstract: Method and apparatus for improving the high current operation of bipolar transistors while minimizing adverse affects on high frequency response are disclosed. A local implant to increase the doping of the collector at the collector to base interface is achieved by the use of an angled ion implant of collector impurities through the emitter opening. The resulting area of increased collector doping is larger than the emitter opening, which minimizes carrier injection from the emitter to the collector, but is smaller than the area of the base.

Abstract: In a semiconductor apparatus having a PNP bipolar transistor and high voltage resistance, there is formed an oxide insulating layer in the surface region of a P-type semiconductor substrate. In the above semiconductor substrate is formed a P-type collector layer so that at least a part of the P-type collector layer is in contact with said oxide insulating layer. In the surface region of said P-type collector layer is formed a P-type collector contact layer. An N-type base layer is formed in that region on the surface side of said P-type collector layer in which said P-type collector contact layer does not exist. A P-type emitter layer is formed on the surface side of said N-type base layer.

Abstract: The invention described herein includes, in one of its forms, a method for fabricating a semiconductor device having ledge material (148, 150, 152, 162) extending over an undercut region. The method comprises the step of forming a layer of material 164 in tensile stress over the undercut region, or region to be undercut. The layer of material in tensile stress can be a dielectric, such as silicon nitride, and provides support for the ledge material in subsequent processing steps.

Abstract: This is a method of fabricating a bipolar transistor on a wafer. The method can comprise: forming a doped emitter contact layer 31 on a substrate 30; forming a doped emitter layer 32 on top of the emitter contact layer, the emitter layer doped same conductivity type as the emitter contact layer; forming a doped base epilayer 34 on top of the emitter layer, the base epilayer doped conductivity type opposite of the emitter layer; forming a doped collector epilayer 36, the collector epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming an collector contact 38 on top of the collector layer; forming a base contact 40 on top of the base layer; forming a emitter contact 44 on top of the emitter contact layer; and selective etching the emitter layer to produce an undercut 45 beneath the base layer.

Abstract: Indium doping is used to make bases of bipolar transistors with superior operational characteristics.

Abstract: A method for reproducibly fabricating a thin base region of a vertical bipolar transistor therein, which has a high transfer speed and increases a current driving force, and a method for increasing the isolating effect of the vertical bipolar transistor through forming a second buried layer implanting N-type impurity into an upper peripheral portion of first buried layer and activating the implanted N-type impurity, then out-diffusing the activated N-type impurity at the same time as growing the epitaxial layer, so the second buried layer definitely separates the elements of the transistor. Both the first buried layer and the second buried layer define a portion of epitaxial layer to form an active region which functions as a collector region. A subcollector region is formed above first buried layer in active region, and a base region is formed at a first upper portion of the active region to overlay the subcollector region.

Abstract: A method for fabricating an HBT in which the subcollector-base junction, which contributes to the base-collector capacitance of the device, is reduced by using a selective subcollector. In particular, subcollector areas of the device that do not contribute to collector resistance reduction are eliminated, thereby reducing the subcollector area, which, in turn, reduces the base-collector capacitance. As such, the maximum power-gain frequency f.sub.max is increased.

Abstract: The present invention teaches a method for fabricating a bipolar junction transistor ("BJT") from a semiconductor substrate having a base region, wherein the BJT comprises an increased Early voltage. The method initially comprises the step of forming a patterned interlevel dielectric layer superjacent the substrate such that a segment of the substrate is exposed. Subsequently, a contact comprising a material having a grain size smaller than polycrystalline silicon is formed superjacent the patterned interlevel dielectric layer and the segment of the substrate exposed. The contact is then implanted with a dopant. Once implanted, the substrate is annealed to enable the dopant to diffuse from the contact into the base region impeded by the grain size to form an emitter region and thereby increase the Early voltage of the bipolar junction transistor.

Abstract: A self-aligned semiconductor component (10) includes a layer (14) having two openings (36, 38) and overlying a doped region (13) in a substrate (11). One (36) of the two openings (36, 38) is used to self-align a different doped region (22) and a portion (27) of an electrode (27, 31). The electrode (27, 31) has another portion (31) overlying the self-aligned portion (27) to increase the current carrying capacity of the electrode (27, 31). A different electrode is formed in the other one (38) of the two openings (36, 38) and has a smaller current carrying capacity than the other electrode (27, 31).

Abstract: In a method of manufacturing a bipolar transistor, a collector region having a first portion and a second portion around the first portion is covered with an insulating film and a polysilicon layer is formed on the insulating film, the polysilicon layer having an opening. The insulating film is then selectively removed about an area that is larger than the area of the opening to thereby expose the first and second portions of the collector region and form a gap between a part of the polysilicon layer and the second portion of the collector region. The gap is then filled with a silicon layer and impurities are doped to form an intrinsic base region in the first portion, followed by forming a side wall space to make the opening smaller than the original area.

Abstract: A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.

Abstract: In a process for manufacturing a bipolar transistor, an intrinsic base is formed by a selective epitaxial growth while the lower surface of a base electrode single crystal silicon film 33 and the surface of a collector epitaxial layer 3 are exposed. In this process, the intrinsic base 8 and an extrinsic base 34 are grown as a single crystal to form a self-alignment type bipolar transistor having a reduced parasitic capacitance between the base and the collector.

Abstract: A bipolar transistor (100) and a method for forming the same. A base-link diffusion source layer (118) is formed over a portion of the collector region (102). The base-link diffusion source layer (118) comprises a material that is capable of being used as a dopant source and is capable of being etched selectively with respect to silicon. A barrier layer (119) is formed over the base-link diffusion source layer (118).A base electrode (114) is formed over at least one end portion of the barrier layer (119) and base-link diffusion source layer (118) and the exposed portions of the barrier layer (119) and underlying base-link diffusion source layer (118) are removed. An extrinsic base region (110) is diffused from the base electrode (114) and a base link-up region (112) is diffused from the base-link diffusion source layer (118). Processing may then continue to fore an intrinsic base region (108), emitter region (126), and emitter electrode (124).

Abstract: A process for preparing a bipolar transistor for very high frequencies is described, which is especially advantageous for the preparation of heterobipolar transistors and leads to components with low parasitic capacities and low base lead resistance. The process includes forming a structured first layer with collector zone and insulation areas surrounding the collector zone on a monocrystalline lead layer. A series of monocrystalline transistor layers are grown on the first layer over the collector zone by differential epitaxy and a series of polycrystalline layers is grown at the same time over the insulation areas. A series of polycrystalline layers is designed as a base lead.

Abstract: In a bipolar junction transistor of an epitaxial planar type comprising a base region, an emitter region formed in the base region, and a poly-silicon layer as an emitter poly-silicon electrode layer overlying the emitter region, the poly-silicon layer being used as an impurity diffusion source for forming the emitter region in fabrication of the transistor, the emitter poly-silicon electrode layer comprises a poly-silicon film containing an additive of one of C, O, and P overlying the emitter region and a poly-silicon layer overlying the poly-silicon film. An impurity is doped in the poly-silicon layer and is diffused into the base region through the poly-silicon film to form the emitter region in the base region in fabrication of the transistor. The poly-silicon film contains the additive and serves to prevent the poly-silicon film and the poly-silicon layer from grain growth which badly affects the impurity diffusion for forming the emitter region.

Abstract: A bipolar control transistor, forming part of an integrated current-limiter device comprises inside an epitaxial layer superimposed over a semiconductor substrate of a first type of conductivity, a base region of a second type of conductivity accessible from a base contact and regions of collector and emitter of the first type of conductivity contained in the base region and accessible from respective collector and emitter contacts. The base region comprises at least one highly-doped deep-body region which contains almost completely said emitter region, a lightly-doped body region which contains the collector region and an intermediate-doped region which co-operates with the first deep-body region to completely contain the emitter region and a surface area of the base region that is included between the regions of collector and emitter.

Abstract: A SiGe-HBT structure for device integration on thin-SOI substrates is disclosed. The emitter and base regions are vertical while the collector contact is lateral in the otherwise MOS-like device structure. This allows one to integrate a SiGe base, the device capacitances are reduced, and the transistor can be combined with fully-depleted CMOS in a SOI-BiCMOS technology.

Abstract: A semiconductor device including a layer formed without being affected by a stepped ground pattern and a method of fabricating the semiconductor device are disclosed. Cap portions (30) (insulating layers) formed over trenches (13) and covering doped polysilicon (5) have an inclined surface (26) which satisfies Y/X <5 where X is the length of the inclined surface (26) in a direction of the surface of a body (50) and Y is the height of the inclined surface (26) from the surface of the body (50). Formation of the insulating layers having the smooth inclined surface satisfying Y/X<5 permits a first main electrode to be formed nondefectively without being affected by the ground pattern including the insulating layers.

Abstract: In a method of manufacturing a bipolar transistor, an oxide film pattern is formed on an epitaxial collector layer of a first conductive type which is formed on a buried layer of the first conductive type. A selectively-ion-implanted-collector (SIC) region is then formed in the collector layer, and after that, a base layer is grown on the SIC region with an inversely graded impurity distribution profile.

Abstract: A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.

Abstract: After a formation of a side wall of silicon nitride on an inner periphery defining an emitter hole passing through a silicon nitride layer and a heavily doped polysilicon base electrode layer, a silicon oxide layer on a collector region is isotropically etched so as to expose an upper surface of the collector region and a bottom surface of an inner peripheral portion of the heavily doped polysilicon base electrode layer, and a ring-shaped hollow space beneath the polysilicon base electrode layer is filled with a piece of polysilicon so that the dopant impurity is diffused from the doped polysilicon layer independently from a selective growth of a base layer over the collector region.

Abstract: A method of manufacturing a bipolar transistor including the steps of doping an impurity of the one conductivity type in a major surface portion of the semiconductor substrate to form a buried layer of the one conductivity type and growing an epitaxial layer on an entire surface on a major surface of the semiconductor substrate, forming a diffusion region of the opposite conductivity type in an emitter formation region on the major surface of the semiconductor substrate and forming a base connecting region in a base formation region to be in contact with the diffusion region of the opposite conductivity type, forming an insulating interlayer on the major surface of the semiconductor substrate including the diffusion region of the opposite conductivity type and the base connecting region, forming an emitter electrode layer contact hole reaching the diffusion region of the opposite conductivity type in an emitter formation region of the insulating interlayer and forming a collector region hole reaching the epit

Abstract: A collector-up bipolar transistor having an undercut region (522) beneath extrinsic regions of a base layer (510) and an emitter layer (508). The extrinsic emitter region is depleted of charge carriers and provides passivation for the extrinsic portion of the base layer (508). Contact to the emitter layer may be made by forming contacts on the top surface of the substrate (500) or in a recess in the backside of the substrate.

Abstract: Disclosed is a pillar bipolar transistor which has a bidirectional operation characteristic and in which a parasitic junction capacitance of a base electrode, and a method for fabricating the transistor comprises etching a substrate using a first patterned insulating layer as a mask to form first and second pillarss separated by a trench therein; injecting an impurity using a mask to form a collector under the first and second pillars and in the second pillar; depositing a first oxide layer and a first polysilicon layer thereon; polishing the first polysilicon layer using the first oxide layer as a polishing stopper; removing a portion of the first polysilicon layer and a portion of the first oxide layer to define an extrinsic base; etching the oxide layer formed on both sides of the first pillar to a predetermined depth to define a connecting portion and forming a buried polysilicon therein to form the connecting portion; depositing a second oxide layer and a second polysilicon layer thereon; polishing the s

Abstract: A bipolar transistor has a base rink structure epitaxially grown from an overhang portion of a poly-crystal silicon base electrode and an epitaxial collector layer and an intrinsic base structure grown on a concave central portion of the base rink structure after a diffusion stage of a dopant impurity into the base rink structure, and the intrinsic base structure is electrically connected through a buried collector region passing through the concave central portion into an epitaxial collector layer, thereby maintaining the dopant impurity profile in the intrinsic base structure without deterioration of transistor characteristics.

Abstract: A ring-shaped emitter region is formed either in a region a little toward an inner periphery or in a region a little toward an outer periphery in an upper layer portion of a ring-shaped base region of a bipolar transistor. A conductive layer is laminated through an insulating layer in a region surrounded by the ring-shaped emitter region provided a little toward the inner periphery of the base region, a conductive side wall is formed on the sides of the conductive layer and the insulating layer, and the ring-shaped emitter region and the conductive layer are connected through the conductive side wall. A metallic emitter electrode is connected to the conductive layer.

Abstract: In a method of manufacturing a bipolar transistor by forming emitter regions of PNP and NPN transistors with diffusion of impurity from the polycrystalline silicon film into the substrate, the B-doped polycrystalline silicon film is deposited on the interlayer insulating film in which the emitter holes of the PNP and NPN transistors are made. Further, the interlayer insulating film is deposited on this film, and the portion of the insulating film which situated on the NPN transistor region is removed. Then, the thermal treatment is carried out in a high-concentration P atmosphere, so as to change the portion of the film which is located on the NPN transistor region to a P-doped polycrystalline silicon film. With this thermal treatment, the P-type and N-type emitter diffusion regions are formed on the base regions of the PNP and NPN transistors.

Abstract: Disclosed is a fabrication of a bipolar transistor using an enhanced trench isolation so as to improve integration and performance thereof, comprising the steps of sequentially etching back portions corresponding to a trench using a trench forming mask to a predetermined depth of the buried collector to form the trench; filling an isolation insulating layer into the trench; polishing the isolation insulating layer up to a surface of the silicon oxide layer; sequentially forming a second insulating layer on the isolating insulating layer and the silicon oxide layer; removing the first polysilicon layer and the first insulating layer formed on an inactive region other than an active region defined by the trench; thermal-oxidizing the collector layer formed on the inactive region to form a thermal oxide layer; removing the second insulating layer and sequentially forming a third polysilicon, a third insulating layer and a second nitride layer; etching back layers formed on a portion of the first insulating layer

Abstract: The invention provides a heterojunction bipolar transistor which has a low reistance SiGe base and is high in current gain and cutoff frequency even at low temperatures near the liquid nitrogen temperature. The transistor fabrication process comprises forming an n-type collector layer on a silicon substrate and a dielectric film on the collector layer, forming a base electrode of p.sup.+ -type polysilicon having an opening on the dielectric film, isotropically etching the dielectric film on the collector layer by using the opening of the base electrode to form a window, forming an external base layer of p.sup.+ -type silicon on the collector layer exposed by the window, selectively etching the external base layer to form an aperture in a central region, forming a p-type SiGe intrinsic base layer in the aperture of the external base layer and then forming an n.sup.+ -type emitter on the intrinsic base layer.

Abstract: A very deep P.sup.+ diffusion step is performed prior to the definition of a self-aligning emitter/P.sup.+ region. Furthermore, the initial P.sup.+ region is formed with dimensions sufficiently narrow to allow the subsequent emitter/P.sup.+ formation step to overlap the deeper P.sup.+ step by enough distance for the P.sup.+ step to completely cover the deep P.sup.+ region with its significant lateral diffusion. In this manner, a low sheet resistance in combination with proper alignment of the P.sup.+ heavy region with the emitter region is obtained.

Abstract: Manufacturing a double polysilicon layer self-aligned type bipolar transistor. A polysilicon layer for emitter impurity diffusion is formed prior to the formation of a polysilicon layer for leading out a base. A first polysilicon layer containing impurities for base impurity diffusion is deposited over the entire surface of a semiconductor structure. After the first polysilicon layer is patterned into a predetermined shape, an intrinsic base layer is formed by thermally diffusing impurities from a base impurity diffusion source. Subsequently, a second polysilicon layer containing emitter impurities is formed over the base impurity diffusion source, and then patterning is performed such that the first and second polysilicon layers remain in a region narrower than the base impurity diffusion source. Thereafter, an emitter layer is formed by thermal diffusion.

Abstract: A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in emitter mask thicknesses is disclosed. The polysilicon emitter isolation provides for better electrical breakdown characteristics between the emitter and the base by protecting the dielectric layer between the polysilicon emitter and base regions from defects and contamination associated with the BiCMOS manufacturing environment. The polysilicon emitter is trenched into the semiconductor substrate in order to reduce transistor operation problems associated with hot electron injection. Consistent base widths improve transistor performance uniformity thereby improving manufacturability and reliability.

Abstract: A bonded, SOI wafer which has stepped isolation trenches and sublayer interconnections first formed in a bulk silicon wafer. After these process steps are complete, a thin polysilicon layer is formed on the planarized upper surface of the bulk silicon wafer. This thin polysilicon layer is then bound to an oxide layer on the surface of a separate wafer to form a bonded silicon-on-oxide structure. The entire assembly is, in effect inverted, and what had been the lower surface of the bulk silicon wafer, is removed to the bottom of the deepest trench step. In this bonded SOI structure, regions between the trenches are deep and suitable for bipolar device fabrication, while the trench steps form shallow regions suitable for fabrication of CMOS devices.

Abstract: A process for fabricating a bipolar junction transistor by forming a trench in a silicon substrate. A lightly-doped base region is formed adjacent to the sidewalls of the trench, and a heavily-doped base region is formed under the bottom of the trench. Silicon oxide layers are formed along the sidewalls and bottom of the trench with a contact window provided to expose part of the lightly-doped base region. A polysilicon layer is formed in the trench, and is heavily doped by a dopant which in turn diffuses into the lightly-doped base region through the contact window to form an emitter region. A collector region is formed in the upper surface of the lightly-doped base region.

Abstract: Disclosed is a fabrication of a hetero-junction bipolar transistor in which a base parasitic capacitance is fully reduced by using a metallic silicide as a base, comprising the steps of injecting an impurity in a silicon substrate to form a conductive buried collector region; growing a collector epitaxial layer on the buried collector region and forming a field oxide layer; selectively injecting an impurity into the collector epitaxial layer to form a collector sinker; sequentially forming a base layer and an first oxide layer thereon; patterning the first oxide layer to define an extrinsic base region; ion-implanting an impurity in the extrinsic base region using a patterned oxide layer as a mask and removing the patterned oxide layer; depositing a metallic silicide film thereon to form a base electrode thin film; forming a capping oxide layer of about 500 .ANG.

Abstract: A process for fabricating lateral bipolar junction transistor semiconductor device. Base and emitter regions are precisely aligned. The resulting lateral width of the base region of the transistor device is able be precisely controlled. A heavily-doped implantation region is formed underneath the base region of the transistor structural configuration such that electron carriers in the transistor are prevented from escaping from beneath the base region of the transistor.

Abstract: A method of self aligning an emitter contact includes forming a base layer (18) on a portion of a collector layer (16). An interface layer (22) is formed on the base layer (18) such that a portion of the base layer (18) remains exposed. An emitter layer (24) is formed on the collector layer (16), the interface layer (22), and the exposed portion of the base layer (18). An emitter cap layer (26) is formed on the emitter layer (24) over the previously exposed area of the base layer (18). An insulating layer (28) is formed on the interface layer (22). An emitter contact (36) is formed on the emitter cap layer (26) at the previously exposed area of the base layer (18). The insulating layer (28) isolates the emitter contact (36) from the base layer (18) and a subsequently formed base contact (38). The insulating layer (28) ensures isolation between the emitter contact ( 36) and the base contact (38) despite misalignment of the emitter contact (36) during formation.

Abstract: The fabrication of bipolar junction transistors in silicon-on-sapphire (SOS) relies upon the laser-assisted dopant activation in SOS. A patterned 100% aluminum mask whose function is to reflect laser light from regions where melting of the silicon is undesirable is provided on an SOS wafer to be processed. The wafer is placed within a wafer carrier that is evacuated and backfilled with an inert atmosphere and that is provided with a window transparent to the wavelength of the laser beam to allow illumination of the masked wafer when the carrier is inserted into a laser processing system. A pulsed laser (typically an excimer laser) beam is appropriately shaped and homogenized and one or more pulses are directed onto the wafer. The laser beam pulse energy and pulse duration are set to obtain the optimal fluence impinging on the wafer in order to achieve the desired melt duration and corresponding junction depth.