Abstract: A novel process is disclosed for fabricating semiconductor devices with self-aligned contacts. Characteristic of the resulting structure is a digitated electrode and a contiguous conductive region that contact first semiconductor regions and second semiconductor regions, respectively. The first semiconductor regions and the second semiconductor regions are formed in a semiconductor substrate, with each second semiconductor region underlying a finger of the digitated electrode. Advantageously, by forming a contiguous conductive region over the first semiconductor regions located between the fingers of the digitated electrode, it is not only possible to contact second semiconductor regions with a common electrode, but also to self-align the common electrode with the digitated electrode. Ohmic shorting between the digitated electrode and the contiguous conductive region is prevented by interposing an insulating region therebetween.

Abstract: A novel method of making a semiconductor device that comprises p-type III-V semiconductor material is disclosed. The method comprises heating of a graphite body such that the body serves as a sublimation source of carbon atoms that are incorporated into the III-V semiconductor material. Exemplarily, the carbon doped material is the base of a GaAs-based HBT.

Abstract: The switching speed of bipolar power rectifiers is increased by formation of misfit dislocations in the depletion region, spaced from the substrate/epitaxial layer interface, in order to reduce minority carrier lifetime. The misfit dislocations are formed by the introduction of germanium during epitaxy, and are distributed along the silicon/silicon-germanium interface. Preferably, the germanium containing layer is located proximate the center of the depletion region.

Abstract: According to a method of manufacturing a high-frequency bipolar transistor, a p-type base region is formed on an n-type silicon substrate. A first oxide film and a nitride film are formed on the base region. A base contact hole is formed by etching, and a first polysilicon film containing a p-type impurity and serving as a base electrode is formed thereon. A second oxide film having a thickness larger than that of the first oxide film is formed by thermal oxidation around the base contact hole to surround the first polysilicon film. A portion of the nitride film which is not covered with said second oxide film and a portion of the first oxide film therebelow are removed by etching to form an emitter contact hole. A second polysilicon film including an n-type impurity and serving as an emitter electrode is formed in the emitter contact hole. The n-type impurity in the second polysilicon film is diffused in the substrate by annealing to form an n-type emitter region.

Abstract: In a bipolar transistor, having a micronized structure for a high-speed LSI, which is fabricated by a self-alignment technology, a barrier insulating film is buried in a portion around an emitter layer so as to be deeper than a junction level between an active base layer and a collector layer. When a polysilicon film pattern which defines an active base region and serves as a portion of a base electrode is formed on a wafer surface, a surface portion of a photoresist serving as an etching mask is converted to a carbonized layer by ion implantation. When a micronized emitter layer is formed by a polysilicon-emitter technology, ion implantation is performed before deposition of the polysilicon film or an impurity is doped in the polysilicon film simultaneously with deposition, and rapid thermal annealing is performed so as to activate the doped impurity.

Abstract: In a method for manufacturing a heterojunction bipolar transistor using a silicon microcrystal as an emitter, a mask 4 having an opening on an element forming region of the main surface of an n-type silicon monocrystal substrate 1 serving as a collector, a p-type outer base 5 is formed on a part of the element forming region of the main surface of the substrate via the opening of the mask 4 by ion-implanting p-type impurity therein, a p-type inner base 6 is formed on the entire surface of the element forming region of the substrate 1 by ion-implanting p-type impurity therein after removing the mask 4, and an n-type emitter 8 is formed by depositing an n-type silicon microcrystal layer on the inner base 6 at a growth velocity of 15 .ANG./sec by a plasma chemical vapor deposition method in a state that the temperature of said substrate 1 is maintained at a constant temperature between 460.degree. to 550.degree. C.

Abstract: A vertical NPN transistor is fabricated in a silicon integrated circuit substrate growing an N-type epitaxial layer, forming a preliminary P-type base region in the surface of the epitaxial layer, covering the surface with a protective glass layer, selectively etching a hole in the glass layer at an emitter-designated place over the preliminary base region, depositing N-type impurities through the hole into the silicon surface to become the emitter, implanting P-type impurities, of a kind that diffuse faster than the N-type impurities, through the hole into the epitaxial layer and heating to at least anneal the substrate. The hole is then filled to provide electrical contact to the emitter.

Abstract: A method for preparing a germanium layer (22) adjacent to a germanium silicon layer (20). Initially, a P-germanium silicon layer (16) is deposited on to an N-germanium silicon layer (14). The continuous germanium layer (22) is formed by heating the layers (14 and 16) in a steam oxidation step to approximately 1000 degrees Centigrade to transform the P-germanium silicon layer (16) into the P-germanium layer (18) and a SiO.sub.2 layer (22). A method for forming a heterojunction bipolar transistor utilizing a P-germanium layer (50) is also disclosed.

Abstract: The invention relates to a method of manufacturing a non-planar HBT transistor comprising first the step of forming the emitter, the step of etching the device around the emitter as far as the level of the base layer, exposing a region for the collector contact, the emitter being protected, and then the step of forming the base contact by self-alignment on the emitter and the collector. This method utilizes steps of profile inversion, during which two dielectric layers of different materials are successively deposited, the first of which has a uniform thickness and the second of which has a non-uniform thickness and which are etched at different rates in order to cause chosen patterns to appear. The invention moreover permits forming concomitantly buried resistors. The device obtained is particularly compact and performant and the method requires only a very limited number of masking steps, which can be realized with a non-critical resolution.

Abstract: Disclosed herein is a bipolar transistor and a method of manufacturing the same. The present invention provides a bipolar transistor in which a collector layer, a base layer and an emitter layer are transversely arranged in sequence through a monocrystal silicon layer formed on an insulation layer of a semiconductor substrate and a method of manufacturing the same. According to the present invention, parasitic capacity between a base and a collector can be reduced and p-n junction capacity between the collector and the substrate can be removed, thereby to achieve high-speed operation.

Abstract: An integrated circuit bipolar transistor is described wherein the relative semiconductor electrode areas are established by an electrode pedestal that includes a base contact positioning feature and wiring constraints are relaxed by a base pedestal that facilitates the positioning of contact wiring that is independent of contact location. A heterojunction bipolar transistor having a base area less than twice as large as the emitter area is described.

Abstract: A fully self-aligned bipolar transistor having low emitter and base-resistances is formed in a semiconductor device. In one embodiment, a patterned masking layer is formed on an active device region of a semiconductor substrate. The patterned masking layer has an opening, within which a TiN sidewall spacer is formed. The active device region is selectively doped to form an intrinsic base, using the TiN sidewall spacer and patterned masking layer as a doping mask. An emitter electrode is formed on the intrinsic base by selective deposition of silicon. An extrinsic base is also formed in the active device region by doping. Self-aligned metal silicide contacts to the extrinsic base and the emitter electrode are formed and the TiN sidewall spacer is removed.

Abstract: A structure and process for fabricating a fully self-aligned high-performance bipolar semiconductor device is disclosed. In accordance with one embodiment of the invention, a substrate is provided having a first surface. A heavily doped buried layer is formed in the substrate extending from the first surface and a lightly doped epitaxial layer overlies the first surface. An isolation region is formed in the epitaxial layer dividing the epitaxial layer into an active surface region and an isolation region. A base electrode is formed on a first portion of the active surface region having an opening which exposes a second portion of the active surface region. An emitter electrode, which is self-aligned to the base electrode, overlies a portion of the base electrode and extends through the opening in the base electrode making contact with the second portion of the active surface region.

Abstract: Selective and non-selective epitaxial growth is utilized to form a bipolar transistor having self-aligned emitter and base regions. A substrate of semiconductor material of a first conductivity type is provided and a first layer of semiconductor material of a second conductivity type is non-selectively epitaxially grown on the substrate. An insulating element is formed on a portion of the first layer of semiconductor material and a second layer of semiconductor material of the second conductivity type is selectively epitaxially grown on the first layer such that a portion of the second layer laterally overgrows onto an upper surface of the insulating element. The lateral overgrowth forms an aperture in the second layer to expose a region of the upper surface of insulating element. A layer of insulating material is formed on the second layer to isolate the second layer of semiconductor material from a subsequent deposition of conductive material.

Abstract: A complementary NPN and PNP contactless vertical transistor structure is formed by a process that includes the steps of providing: (1) a buried layer and P-- tub for NPN; (2) a channel stopper for NPN, and a buried layer for PNP; (3) isolation oxide for NPN and PNP; (4) a sink for NPN, and a ground for PNP; (5) a base for NPN, and a sink for PNP; (6) a base for PNP; (7) a N+ poly implant for NPN emitter and PNP extrinsic base; (8) a P+ poly implant for NPN extrinsic base and PNP emitter; (9) poly definition; (10) silicide exclusion for resistors and diodes; (11) contacts; (12) first metal; (13) vias; (14) second metal; and (15) scratch protection.

Abstract: A fully self-aligned polycrystalline silicon emitter bipolar transistor. Self-alignment of the p.sup.+ base contact (12) is achieved by using oxidized sidewalls (8) (sidewall spacers) of the emitter mesa (7) as part of the p.sup.+ base contact implantation mask. Collector contact (13) alignment can be achieved using oxidized sidewalls (17) of polycrystalline silicon alignment mesas (14) defined in the same polysilicon as the emitter mesa (7) but deposited on oxide (2) rather than the implanted base region (5).

Abstract: Vertical buried emitter heterojunction bipolar transistors having greatly reduced emitter to base junction area and collector dimensions are fabricated in a gallium arsenide substrate to form an integrated circuit structure. The ability to scale these critical dimensions is made possible by forming a portion of the base along the side walls and bottom of a trench which has been etched in the upper two layers of a layered gallium arsenide structure. The base is formed by implanting beryllium into the surface of an upper layer, the trench sidewalls which are formed in an undoped layer, and the bottom of the trench which is an undoped layer formed on the buried emitter. A GaAs collector layer having reduced lateral dimensions is deposited in the trench and in part, on the surface of the layered structure. Since only a small portion of the base region (the bottom of the trench) is in direct contact with the heavily doped emitter layer, the emitter to base junction area can be significantly reduced.

Abstract: A bipolar transistor having an intrinsic base portion for forming emitter-base PN junction with an emitter region and an extrinsic base portion for connecting a base electrode is disclosed. A concavity is formed between the intrinsic and extrinsic base portions, and the intrinsic base portion is electrically connected to the base electrode through a passage formed under the concavity and through the extrinsic base portion. The emitter region is contacted at its side to an insulating film formed in the concavity.

Abstract: A bipolar VLSI process includes masking and patterning, implanting a P+ channel stop and locally oxidizing a lightly P-doped, monolithic silicon substrate to define a collector region. An N-type collector is implanted and the implants are diffused to form a shallow gradient P-N junction. Then, device emitter, base and collector contact features are photolithographically defined by two openings spaced along the length of the collector region. The collector region is formed in a keyhole shape with a wider end portion encompassed by the collector contact feature and adjoining opening and a narrower opposite end portion which includes the base contact and emitter features and intervening opening. Low resistivity P- and N-type regions are implanted in the substrate in the openings; the openings are covered by local oxidation; and the substrate surface region are exposed in the adjoining contact features.

Abstract: A process of fabricating semiconductor devices involving plural epitaxial layer growth steps.

Abstract: In a method of manufacturing a semiconductor device, when contact holes are to be formed in an insulating film formed on a monocrystalline or polycrystalline semiconductor layer, the contact holes can be formed using a polycrystalline semiconductor layer formed on the insulating film as a mask. Therefore, the lithographic step of forming the contact holes in the insulating film formed on the monocrystalline or polycrystalline semiconductor layer can be eliminated.

Abstract: A method of forming a bipolar transistor is provided, comprising the steps of: providing a semiconductor substrate including a first region of a first conductivity type; forming a layer of insulative material over a surface of the first region; forming a layer of conductive material over the layer of insulative material; patterning the first and second layers to form a generally vertical sidewall bounding an exposed portion of the first region surface; and epitaxially depositing a base region of a second conductivity type over the exposed portion of the first region surface and the sidewall such that the base region is in electrical contact with the second region.

Abstract: A method for fabricating a semiconductor device comprises the steps of forming the first semiconductor layer on a semiconductor substrate, forming a surface protection layer of antimony (Sb) or the material having Sb as its main component, executing the other steps necessary for the fabrication of the semiconductor device, removing the surface protection layer, and forming, on the first semiconductor layer thus exposed, the second semiconductor layer.

Abstract: A process and structure for resolving the divergent etching requirements of a relatively thick base oxide (62) and a relatively thin gate oxide (64) in a BiCMOS integrated circuit. The necessity of etching base oxide (62) is eliminated by extending nitride mask (58) over the extrinsic base region (86) so that the relatively thick base oxide (62) only covers intrinsic base region (60) and tab region (61). Base oxide (62) at tab region (61) is partially etched in the course of forming sidewall oxide filaments (78), resulting in the residual tab oxide (62'). An extrinsic base implant is performed in extrinsic base region (86) and tab region (61), with the presence of residual tab oxide (62') affecting the profile of the implant so that it is stepped. The resulting structure, after an anneal, is extrinsic base (87'), an intrinsic base (63) (formed prior to the extrinsic base implant), and an overlap region (88') common to both.

Abstract: A CMOS and bipolar fabrication process wherein a silicon dioxide layer initially formed over a silicon substrate is etched for forming separate collector and base/emitter regions for a bipolar device, and PMOS and NMOS regions for corresponding PMOS and NMOS devices. Buried layer implants are performed using a minimum number of masks, and then an epitaxial layer is grown over the exposed portions of the silicon substrate. The silicon dioxide walls between the devices provide full dielectric isolation between the devices, as well as between the collector and base/emitter regions of the bipolar device. Nonetheless, the oxide wall between the collector and base/emitter of the bipolar device is sufficiently small to allow the buried layer implants to joint under the wall for forming a conventional buried layer for the bipolar device. Because of the oxide walls, the minimum distance between devices may be 0.5 microns or less.

Abstract: A method of forming semiconductor device contacts includes the steps of: providing a semiconductor substrate having at least two features thereon whereat it is desired to make electrical connections; forming a layer of etch stop material having a first etch characteristic over each of the features; forming a layer of dielectric material having a second etch characteristic over each of the features; simultaneously etching at least two vias through the layer of dielectric material using an etchant selective to the layer of dielectric material so as to substantially stop on the layer of etch stop material, the at least two vias including a via over each of the features; and extending the vias through the layer of etch stop material so as to expose the features for subsequent electrical connections.

Abstract: There is provided a method for use in the fabrication of a transistor, the method including the steps of: providing a substrate of semiconductor material including a region of first conductivity type; forming a first layer of second conductivity type epitaxial semiconductor material over the region; forming a second layer of second conductivity type epitaxial semiconductor material over the first layer, the second layer of a relatively higher dopant concentration than the first layer; oxidizing a portion of the second layer; and removing the oxidized portion of the second layer to expose a portion of the first layer, the exposed portion of the first layer forming an intrinsic base region. The steps of forming the first and second layers are preferably performed using low temperature, ultra-high vacuum, epitaxial deposition processes.

Abstract: This invention pertains to a self-aligned trench-isolated emitter structure and the method for forming same. The emitter structure comprises a portion of a bipolar transistor which exhibits improved function due to the emitter structure. A single layer of conductive material forms both the emitter and base contacts in the transistor structure, which structure has particularly shallow emitter and base junctions (about 0.15 micrometer or less). The self-aligned emitter contact, isolated from the base contact by a dielectric filled trench, permits overall size reduction of the device, whereby junction area and accompanying leakage across junctions is reduced. In addition, when the structure of the bipolar transistor is such that the trench isolates the emitter area from both the base contact and the extrinsic base, it is possible to provide improved base conductivity without generating peripheral transistor effects.

Abstract: A process for fabricating a semiconductor device by forming a diffusion region in a first semiconductor wafer and bonding the surface of the first semiconductor wafer having the diffused region to a second semiconductor wafer to form a low resistance buried layer. The process includes further diffusion to provide an external electrical contact with the buried layer. Further enhancements are provided by selectively forming voids and/or selectively applying materials of greater and lesser conductivity on at least one of the semiconductor wafers before bonding, forming complex internal semiconductor structures in the bonded wafer structures.

Abstract: A method of forming a complementary bipolar transistor device includes the steps of: providing a substrate of semiconductor material including at least two electrically isolated N-type device regions having a generally planar common surface; forming a P-type buried subcollar region in a first of the device regions; forming an N-type buried subcollector region in a second of the device regions; forming an N-type base region in the common surface of the first device region; forming a layer of P-doped polysilicon over the base region in the first device region and over the second device region; patterning the layer of P-doped polysilicon to form an emitter contact generally centered on the base region of the first device region and a generally annular base contact on the second device region; forming a layer of insulating material over the patterned layer of P-doped polysilicon; forming a layer of N-doped polysilicon generally conformally over the device; patterning the layer of N-doped polysilicon to form a bas

Abstract: A semiconductor device is made from a body of semiconductor material having a layer of dielectric material and a first layer of conductive material over a main face of the body, the layers each having an opening therein through which an area of the main face of the body of semiconductor material is exposed. A second layer of conductive material is formed over the sides of the opening and the conductor material, whereby the second layer of conductive material is in conductive contact with the first layer of conductive material along the sides of the opening. Material of the second layer of conductive material is removed to a depth such that a portion of the main face of the body of semiconductor material is exposed but a sidewall of conductive material remains along a side of the opening and provides an electrically conductive connection between the first layer of conductive material and the body of the semiconductor material.

Abstract: A method of manufacturing a semiconductor device includes forming a base region and a collector region on an Si substrate, forming, on the base region, an emitter region of a semiconductor material having an energy gap larger than that of Si, forming an Si film on the emitter region, ion-implanting an element into a surface portion of the emitter region or at the interface of the emitter region and the Si film and a periphery portion of the interface, and simultaneously forming electrodes on the base and collector regions and on the Si film. A heterojunction bipolar transistor manufactured by the above method is also disclosed.

Abstract: Microfabrication and large scale integration of a device can be realized by using a planar heterojunction bipolar transistor formed by a process comprising successively growing semiconductor layers serving as a subcollector, a collector, a base, and an emitter, respectively, through epitaxial growth on a compound semiconductor substrate in such a manner that at least one of the emitter junction and collector junction is a heterojunction, wherein a collector drawing-out metal layer is formed by the selective CVD method.

Abstract: A process for the manufacture of a transistor device of the type having active regions e.g. an emitter (17) and a base (11) each contacted by isolated extended conductive regions (37, 33) respectively. At start of process a mesa structure is defined in layered III-V material (3, 5, 11 and 13). The sidewall of the mesa is covered by a conformal coating (27) of insulating material; and, lattice matched material (33) grown on the exposed adjacent material (25) to form a first extended contact. This then is covered by a further layer (35) of insulating material (35). The second extended contact (37) is then grown over the mesa active region material (13). This contact material (37) is isolated from the first contact material (33) by the remanent insulating material (27, 35). This process is applicable to the GaAs/GaAlAs III-V material system as also other material systems. Transistor devices produced by this process may be either bipolar or field-effect type.

Abstract: A device area (16) is defined in a semiconductor body (10) by forming at one major surface (12, 12a) of the body a step (11) having a side wall (11a) and top surface (11b) bounding the device area 16. A silicon layer (13) is deposited so as to cover the side wall (11a) and top surface (11b) of the step and an adjoining lower surface area (12c). Dopant impurities are introduced so that the side wall silicon region (13a) is shielded from the dopant impurities and the undoped side wall silicon region (13a) is later removed by selective etching. The silicon region (13c) on the lower surface area (12a) adjoining the step (11) is masked and the silicon region (13a) on the top surface (11b) at the step (11) removed to leave the doped silicon region (13c) on the one major surface (12a) for contacting a device region (29), for example the base region of a transistor, of the device area.

Abstract: A compact complementary transistor switch (CTS) memory cell structure utilizing both vertical PNP and vertical NPN transistors in gallium arsenide technology is described. The base region of the vertical PNP transistor merges with the collector region of the vertical NPN transistor. The collector region of the vertical PNP transistor merges with the base region of the vertical NPN transistor. The emitter of the vertical PNP transistor is at the top, and the emitter of the vertical NPN transistor is at the bottom in relation to the emitter of the vertical PNP transistor. This structure leads to improvements in memory density, performance and wireability of a memory array comprising many such cells. A novel yet simple process for making such compact CTS memory cells is also disclosed.

Abstract: A novel fabrication method is disclosed for fabricating a bipolar transistor having a digitated emitter electrode and a contiguous polysilicon region acting as a self-aligned base contact. The process substantially reduces the parasitic capacitances as well as eliminates the need for the intrinsic base region to be exposed to multiple etching, which results in the fabrication of small and reproducible base widths.A first polysilicon layer is deposited over the surface of a semiconductor substrate and, then, implanted with base dopants, which are driven into the surface of the active region by a furnace process for forming an intrinsic base region. Emitter dopants are next implanted into the first polysilicon layer. Subsequently, a nitride layer is deposited and the digitated emitter fingers patterned by selective etching.

Abstract: A bipolar transistor in which a base region and a collector lead-out portion is separated is disclosed. The base region and an active collector portion under the base region is surrounded by a narrow trench filling an insulating film, and the trench is in turn surrounded by the collector lead-out portion. A collector electrode is contacted to the upper surface of the collector lead-out portion such that the collector contact surrounds the active collector portion via the trench, in the plan view.

Abstract: This invention discloses a method of manufacturing an SST bipolar transistor, and the manufacturing method is capable of defining the size of a base region of the SST bipolar transistor. An insulating film and a spacer film serving as a spacer are sequentially formed in a bipolar transistor forming region on the main surface of a semiconductor substrate. Thereafter, the spacer film is patterned into a spacer film pattern for defining the size of the base region. A second insulating film, a base electrode pattern and a third insulating film are sequentially formed on the spacer film pattern. A first opening which reaches the spacer film pattern through the second insulating film, the base electrode pattern and the third insulating film is formed. The spacer film pattern is etched from the first opening to form a second opening having a diameter larger than that of the first opening. The insulating film exposed in the second opening is etched.

Abstract: An improved dual metallization process in which self-aligned tungsten contacts are formed to closely-spaced emitter or source sites in RF power silicon devices. Low-resistivity ohmic contacts are made by selectively depositing tungsten on the exposed silicon surfaces as a first metal layer without a photomasking process and after a dielectric layer deposition and via opening process. The metallization process is completed by depositing a second metal or polysilicon layer on the dielectric layer and through vias to selected tungsten contacts. The tungsten combines with doped silicon in the emitter or source regions to form the low-resistivity ohmic contacts without the requirement of a platinum or palladium deposition and siliciding step as in prior art. The tungsten is preferably chemical-vapor-deposited in a two-temperature step when a first few hundred Angstroms of tungsten are grown at a low temperature on the order of 250.degree. C.-350.degree. C.

Abstract: Disclosed is a bipolar transistor and a method of fabrication thereof compatible with MOSFET devices. A transistor intrinsic base region (54) is formed in the face of a semiconductor well (22), and covered with a gate oxide (44). The gate oxide (44) is opened, and doped polysilicon is deposited thereover to form a polyemitter structure (68) in contact with the base region (54). Sidewall oxide (82, 84) is formed on the polyemitter structure (60). A collector region (90) and an extrinsic base region (100) are formed in the semiconductor well (22) and self aligned with respect to opposing side edges of the polyemitter sidewall oxide (82, 84).

Abstract: A compressed vertical bipolar transistor configuration that eliminates one side of the standard symmetrical base contact, while also eliminating the requirement for a collector contact reach-thru. The bipolar transistor comprises: a collector layer; a base layer disposed over the collector layer; an emitter layer disposed over the base layer; a first sidewall insulating layer disposeed adjacent to and in contact with one side of the emitter layer, the base layer, and at least a portion of the collector layer; a second sidewall insulating layer disposed adjacent to and in contact with another side of the emitter layer and at least a portion of the base layer; and a base contact extension layer formed from heavily doped semiconductor material of the same conductivity type as the base layer, said base contact extension layer being in contact with and extending laterally from another side of the base layer.

Abstract: A fabrication method for a high speed and high packing density semiconductor device (BiCMOS) in which high speed polysilicon self-aligned bipolar transistors and high packing density CMOS are contained on the same wafer in such a manner that simplicity in fabrication is attained, while the high speed of operation and the high packing density of array are simultaneously realized.

Abstract: A semiconductor structure is provided comprising a bulk substrate of semiconductor material having a first-type doping conductivity in a first dopant concentration. A first layer of semiconductor material is epitaxially formed on the substrate, such first layer having the first-type doping conductivity in a second dopant concentration lower than the first concentration. A second layer of semiconductor material is epitaxially formed on the first layer, the second layer having a second-type doping conductivity opposite to the first-type doping conductvity and thereby forming a P-N junction with the first layer. A plurality of regions, comprising semiconductor material having the first-type doping conductivity and extending through the second layer and a predetermined distance into the first layer, are further included for providing electrical isolation between active devices formed in different regions of the second layer.

Abstract: A semiconductor apparatus is disclosed, in which the entire or part of an electron active region is formed by a superlattice structure semiconductor layer in which a plurality of different semiconductor layers, less than 8 monolayers, and containing a fraction or a binary compound semiconductor layers are alternately and epitaxially grown and a main current direction is selected to be in the direction perpendicular to the laminae of said superlattice layers.

Abstract: A structured semiconductor body based on a Si substrate and having monocrystalline semiconductor regions and barrier regions which contain polycrystalline silicon which have preferably been produced in an Si-MBE process. The barrier regions are provided to delimit the monocrystalline Si semiconductor structures to prevent undesired current flow, for example between two monocrystalline devices of an integrated circuit. The polycrystalline silicon of the barrier regions has a substantially lower electrical conductivity than the monocrystalline regions, and consequently it is possible to spatially selectively dope portions the barrier region so as to provide regions which electrically contact a monocrystalline silicon region. In a preferred embodiment a polycrystalline silicon region within the barrier region is doped so that it forms a pn-junction with the adjacent monocrystalline semiconductor region and can be used, for example, as an emitter zone of a bipolar device.

Abstract: A method of forming a bipolar transistor comprising the steps of forming a base region in a semiconductor structure and disposing an emitter region on a surface of a first portion of the base region, the emitter region having upper and side surfaces. An active base region is formed in the first portion of the base region and an inactive base region is formed in a second portion of the base region adjacent to the first portion and the side surface of the emitter region. A layer of insulating material is formed over a surface of the inactive base region and over the upper and side surfaces of the emitter region. Portions of such layer are selectively removed to expose the upper surface of the emitter region and a portion of the surface of the inactive base region, and to maintain a region of insulating material between the exposed surface portion of the inactive base region and the side surface of the emitter region.

Abstract: A self-aligned process for the fabrication of a walled-emitter transistor includes the formation of an isolated device island on the surface of a semiconductor wafer. A layer of dielectric is then formed on the wafer, leaving only part of the device island exposed. A `substitute emitter` of silicon nitride is then formed on the exposed part of the device island in the position which will subsequently be occupied by the emitter. The exposed surface of the device island is then oxidized, some oxide being formed beneath the periphery of the substitute emitter. Oxide spacers are then formed non-lithographically about the periphery of the substitute emitter, after which the substitute emitter is removed and a base is formed in the semiconductor thus exposed. An emitter is then formed in the exposed semiconductor.

Abstract: A heterojunction bipolar transistor having a planar surface topology, reduced lateral dimensions and a base electrode aligned to both the emitter and collector electrodes is fabricated by forming sub-collector, collector, base and one or more emitter layers on a substrate. An opening extending to the sub-collector layer is then formed and a first portion of the collector electrode is formed therein so that the sidewalls of the opening are not contacted by the first portion. Dielectric material is then formed between the sidewalls of the opening and the first portion of the collector electrode. A second portion of the collector electrode is then formed on the first portion of the collector electrode along with an emitter electrode so that the second portion of the collector electrode and the emitter electrode are substantially planar. After then exposing the base layer, the self-aligned base electrode is formed between the second portion of the collector electrode and the emitter electrode.

Abstract: A method for the manufacture of a planar, self-aligned emitter-base complex, whereby a semiconductor layer structure standard for hetero-bipolar transistors is first grown on a substrate, the base regions are subsequently etching through a mask technique and are provided with the base metallization and with a first dielectric layer and insulation implantations and spacers for electrical insulation of the base are manufactured, and, following thereupon, the emitter region is provided with the emitter metallization and with a third dielectric layer.