Abstract: A method of self aligning an emitter contact includes forming a base layer (18) on a portion of a collector layer (16). An interface layer (22) is formed on the base layer (18) such that a portion of the base layer (18) remains exposed. An emitter layer (24) is formed on the collector layer (16), the interface layer (22), and the exposed portion of the base layer (18). An emitter cap layer (26) is formed on the emitter layer (24) over the previously exposed area of the base layer (18). An insulating layer (28) is formed on the interface layer (22). An emitter contact (36) is formed on the emitter cap layer (26) at the previously exposed area of the base layer (18). The insulating layer (28) isolates the emitter contact (36) from the base layer (18) and a subsequently formed base contact (38). The insulating layer (28) ensures isolation between the emitter contact ( 36) and the base contact (38) despite misalignment of the emitter contact (36) during formation.

Abstract: This is a method of fabricating a bipolar transistor on a wafer. The method can comprise: forming a doped emitter contact layer 31 on a substrate 30; forming a doped emitter layer 32 on top of the emitter contact layer, the emitter layer doped same conductivity type as the emitter contact layer; forming a doped base epilayer 34 on top of the emitter layer, the base epilayer doped conductivity type opposite of the emitter layer; forming a doped collector epilayer 36, the collector epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming an collector contact 38 on top of the collector layer; forming a base contact 40 on top of the base layer; forming a emitter contact 44 on top of the emitter contact layer; and selective etching the emitter layer to produce an undercut 45 beneath the base layer.

Abstract: A method for the manufacture of a laterally limited single crystal region that is suitable for use as an active part of a transistor, including the steps of: a) providing a substrate made of a single crystal semiconductor material; b) forming a first layer on a surface of the substrate, said first layer being selectively etchable with respect to the substrate; c) forming a second layer on the first layer, the second layer being selectively etchable with respect to the first layer; d) providing an opening in the first and second layers so as to expose an area on the surface of the substrate; e) covering surfaces and sidewalls of the second layer with a third layer f) selectively etching the first layer with respect to the substrate and the second layer and the third layer so as to provide an undercut between the second layer and the surface of the substrate; g) forming a single crystal region on the exposed surface of the substrate by selective epitaxy without nucleation occurring at the surface of the third l

Abstract: A collector region is formed in a semiconductor substrate. An insulating layer is formed on the semiconductor substrate, and a non-monocrystalline silicon layer is deposited thereon. The non-monocrystalline silicon layer is annealed to obtain a polycrystalline silicon layer which is patterned into a polycrystalline silicon resistor. The polycrystalline silicon resistor is covered by an insulating layer. Thereafter, a base region is formed, and an emitter region is formed in the base region.

Abstract: A semiconductor device and method to reduce the size of bipolar transistors and decrease the number of steps required to fabricate the bipolar transistor by using a unitary contiguous oxide sidewall to separate a collector contact from the base, emitter and emitter contact. The device and method may also be used during the fabrication of BiCMOS devices.

Abstract: A bipolar transistor is provided in which the emitters do not traverse the base but terminate inside the top surface of the base. Each emitter is L-shaped in some embodiments. The base top surface has a polygonal or circular outer boundary. The transistor has a long emitter perimeter available for base current flow and more than two emitter sides (e.g., five sides) available for base current flow. Further, the transistor has a large ratio of the emitter area to the base area. Consequently, the transistor has low noise, high gain, high frequency range, and a small size.

Abstract: On manufacturing a bipolar transistor, a field silicon oxide layer (7) having a beaked edge portion (bird's beak portion) is formed by a heat oxidation process using a silicon nitride film (5) as an oxidation mask. In this event, an edge of the nitride film is boosted up as a boosted portion by an upper part of the beaked edge portion. The upper part of the beaked edge portion is etched to form an undercut portion under the boosted portion. The undercut portion is filled with a base leading polysilicon (10) having impurities. On forming an insulator film (11) on the base leading polysilicon in a heated atmosphere, an outer base region (14) is formed in an epitaxial layer (3) by making the impurities diffuse from the base leading polysilicon towards the epitaxial layer in the heated atmosphere. Between the epitaxial layer and an edge portion of a nonboosted portion of the nitride film, a silicate glass (12) containing impurities is buried.

Abstract: A method for producing a semiconductor device includes growing a collector layer, a base layer, and an emitter layer on a substrate; forming an emitter electrode, a tungsten film, and a silicon film services as an etching stopper on a prescribed region of the emitter layer; etching the emitter layer using the above-described films as a mask to expose the base layer; forming side walls on opposite side surfaces of the silicon film, tungsten film, emitter electrode, and emitter layer; forming a zinc oxide layer serving as an impurity diffusion source on the base layer and performing a diffusion to produce high purity concentration regions in the base layer; removing the zinc oxide layer by wet etching using hydrofluoric acid as an etchant; depositing a base metal on the base layer and removing an unnecessary portion of the base metal by ion milling for form base electrodes; selectively removing the silicon film; and forming an electrode in contact with the tungsten film.

Abstract: A method for producing a bipolar transistor completely surrounded by an insulating trench in a substrate. Insulating regions at the surface of the substrate can be produced by depositing an SiO.sub.2 layer on the basis of thermal decomposition of TEOS and subsequent structuring of the SiO.sub.2 layer. The insulating regions can be employed as a self-aligning mask for the production of a collector terminal and of a substrate terminal.

Abstract: The present invention provides a BiCMOS integrated circuit with bipolar, NMOS and PMOS transistors. In a bipolar transistor, an emitter buffer is provided to minimize a hot carrier effect. The emitter buffer is implanted using the same mask used for a base link. However, the n-type dopant is implant using a large angle, while the p-type dopant is implanted using a normal implant. A "base" oxide is grown over the implant region. This oxide ultimate isolates the emitter buffer from the polysilicon emitter contact section. Local interconnects are formed using a "dual-gate" technique, in which a tungsten silicide cap layer is formed over polysilicon to short pn junctions in the interconnect.

Abstract: The present invention is directed to a method for forming a self-aligned epitaxial base transistor in a double polysilicon type process using non-selective low temperature epitaxy (LTE) to form the base layer. The present invention utilizes a thin very heavily doped LTE layer that is both a conductive etch stop and a diffusion source for doping the extrinsic base of the transistor. The deposition of the non-selective LTE base layer is followed immediately by the deposition of the conductive etch stop layer. A layer of undoped polycrystalline semiconductor is deposited on the conductive etch stop layer and subsequently ion implanted. Oxide and nitride insulating layers are deposited and the structure is patterned using a highly directional reactive ion etch to form the emitter window leaving a thin layer of the polycrystalline layer. The thin polycrystalline layer is selectively removed in a KOH solution leaving the conductive etch stop layer.

Abstract: In one form of the invention, a method is disclosed for removing portions of successive layers of GaAs 34 and GaInP 32 comprising the steps of: performing an anisotropic reactive ion etch on the GaAs layer; and performing an isotropic wet etch on the GaInP layer, whereby a mesa formed as a result of the reactive ion etch and the wet etch has substantially vertical sidewalls, and further whereby GaInP/GaAs structures having dimensions of less than approximately 3.0 .mu.m may be fabricated.

Abstract: A high voltage bipolar transistor fabricated on a CMOS substrate without adding any additional process steps. During the CMOS n-well mask and implant steps an n-well is formed for the transistor. Next, during the CMOS field and deep boron implant steps a circular p-field is formed within the n-well. Finally, during the CMOS p+ mask and implant steps the p+ emitter is formed. The presence of the p-field between the emitter and n+ base provides high voltage protection.

Abstract: This invention discloses a process by which a silicon bipolar transistor can be fabricated having a polysilicon emitter region and a polysilicon base region by a single polysilicon deposition step. After conventional fabrication of the substrate, collector and base layers, a first dielectric layer is deposited over the developing wafer structure. The first dielectric layer is then etched in order to define polysilicon emitter, base and collector regions. Next, a polysilicon layer is deposited over the first dielectric layer and the etched regions. A planarization layer is deposited over the polysilicon layer, and the planarization layer and the polysilicon layer are etched so that polysilicon only remains in the defined polysilicon emitter, base and collector regions. The polysilicon emitter, base and collector regions are then implanted with dopants to provide the appropriate interfaces.

Abstract: A method of fabricating a semiconductor device includes the steps of forming a base diffusion layer in a predetermined region in a semiconductor substrate of a first conduction type, the base diffusion layer being of a second conduction type; forming first insulating films and simultaneously forming an emitter lead-out electrode and a collector lead-out electrode in regions above an emitter-contact-forming region and a collector-contact-forming region, the first insulating films extending on the emitter and collector lead-out electrodes, the emitter and collector lead-out electrodes including impurity corresponding to the first conduction type; forming second insulating films at sides of the emitter and collector lead-out electrodes; forming a base contact; forming a base lead-out electrode including impurity corresponding to the second conduction type; diffusing the impurity from the emitter lead-out electrode, the collector lead-out electrode, and the base lead-out electrode to form an emitter diffusion lay

Abstract: A self-aligned fully-walled monocrystalline silicon emitter-base structure for a bipolar transistor and methods for producing the structure are provided. The methods involve creating an oxide side wall surrounding a monocrystalline silicon emitter-base structure by first defining the emitter region in a base island region. Successive oxide layers are deposited on top of the emitter region and etched back to produce an oxide wall around the entire perimeter of the emitter region. In a preferred embodiment of the invention a metal silicide is also formed across the top of the base island region of the semiconductor outside of the emitter region. Since the extrinsic base region, outside of the oxide sidewalls, is entirely covered by a low resistance silicide film, the base contact area can be significantly reduced compared to prior art devices.The process results in a fully-walled emitter-base structure made of monocrystalline silicon which exhibits improved high-frequency performance.

Abstract: In a method for manufacturing a bipolar transistor with the SST structure in which a P-type base region consists of a P.sup.+ -type extrinsic base region, a P-type link base region and a P-type intrinsic base region, a silicon oxide film, for example, is formed in advance in a formation region of the P-type link base region and the P-type intrinsic base region on the surface of an N-type epitaxial layer, and a P.sup.+ -type polycrystalline silicon film and a silicon nitride film that cover at least the formation region of the P-type base region are formed. An emitter opening surrounded by a gap part and a base lead-out electrode consisting of the P.sup.+ -type polycrystalline silicon film are formed. A P.sup.+ -type extrinsic base region and a P-type intrinsic base region are formed by applying heat treatment after forming a BSG film on the surface so as to fill in the gap part.

Abstract: This is method for forming epitaxial structures on a substrate which comprises: forming a first epi layer on the substrate; removing one or more substantial portions of the first epi layer; forming a second epi layer over the first epi layer and adjacent said first epi layer; forming a masking layer over portions of the second epi layer which are not over the first epi layer; and substantially removing a portion of the second epi layer which is over the first epi layer to provide a substantially planar structure having different properties. Other devices and methods are also disclosed.

Abstract: A method of making a transistor comprising the steps of providing a structure having a collector layer 3, a base layer 5, and an emitter layer 7, one atop the other, forming a contact 9 on the emitter layer, removing a portion of the emitter layer to leave a relatively thick mesa region 13 with the contact thereon, a surrounding relatively thin ledge region 11 and an exposed portion of the base layer 5 and forming a contact on the exposed portion of the base layer 5. The emitter layer 7 is preferably GaInP, and preferably Ga.sub.x In.sub.1-x P, wherein x is in the range of approximately 0.50 to 0.52, and the base 5 is preferably GaAs. The ledge portion 11 has a thickness of about 700 Angstroms.

Abstract: A fabrication method for semiconductor devices connecting a multi-crystal semiconductor thin film and a semiconductor region including a high density of an impurity formed in a single crystal semiconductor substrate. After forming a N-type semiconductor region as the emitter by ion implanting, for instance, as into a P-type semiconductor region as the base, a polysilicon thin film 114 is deposited so as to be implanted with As ions and then heat treated. In this case, an amorphous portion of the N-type semiconductor region and an amorphous silicon thin film in contact therewith are transformed by solid phase epitaxial growth so as to form a single crystal semiconductor region, a single-crystalline silicon thin film, and a polysilicon thin film, thus forming a bipolar element having an emitter.

Abstract: A method of making an improved bipolar transistor and the transistor itself having a double-self-aligned device structure are disclosed. The method and the transistor device provide self-alignment of collector-base and base-emitter junctions to each other, in addition to self-alignment of the base and emitter.

Abstract: Semiconductor devices having a reduced parasitic capacitance while having a maximum acceptable current similar to those of prior devices, and a method of manufacturing thereof are disclosed. The inventive device has a hole at the bottom of which an insulating film separated from the hole walls is located, a semiconductor film being present in the hole, which is connected to the semiconductor substrate adjacent to the insulating film and a conductor film constituting a portion of the hole wall, and extends onto the insulating film so as to cover at least part of the film.

Abstract: An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Abstract: Generally, and in one form of the invention, a method is disclosed for contacting a feature on an integrated circuit comprising: depositing a removable planarizing material 14 around the feature 10 so that a portion of the feature 10 extends above the removable planarizing material 14; depositing a masking layer 18 above the removable planarizing material 14, the masking layer 18 covering all but an exposed region above the feature 10 and an area around the feature; depositing an interconnect contact material 20 on the exposed region; and removing the masking layer 18 and the removable planarizing material 14, leaving the interconnect contact material 20 deposited on the exposed region, whereby a reliable, low capacitance, electrical contact is made to a very small feature 10.

Abstract: A layer of silicon carbide (33, 38, 41) is utilized in forming a bipolar transistor (30, 40). The transistor (30, 40) is formed on a substrate (31, 32) that has a single crystal silicon surface. The layer of silicon carbide (33, 38, 41) is epitaxially formed on the single crystal silicon surface. Thereafter, a layer of silicon (34) is epitaxially formed on the layer of silicon carbide (33, 38, 41). The silicon carbide (33, 38, 41) functions as an active transistor layer or alternately is within the transistor's depletion region.

Abstract: A bipolar transistor device having reduced collector-base capacitance and advantageous extrinsic base resistance properties is fabricated by a self-aligned process. Successively formed first and second self-aligned masking spacers are utilized to define the collector-base junction area and to permit the conductivity of base link and base contact portions of the extrinsic base to be independently established.

Abstract: A method of manufacturing a heterojunction bipolar transistor is disclosed. On a base layer of a first semiconductor which contains at least one of gallium and arsenic as a constituent element, an emitter layer of a second semiconductor is formed which contains as a constituent element at least one of gallium and arsenic and which has a band gap larger that of the first semiconductor. Predetermined regions of the emitter layer and an upper portion of the base layer are removed to form a mesa structure. Then, a surface of a junction region of the base layer and the emitter layer of the formed mesa structure is treated using a phosphate etchant and a sulfur or sulfide passivating agent. After the surface treatment, the surface of the junction is covered with an insulating film.

Abstract: There is provided a method of fabricating a semiconductor device. This method includes the steps of: forming a collector layer, a base layer, an emitter layer, and a dummy layer; patterning the dummy layer and the emitter layer into a mesa structure; forming a base electrode on the base layer in self-alignment to the mesa structure, and simultaneously forming a base electrode material on the dummy layer; forming a surface planarization film on the base layer to cover sides of the mesa structure; and removing the base electrode material and the dummy layer. The removal of the dummy layer is performed by subjecting the dummy layer to an etchant through an opening in the base electrode material.

Abstract: A pre-processed substrate structure for a semiconductor device. A subcollector layer is spaced apart from a substrate by a dielectric. A relatively small, lightly-doped epitaxial feed-through layer extends through the dielectric between the substrate and the subcollector. A transistor constructed over the subcollector has very low collector-to-substrate capacitance. A plurality of devices on a common substrate are electrically isolated from each other by channel stops formed in the substrate around each device.

Abstract: In a bipolar transistor, having a micronized structure for a high-speed LSI, which is fabricated by a self-alignment technology, a barrier insulating film is buried in a portion around an emitter layer so as to be deeper than a junction level between an active base layer and a collector layer. When a polysilicon film pattern which defines an active base region and serves as a portion of a base electrode is formed on a wafer surface, a surface portion of a photoresist serving as an etching mask is converted to a carbonized layer by ion implantation. When a micronized emitter layer is formed by a polysilicon-emitter technology, ion implantation is performed before deposition of the polysilicon film or an impurity is doped in the polysilicon film simultaneously with deposition, and rapid thermal annealing is performed so as to activate the doped impurity.

Abstract: There is disclosed herein a bipolar transistor structure having a self aligned extended silicide base contact. The contact extends to the position of a base contact window located outside the perimeter of the isolation island on a contact pad formed over the field oxide. This allows the size of the isolation island to be kept smaller and allows a smaller extrinsic base region to be formed. The base contact is formed of titanium and titanium silicide where the titanium/silicide boundary is self aligned with the edge of the device isolation island. The silicide is formed by reacting the titanium which completely covers the exposed epitaxial silicon inside the isolation island. An anisotropically etched oxide sidewall spacer insulates the silicide from the sidewall of the silicide-covered, polysilicon emitter contact.

Abstract: A bipolar transistor is formed from epitaxial cubic boron nitride grown on a silicon substrate which is a three to two commensurate layer deposited by pulsed laser evaporation techniques. The thin film, cubic boron nitride bipolar transistor is in epitaxial registry with an underlying single crystal silicon substrate. The bipolar transistor is particularly suitable for high temperature applications.

Abstract: Disclosed is a process for preparing a semiconductor device which comprises a step of growing, in a molecular beam epitaxial growth apparatus, a P-type silicon epitaxial layer which becomes the base, on an N-type silicon epitaxial layer which becomes the collector; a step of growing, in a molecular beam epitaxial growth apparatus, an antimony doped N-type silicon amorphous layer which becomes the emitter, on said P-type silicon epitaxial layer; and a step of converting the above N-type silicon amorphous layer to an N-type silicon epitaxial layer by the solid phase epitaxy method according to the annealing heat treatment.

Abstract: A method for manufacturing a bipolar transistor in which the base, emitter and collector terminals are produced from a single, planar layer of, for example, polysilicon, directly deposited onto a substrate. The planar layer is doped by a first conductivity type for the base terminal. After masking with an implantation mask, covering a region of the planar layer for the base terminal and defining regions of the planar layer for the emitter and collector terminals, the regions for the emitter and collector terminals are doped by an implantation of a second conductivity type, the second conductivity type being opposite the first conductivity type. After a self-aligned supplementation of the implantation mask, for example, with the assistance of a spacer technique, with which the regions of the planar layer for the emitter and collector terminals are also covered, the planar layer is structured by anisotropic etching by using the supplemented implantation mask as an etching mask.

Abstract: A method for forming a grown bipolar transistor electrode contact wherein a substrate (12) is provided. A doped region (31) is formed within the substrate (12). A dielectric layer (26) is formed having an opening (36) which exposes a portion of the doped region (31). Conductive spacers (38) are formed adjacent a sidewall of the dielectric layer (26). A conductive region (34) is formed through either a selective process or an epitaxial process by using the conductive spacers (38) as a source for epitaxial or selective formation. The conductive region (34) forms the grown bipolar electrode contact by electrically contacting the doped region (31). The conductive region (34) is optionally overgrown in a lateral direction over a top surface of the dielectric layer (26) to form a self-aligned electrical contact pad for the doped region (31).

Abstract: A high voltage bipolar transistor (10) is fabricated in an N- HV/epitaxial well (12) formed by an N- substrate implant and the overlying portion of the N- epitaxial layer 12b. The N- substrate implant replaces the normal buried N+ collector layer, in effect extending the depth of the epitaxial layer to increase junction breakdown voltages. The collector is formed by buried N+ collector regions (14a and 14b) formed adjacent to, and on either side of, the N- substrate implant. The transistor is fabricated conventionally in the N- HV/epitaxial well, except that, to further enhance high voltage performance, P+ extrinsic base regions (23a and 23b) can be extended using optional deep P+ implants (reducing curvature effects which correspondingly reduces electric field, and thereby inhibits premature junction breakdown).

Abstract: A method is provided for use with an integrated circuit which includes a npn bipolar transistor on which a variable thickness oxide layer has been formed, the method for improving the radiation hardness of the transistor comprising the steps of: removing the variable thickness oxide layer; and forming a new oxide layer on the transistor, the new oxide layer having less overall volume than the removed variable thickness oxide layer.

Abstract: A process for fabricating a semiconductor device basically includes forming a boron implanted layer intended to be a base region by implanting boron ions to a substrate through a first opening, implanting fluorine ions to the substrate through a second opening serving to define an emitter-inner base formation region beneath the second opening and in the boron implanted layer to lower the boron ion concentration of that region only thereby lowering the peak carrier concentration of an inner base region than that of an emitter region to be formed later, and doping the region defined by a third opening with arsenic ions to form the emitter region with the inner base region underlying.

Abstract: A vertical bipolar transistor (10) and a lateral bipolar transistor (11) are formed wherein both transistors (10 and 11) have a substrate (12). A dielectric layer (22) is formed overlying the substrate (12), and a conductive layer (24) is formed overlying the dielectric layer (22). Another dielectric layer (26) is formed overlying the conductive layer (24). A device opening is formed through the dielectric layers (22 and 26) and the conductive layer (24). A conductive region (33) is formed within the device opening and overlying the substrate (12). For transistor (10), the conductive region (33) is doped to form an active base electrode region (36) and a first current electrode region (38). A second current electrode region is formed via a diffusion (16). For transistor (11), a base electrode is formed via a diffused base region (46), and first and second current electrodes are respectively formed via diffused regions (44 and 48).

Abstract: A vertical PNP transistor for use in an integrated circuit is disclosed. A P-type substrate serves as collector. An N-type epitaxial layer is formed on the substrate and serves as base. A P-type region is formed in the epitaxial layer and serves as emitter. An N.sup.+ -type localized buried layer is formed on the substrate in the area beneath the emitter. The localized buried layer covers less than all of the area under the emitter. An N.sup.+ -type sinker region is formed through the epitaxial layer, connecting to the localized buried layer and serving as a connection to the base of the vertical PNP transistor.

Abstract: Generally, and in one form of the invention, a multiple layer collector structure is provided which comprises a relatively thin, highly doped layer 12 and a relatively thick, low doped or non-intentionally doped layer 14.

Abstract: An electronic component especially a permeable base transister is provided as a composite of homoepitaxially grown layers so that space-charge zones defined by the permeable base are formed as pn-junctions between an n-conducting layer and a p-conducting layer.

Abstract: A base-coupled logic gate is characterized by input Schottky diodes that are directly formed on the base region of the switching transistor for the gate. A logic of this type provides flexible circuit arrangements and savings in required area, while achieving very high speeds. As a result of the savings in area, the buried layer capacitance of the gate is also reduced, which facilitates the high-speed operation of the circuit.

Abstract: A process for creating self-aligned vertically arrayed planar transistors. The preferred embodiment relates to the simultaneous fabrication of both NPN and PNP planar vertically arrayed transistors in a conventional monolithic, epitaxial, PN junction isolated, integrated circuit. A field oxide is employed to surface isolate the devices and assist in the self-alignment improvement.

Abstract: A process for producing a semiconductor device for an integrated circuit is disclosed. A patterned structure made of first polycrystalline silicon and a first thermal oxide film is formed on an underlayer or foundation. A protrusion or raised portion is formed by using the patterned structure as a mask. A first insulating region is formed around the protrusion. After removing the first thermal oxide film an remaining portion of the patterned structure is thermally oxidized to obtain second thermal oxide film while the peripheral area of the surface of the protrusion is exposed. A second polycrystalline silicon pattern layer with a high impurity concentration is formed so as to contact with the exposed surface of the protrusion and with sideface of the second thermal oxide film, and to extend onto the first insulating layer.

Abstract: A protective circuit for an input to a bipolar transistor (10) capable of operating in the microwave frequency range. In a first embodiment, a polysilicon diode (24) is connected across a base-emitter junction of the bipolar transistor (10). In a second embodiment, a polysilicon resistor (38) is connected in series with an emitter of the bipolar transistor (10), and the polysilicon diode (24) is connected across the series combination of the base-emitter junction and the polysilicon resistor (38). The layout of the transistor (10) and the islands of polysilicon (23, 25) housing the diode is critical since the bipolar transistor (10) is capable of operating in the microwave frequency range. In a first layout, an island of polysilicon (25) is centered between two transistor regions (47 and 48). In an exterior diode layout, a transistor region (51) is centered between two islands of polysilicon (23 and 25).

Abstract: A method of internally limiting current and providing overvoltage protection in a semiconductor device comprises providing a semiconductor device having at least a first junction wherein both sides of the junction have predetermined dopant concentrations and wherein the first junction is spaced apart a predetermined distance from either a second junction or current blocking means. The predetermined dopant concentrations and distance are such that when a predetermined voltage is applied to the device, a depletion region from the first junction encounters either a depletion region from the second junction or current blocking means, thereby pinching off current at a desired voltage. The pinch-off voltage may be varied by adjusting the distance between the first junction and either the second junction or current blocking means and also by adjusting the predetermined dopant concentrations.

Abstract: A bipolar transistor is provided with an external base region.

Abstract: An integrated circuit vertical bipolar transistor includes monocrystalline emitter, base and collector contacts for electrically contacting the transistor's emitter, base and collector regions, respectively. The collector, base contact and emitter contact are preferably insulated from one another by oxide regions which are formed from the monocrystalline collector and monocrystalline base contacts. Since all of the contacts are formed of monocrystalline material and the oxide isolation is formed from monocrystalline material, high performance devices are formed.The process of forming the transistor self aligns the base to the collector and the emitter to the base. The monocrystalline base contact is also self aligned to the base and the monocrystalline emitter contact is self aligned to the emitter. The process preferably uses epitaxial lateral overgrowth and selective epitaxial growth from a mesa region to form the monocrystalline contacts.

Abstract: A bipolar hetero-junction transistor has an emitter formed which consists of doped and hydrogenated semiconductor material which is at least partly in amorphous form. A high current gain (.beta.) is obtained due to the wide bandgap in the emitter material. Preferably, the layer forming the emitter consists of microcrystalline silicon which is doped and hydrogenated. This yields a small base resistance which is preferable for high frequency purposes. The amorphous bipolar hetero-junction transistor can be produced by a CVD-technique, by using a plasma or by photodissociation. The transistor having a microcrystalline emitter layer can be produced by one of the above methods or by heating an amorphous emitter layer.