Abstract: A bipolar integrated circuit requiring less silicon area is provided by the use of a three layer epitaxy on top of a substrate. The first epitaxial layer is of the same conductivity type as the substrate and adds additional height to the substrate surrounding the buried layer. The buried layer serves as a collector and it is surrounded by an isolation area. The top two epitaxial layers are of a conductivity type opposite to that of the substrate with the upper most epitaxial layer having a higher dopant density than does the middle epitaxial layer. A master mask is used to provide self-alignment between the isolation area, a collector plug which makes contact to the buried layer, and a base region.

Abstract: A process for making an inverted silicon-on-insulator semiconductor device having a pedestal structure. After the processing of polysilicon layers, dielectric layers, an epitaxial region and a nitride layer, a second substrate is bonded to the nitride layer and the first substrate is removed. This allows for an epitaxial region which is isolated from the substrate.

Abstract: Disclosed is a method of producing a bipolar transistor which enables an external base region, an intrinsic base region and an emitter region to be formed in self-alignment with respect to the base electrode. More specifically, the method comprises the steps of side-etching an insulating film formed underneath the base electrode by a wet etching process to provide an undercut portion, depositing polycrystalline silicon so as to extend into the undercut portion by low pressure CVD to thereby fill the undercut portion with the polycrystalline silicon, and subjecting the polycrystalline silicon to thermal oxidation, thereby simultaneously forming a sidewall spacer whereby the base electrode and the emitter electrode are electrically isolated from each other and an oxide film on the emitter forming region, the oxide film having high selectivity in anisotropic etching with respect to the substrate (silicon).

Abstract: A bipolar transistor structure wherein the emitter zone is produced by outward diffusion from etching residues which are formed by deposition of conductive material and re-etching, with the etching residues forming part of the emitter terminal region. In addition to individual transistors, pairs of transistors having coupled emitters can also be produced and employed in hig precision differential amplifiers. Memory cells can also be produced which have low surface requirements, particularly due to the reproduceable attainment of emitter widths below one micron. Since the methods enable the production of completely self-aligned transistors, they can be implemented with straightforward steps which are largely independent of lithography. Emitter widths in the range of about 0.2 to 0.5 microns can be produced.

Abstract: A semiconductor device comprising a semiconductor substrate with at least one semiconductor region formed in it, a polycrystalline silicon layer formed in contact with the semiconductor region and a metal layer formed on the polycrystalline silicon layer. The peripheral portion and outer edges of the polycrystalline silicon layer are covered with an insulation layer.

Abstract: In an NPN transistor, a contact base region, an active base region, and a further base region are formed in the silicon substrate. The further base region is between the contact base region and the active base region, and is adjacent to the contact base region and the active base region. The further base region has a depth shallower than that of the contact base region and deeper than that of the active base region. In the method of forming the bipolar transistor, a polysilicon semiconductor layer is formed on a semiconductor substrate. The polysilicon semiconductor layer is partially etched to form a base leading electrode and an emitter leading electrode. A semiconductor impurity is implanted into a base forming region of the silicon substrate via that portion where the polysilicon semiconductor layer is removed.

Abstract: The method of manufacturing a semiconductor device according to the present invention comprises the step of forming an opening in use for forming an emitter region. This step uses the independent etching characteristics of N and P type polysilicons to simplify the opening forming process, which is very complicated in the conventional method. To be more specific, the impurity doped in the first polysilicon layer at a high concentration is diffused into the second polysilicon layer adjacent to the first polysilicon layer. When the impurity doped in the first polysilicon layer is diffused into the second polysilicon layer, the diffused impurity dominantly determines the conductivity type of that portion of the second polysilicon layer, into which the impurity is diffused. Therefore, one of the first polysilicon layer and the second polysilicon layer portion is etched by a solution, independently of the other.

Abstract: A method of fabricating a bipolar transistor on a semiconductor substrate capable of operating at a high operating speed and formed in a compact construction. A first polycrystalline silicon layer is oxidized selectively to form areas for forming base electrodes and a collector electrode. Boron is implanted into the polycrystalline silicon layer in a high concentration to form the base electrodes, the silicon dioxide film is removed to form an opening from a region for forming an emitter, the side wall of the opening is oxidized, an inactive base is formed in the polycrystalline silicon layer, active base is formed in the inactive base by implanting boron in the inactive base. Then, the entire surface of the device is coated with an oxide film and a second polycrystalline silicon layer.

Abstract: A metal layer is formed by selective CVD method on an emitter region formed by using a field oxide film as a mask. Opening for ion-implanting an impurity for forming external base region is formed in the field oxide film by utilizing the metal layer and a metal layer creep up a bird's beak of the field oxide film as masks. An impurity is doped in a semiconductor substrate through the opening formed in the field oxide film to form external base region. The distance between the emitter region and external base region is controlled by a length of the metal layer creep up the bird's beak.

Abstract: A bipolar VLSI process includes masking and patterning, implanting a P+ channel stop and locally oxidizing a lightly P-doped, monolithic silicon substrate to define a long, narrow collector region. An N-type collector is implanted in the collector region. The implants are diffused to form a shallow gradient P-N junction. Then, device features requiring a predetermined spacing and size are photolithographically defined along the length of the collector region. The device features and the collector region are made long enough for the features to readily transect the collector region even if the mask is misaligned. The active transistor and the collector, base and emitter contacts are self-aligned with the collector region so as to take advantage of the noncritical spacing of the preceding steps. A single polysilicon layer used to form base, collector and emitter contacts and a triple diffusion transistor.

Abstract: A method of manufacturing an integrated circuit is set forth comprising a field effect transistor having an insulated gate (35) and a further circuit element having a first (9) and a second electrode zone (14) of opposite conductivity types. Simultaneously with the gate (35) a conductive pattern (11) separated by an insulating layer (34) from the first electrode zone (9) is provided on the first electrode zone (9). This pattern (11) provides a pair of the edge of the doping opening (12) for the second electrode zone (14). A second insulating layer (16) is provided on the pattern (11) and is removed locally by anisotropic etching in such a manner that in the doping opening (12) edge portions (17) (16) are left. Subsequently, a conductive layer (22) for connection of the second electrode zone (14) is provided, which extends over the second insulating layer (16), over the pattern (11) and over the edge portions (17) (16 ) into the opening (12) of reduced size and on the second electrode zone (14).

Abstract: An improved method for fabricating a bipolar transistor reduces base current resistance which heretofore has limited the switching frequency and current handling ability of bipolar transistors. The transistor base and emitter are formed as a diffusion through an emitter contact pedestal formed on an epitaxial layer over a substrate. Access to the n-type emitter is through the emitter contact pedestal while access to the lightly doped p-type base is through a nearby heavily doped p-type base insert. Electrical isolation between the pedestal and the base insert is ensured by forming oxide sidewall spacers on the emitter contact pedestal during the implant used to form the base insert. Defining the isolation with sidewall spacers permits reliable isolation of emitter and base insert while minimizing their physical separation.

Abstract: A transistor is formed according to the solid phase epitaxial growth which is one of the semiconductor integrated circuit device manufacturing techniques. A low-concentration impurity region is formed by selective solid phase epitaxial growth instead of using an epitaxial substrate. The solid phase epitaxial growth is performed twice, when a collector region is formed and when a base region is formed. The depth of collector and base regions are determined by the thickness of the solid phase growth layers, respectively.

Abstract: A method and product for monocrystalline semiconductor buried layer contacts formed from recrystallized polycrystalline buried layers.

Abstract: A bipolar transistor is constructed to include a substrate, a collector layer epitaxial grown on the substrate and a base layer ion implanted in the collector layer. Next a further epitaxial layer is grown on the collector layer over the ion implanted base layer. A base contact region is ion implanted in this further epitaxial layer between the surface of this further layer and the base layer. The base contact region surrounds and defines an emitter in the further layer. A base ohmic contact is formed on the surface of the further layer in a location overlaying and contacting the base contact region. An emitter ohmic contact is also formed on the surface of the further layer in contact with the emitter. Additionally a collector ohmic contact is also formed on this same surface in a position isolated from the emitter by the base contact region. The collector ohmic makes an electrical contact with the collector by utilizing the further layer as a contact pathway.

Abstract: A semiconductor substrate includes: a first monocrystalline semiconductive layer formed on the surface of a crystalline silicon substrate with the intervension of a first insulation film; a second insulation film set to the upper surface of the first monocrystalline semiconductive layer and provided with a plurality of apertures each having a specific pattern; and a second monocrystalline semiconductive layer which is epitaxially grown by the seed crystallization process and provided with the same crystalline characteristics as that of the first monocrystalline semiconductive layer.Accordingly, the preferred embodiment of the present invention provides an extremely useful semiconductor substrate which easily isolates the elements of semiconductor devices between layers of insulating film described above.

Abstract: A method for manufacturing a fully self-adjustsed bipolar transistor in which the emitter zone, the base zone, and the collector zone are aligned vertically in a silicon substrate; the collector is connected by means of a deeply extending terminal in the substrate, the inactive base zone is embedded in an insulating trench to separate the inactive base zone from the collector; the emitter terminal zone is composed of doped polycrystalline silicon and is separated from the inactive base zone by a silicon oxide layer. A fully self-adjusted bipolar transistor is produced wherein the emitter is self-adjusted relative to the base and the base is self-adjusted relative to the insulation. The number of method steps involving critical mask usage is low, and parasitic regions are minimized so that the switching speed of the component is increased. The transistor is used for integrated bipolar transistor circuits having high switching speeds.

Abstract: A bipolar transistor having self-aligned base and emitter regions is fabricated in a silicon layer which is epitaxially grown on a substrate so as to fill up a cavity formed through a polysilicon layer deposited on the substrate. The polysilicon layer is doped with impurities for creating an extrinsic base region in the epitaxially grown silicon layer and is insulated from the emitter electrode by a dielectric layer formed thereon. The dielectric layer can be provided by selectively oxidizing the polysilicon layer. Thus, the step formed at the emitter electrode is small and equal to the thickness of the dielectric layer, about 3000 .ANG., for example, thereby eliminating the faulty step coverage in the prior art self-aligned bipolar transistor usually having the step as large as 1 micron.

Abstract: A method of manufacturing a heterojunction bipolar transistor comprising the sequential steps of; forming an extra epitaxial layer (9) on a layered structure which consists of a collector layer (2), a base layer (3), and an emitter layer (4) provided on a semiconductor substrate (1) in that order; forming a recess (10) by selectively etching the extra epitaxial layer (9); and forming an emitter electrode (70a) and a resist mask (70a) in the recess (10) by way of self alignment scheme, where the resist mask (70a) covers the emitter electrode (60e). An extremely small-sized resist mask (70a) can be formed, and extremely small-sized emitter mesa (4a) is formed by applying wet etching to the epitaxial layer (9) and the emitter layer (4) using the resist mask (70a).

Abstract: An improved integrated circuit structure is disclosed comprising bipolar and MOS devices formed on the same substrate. The bipolar devices have at least the emitter and the collector contact portions formed from a polysilicon layer which results in raised contacts. The MOS devices are similarly formed with raised gate contact portions formed from the same polysilicon layer. Metal silicide is formed over at least a portion of the base, source, and drain regions to provide conductive paths to the base, source, and drain contacts. In one embodiment, the base, source, and drain contacts are also formed from the same polysilicon layer to permit formation of a highly planarized structure with self-aligned contacts formed by planarizing an insulating layer formed over the structure sifficiently to expose the upper surface of the contacts.

Abstract: A method for making a bipolar semiconductor device having silicide contacts which is compatible with the processing steps used in the fabrication of MOS devices. The present invention includes the use of sidewall spacers to limit the self-aligned implants of the extrinsic base and the silicide contact. The device is annealed so that the diffusion of the polysilicon layer which forms the emitter may be controlled. Since the emitter size may be controlled, the emitter to base contact area may be reduced resulting in improved device performance.

Abstract: Regions of the substrate which are to be the collector sinker and the active area of a bipolar transistor are isolated by forming a trench about them and filling it with a dielectric. The dielectric can be oxide formed in a LOCOS process. A dielectric body, which may be nitride, is formed on part of the active area, and base contacts implanted using it as a mask. Polysilicon is deposited over the whole and then cut to form future metallization-to-base contacts. The dielectric body is removed and the base implanted through the resulting aperture. Oxide spacers are formed on the sidewall of the aperture and polysilicon deposited. The polysilicon is doped and used to produce the emitter by driving the dopant into the substrate between the oxide spacers.

Abstract: An improved method is described for constructing one or more integrated circuit components including bipolar and MOS devices on a silicon substrate without damaging areas of the substrate wherein active elements of the integrated circuit components will be formed. The method comprises forming multilayer pedestals of masking materials over the active regions of the substrate and subsequently removing these masking materials using wet etching to avoid damage to the substrate by dry etching.

Abstract: A method for planarizing a semiconductor slice prior to its metallization is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of the platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar.

Abstract: A method of forming double polysilicon contacts to underlying diffused regions of a semiconductor body which includes forming first and second level electrically conductive silicon layers over the body which contact respective first and second diffused regions of the body. The diffused regions are formed such that said first diffused region is ringed by said second diffused region. The second silicon layer thus overlaps the first silicon layer. The top surfaces of the first and second silicon layers are silicided such that the silicide formed over the first silicon layer is aligned with the edge of the second silicon layer.

Abstract: A heterojunction bipolar transistor and method of manufacturing the same is disclosed in which, a semi-insulation layer and an external base layer sequentially epitaxially grown on a collector layer are selectively mesa-etched through a mask of an insulation film provided with an opening so that the external base layer, the semi-insulation layer and the collector layer are selectively exposed. Subsequently an internal base layer and an emitter layer are selectively epitaxially grown in sequence on the exposed regions of the external base layer, the semi-insulation layer and the collector layer. An emitter electrode is formed in a self-aligned manner through the opening of the insulation film. Thus, transistor performance is improved and element size accuracy is improved.

Abstract: A laminated film made of a first insulating film and a second insulating film having a selectivity of etching condition to the first insulating film is selectively formed on a first conductivity type semiconductor substrate to use the substrate under the laminated film as a base and emitter active region forming region. The laminated film remains until an anisotropically dry etching step is finished to prevent the base and emitter active region from damaging due to an etching atmosphere at anisotropically dry etching time.

Abstract: The present invention relates to a semiconductor device and a method of producing the same. According to this method, a lower diffusion layer of a double isolation diffusion area is attached to a surface of a substrate, an epitaxial layer being formed on the lower diffusion layer, the lower diffusion layer being largely outdiffused upwardly in the epitaxial layer and simultaneously an element diffusion area being deeply diffused from a surface of the epitaxial layer, and then an upper diffusion layer of the double isolation diffusion area being shallowly diffused from the surface of the epitaxial layer. Thus, the lateral expansion of the upper diffusion layer of the double isolation diffusion area can be suppressed and the integrated extent can be improved.

Abstract: The invention includes a method of manufacture of monolithic integrated VLSI circuits comprising bipolar transistors whose base regions are contacted in a self-aligned manner in proximity to the respective emitter regions by the use of silicide layers. The invention starts out from a process which, when using an insulating masking layer portion covering up the emitter area of the planar transistor, permits the self-aligned fabrication of emitter regions extending to the adjoining base region and to the base contacting region. Further embodiments of the process according to the invention permit the simultaneous manufacture of co-integrated CMOS circuits and of polycrystalline. Si-conductor leads whose resistances are reduced owing to the use of silicide layers.

Abstract: A three dimensional, bipolar wafer process for integrating high voltage, high power, analog, and digital circuitry, and structure formed thereby includes a wafer of non-compensated epitaxial strata on a heavily donor doped monocrystalline silicon substrate of <100> crystal orientation, which is etched and with three dimensional transistors formed in it. Passivation for and contacts to said circuits are established, and the circuits are interconnected. The high voltage and high power transistors include transistors of an H-bridge circuit, including at least one set of cascode double heterojunction transistors, the analog transistors include a bipolar transistor, and the digital transistors include transistors of a I.sup.2 L circuit. One method for constructing the wafer is by sequentially epitaxially depositing each strata in an UHV silicon-based MBE apparatus.

Abstract: A method of manufacturing a heterojunction bipolar transistor in which a collector region, a base region and an emitter region are successively formed on a compound semiconductor substrate, forming the emitter region by epitaxial growth in a concave portion formed on an electrode leading region at the base region.

Abstract: A process of fabricating a semiconductor device comprising the steps of forming a dielectric layer overlying a doped semiconductor layer, forming a first insulator layer on the dielectric layer, etching the dielectric layer and the insulator layer to form a bump region comprising coextensively patterned portions of the dielectric and insulator layers, forming a second insulator layer partly on the doped semiconductor layer and partly on the bump region, conformally forming on the second insulator layer an undoped polycrystalline semiconductor layer having a step portion, forming on the polycrystalline semiconductor layer a planarizing layer covering the step portion of the polycrystalline semiconductor layer, etching back the polycrystalline semiconductor layer and the planarizing layer until the second insulator layer has a surface portion exposed over the bump region, etching the first and second insulator layers with the remaining portion of the polycrystalline semiconductor layer used as a mask for formin

Abstract: A process of making an integrated injection logic (I.sup.2 L) semiconductor structure is disclosed which is particularly advantageous for implementation in a group III-V compound semiconductor such as gallium arsenide. By use of "regrowth" techniques, the base region of the lateral transistor is made extremely thin (less than one-tenth micron). Utilization of a Schottky collector in a vertical transistor simplifies the structure.

Abstract: A process for fabricating a bipolar transistor structure having device and isolation regions fully self-aligned. The transistor is fabricated using a process wherein collector base and emitter layers are sequentially formed on a semiconductor substrate by a molecular beam epitaxy technique. The emitter layer is covered by insulation layers and a photoresist layer is then formed on the insulation layer. The photoresist layer is masked, exposed and developed to provide a pattern which is used as an etch mask to form both the device emitter area and isolation areas. The isolation areas, the emitter region and the base and collector regions are therefore formed.

Abstract: The heterojunction bipolar transistor has a structure of wide band-gap transistor and comprises a collector region having an N-type GaAs layer, a base region having a P-type germanium layer formed on the N-type GaAs layer, and an emitter region having an N-type semiconductor layer of mixed crystal of silicon and germanium formed on the P-type germanium layer. The mixed crystal of the N-type semiconductor layer may have a uniform distribution of silicon or a graded distribution of silicon in which a content of silicon is zero at the surface facing the P-type germanium layer and is continuously increased with distance from the surface facing the P-type germanium layer.

Abstract: A lateral bipolar transistor is described incorporating at least two grooves extending from the upper surface and spaced apart by a predetermined amount from which impurities are introduced to form an emitter region extending from the sidewall of one groove and a collector region extending from the sidewall of an adjacent groove with the base being the substrate material between the two regions. A plurality of grooves may be utilized to form a plurality of transistors with the grooves staggered to facilitate access to the ends of the grooves functioning as emitters and those functioning as collectors. The large vertical junction area formed by the side walls relative to the horizontal junction area at the bottom of the grooves and the uniform base width result in a high current gain lateral transistor.

Abstract: For a semiconductor device including a bipolar transistor, the emitter, a heavily doped base region surrounding the emitter, and base and collector contact regions, (the collector including a buried layer at an epitaxial layer/substrate interface of the semiconductor body), are formed by employing, on the epitaxial layer, layers of first and second resists, each resist layer comprising an impurity barrier, the second resist being attacked by an etchant relatively inactive with the first resist, by first or second photolithographic steps, of a sequence of only three photolithographic steps, forming three apertures in a first resist layer, to expose the subsequent emitter and two contact regions, then before each, or the, remaining photolithographic step of the sequence, providing a second resist layer, and exposing selectively, and coarsely through the second resist, the subsequent emitter, and either the collector contact region by the third photolithographic step, or the base contact region by the second pho

Abstract: Improved semiconductor devices having minimum parasitic junction area are formed by using multiple buried polycrystalline conductor layers to make lateral contact to one or more pillar-shaped epitaxial single crystal device regions. The lateral poly contacts are isolated from each other and from the substrate and have at least one polycrystalline pillar extending to upper surface of the device to permit external connections to the lower poly layer.The structure is made by depositing three dielectric layers with two poly layers sandwiched in between. Holes are anisotropically etched to the lowest poly layer and the substrate. A conformal oxide is applied over the whole structure and anisotropically etched to remove the bottom portions in the hole where the poly pillar and the isolation wall are to be formed and isotropically where the single crystal pillar is to be formed. The remaining oxide regions isolate the buried conductor layers, contacts, and isolation walls.

Abstract: For providing semiconductor zones (16, 18, 26) and contact metallization (19, 27) within an opening (9) in a self-registered manner, which opening is provided along its edge with polycrystalline connection parts (10) separated by an insulating material (15) from the metallization (19, 27), a protective layer (11) is formed which is maintained within the opening (9)until within this opening (9) the connection parts (10) are formed by anisotropic etching from a uniform layer of polycrystalline semiconductor material (10). The method is suitable for the manufacture of both bipolar transistors and field effect transistors.

Abstract: A method for making a semiconductor device having transistors comprising the active regions which are protected by polysilicon layer during the whole process from damages due to the other processing, that is dry etching, etc. and a minimized base region so as to provide a high operating speed and a minimium size thereof as well as lowest power consumption features.

Abstract: An improved bipolar device is disclosed having a polysilicon emitter formed over a base region of a silicon substrate with oxide spacer portions formed on the sides of the emitter and metal silicide portions formed over the base region adjacent the oxide spacers whereby the use of polysilicon for the emitter results in high gain as well as vertical shrinking of the device because of the shallow diffusion of the emitter into the base and the elimination of an extrinsic base region. The use of oxide spacers and metal silicide adjacent the spacers results in a shrinkage of the horizontal spacing of the device to lower the base-emitter resistance and capacitance to thereby increase the speed of the device.

Abstract: A process for manufacturing isolated semi conductor components in a semi conductor wafer of the type used in bipolar technology. In this process, polycrystalline silicon is deposited in a recess in a silicon substrate whose walls are insulated by a silicon nitride layer except for an opening formed in this nitride layer at the bottom of said recess. Then, the polycrystalline silicon is re-epitaxied so as to become monocrystalline silicon by thermal heating from the "nucleus" formed by the underlying silicon in said opening.

Abstract: Improved bipolar transistors having minimum base-collector and collector-substrate junction area are formed by using multiple polycrystalline (e.g. doped poly silicon) layers to make lateral contact to a pillar shaped single crystal device region. The lateral poly silicon contacts are isolated from each other and the substrate and extend to the upper surface of the device for external connections. The structure is made by depositing two dielectric-poly layer sandwiches, etching and oxidizing part of the poly silicon layers to provide isolated overlapping poly silicon regions, etching a first hole through both poly silicon regions to the substrate, etching a second hole to the lower poly silicon layer, and filling the first and second holes with single and poly-crystalline silicon, respectfully. A sidewall oxide is formed at the periphery of the top of the single crystal pillar for defining the emitter location without additional masking.

Abstract: Structures which improve the high frequency performance of bipolar discrete or integrated transistors through minimization of base contact size and hence collector-base capacitance (and collector-substrate capacitance, if integrated), are disclosed. The transistor comprises at least one elongate emitter arm and substantially minimum-dimension base contacts positioned one facing each side of each emitter arm at at least a minimum dimension from each emitter arm. A base diffusion area is positioned under and is minimum-dimensionally larger than the outer perimeter of the areas bounded by all of the smallest imaginary triangles each including a base contact and a facing emitter arm. Specific examples are described, namely a so-called "lozenge" structure, for relatively narrow emitters, a "cross" structure for wider emitters, and a "T" structure.

Abstract: An integrated injection logic (I.sup.2 L) semiconductor structure is disclosed which may be advantageously implemented in a group III-V compound semiconductor such as gallium arsenide. The base region of the lateral transistor is made extremely thin (less than one-tenth micron) by use of "regrowth" techniques. The structure of the vertical transistor is simplified by using a Schottky collector.

Abstract: A semiconductor device which comprises a semiconductor area having one principal surface, an emitter area and a collector area formed selectively and apart each other on the principal surface of said semiconductor area, a base area formed on said one principal surface between the emittor area and the collector area, an insulating film formed on said base area, and a high fusing point metallic film formed on said insulating film and covering said base area.

Abstract: A method for manufacturing a semiconductor device which comprises the steps of forming a first groove in that portion of a semiconductor substrate where an isolation is to be formed; selectively forming a second groove narrower than the first groove in that surface region of the semiconductor substrate which is surrounded by said first groove; depositing a masking material over the whole surface of the semiconductor substrate with a thickness less than half the width of the first groove and greater than half the width of the second groove; aniotropically etching the deposited masking material to eliminate substantially its thickness, thus leaving the masking material on the side walls of the first groove and entirely in the second groove; introducing an impurity into the bottom of the first groove to form an impurity region; filling the first groove with an isolating material; and forming a semiconductor element in that section of the semiconductor substrate which is surrounded by an isolation consisting of t

Abstract: A process for fabricating a bipolar transistor with a thin base and an abrupt base-collector junction includes the steps of depositing a thin layer of polycrystalline or amorphous silicon base material in a single crystal collector region, while in-situ doping the deposited silicon with boron atoms, and thereafter, recrystallizing the deposited silicon layer by thermal-pulse annealing at a temperature high enough to effect recrystallization and solid phase epitaxial regrowth while low enough to minimize interdiffusion of dopants between the base and collector.The process further includes providing the transistor fabricated by the aforedescribed steps with an abrupt base-emitter junction. This is accomplished by depositing n.sup.++ doped polysilicon with a LPCVD process and thereafter thermal annealing the polysilicon.