With Encapsulated Wire Patents (Class 174/251)
  • Patent number: 10361224
    Abstract: A display device comprises: a display panel; a metallic wiring formed in the display panel; and a semiconductor integrated circuit element connected to the display panel through a UV curing anisotropy conductive film, wherein the semiconductor integrated circuit element includes a plurality of bumps, the metallic wiring is electrically connected to the bumps through the UV curing anisotropy conductive film, the metallic wiring includes a plurality of openings, and at least one of the bumps is disposed between two adjacent openings closest to each other in the plurality of openings.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: July 23, 2019
    Assignee: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
    Inventor: Yuuichi Takenaka
  • Patent number: 10362675
    Abstract: Disclosed is a flexible circuit board having a three-layer dielectric body and four-layer ground layer structure. A flexible circuit board having a three-layer dielectric body and four-layer ground layer structure, according to the present invention, comprises: a first dielectric body; a second dielectric body facing the flat surface of the first dielectric body; a third dielectric body facing the bottom side of the first dielectric body; a signal line formed on the flat surface of the first dielectric body; a pair of first ground layers laminated on the flat surface of the first dielectric body and having the signal line therebetween; second ground layers laminated on the bottom side of the first dielectric body so as to correspond to the first ground layers; a third ground layer laminated on the flat surface of the second dielectric body; and a fourth ground layer laminated on the bottom side of the third dielectric body.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: July 23, 2019
    Assignee: GIGALANE CO., LTD.
    Inventors: Sang Pil Kim, Da Yeon Lee, Hwang Sub Koo, Hyun Je Kim, Hee Seok Jung
  • Patent number: 10314179
    Abstract: A manufacturing method of a circuit board structure is described as follows. An inner circuit structure including a core layer having an upper and an opposite lower surface, a first patterned circuit layer disposed on the upper surface and a second patterned circuit layer disposed on the lower surface is provided. An insulating material layer is formed on a portion of the first patterned circuit layer. A laser resisting layer is formed on at least a portion of the insulating material layer. A release layer is adhered to the laser resisting layer. A build-up process is performed so as to laminate a first and a second build-up circuit structures on the first and the second patterned circuit layers, respectively. A laser ablation process is performed on the first build-up circuit structure so as to form a cavity at least exposing a portion of the upper surface of the core layer.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: June 4, 2019
    Assignee: Unimicron Technology Corp.
    Inventors: Hung-Lin Chang, Ming-Hao Wu, Syun-Siao Chang, Cheng-Po Yu, Chi-Min Chang
  • Patent number: 10305066
    Abstract: There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size and/or utilize the side surface of an assembled flexible display.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: May 28, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Haejoon Son, JoungHo Ryu, SieHyug Choi
  • Patent number: 10290589
    Abstract: A foldable microelectronic assembly and a method for forming the same are provided. One or more packages comprising encapsulated microelectronic elements are formed, along with a compliant layer. The packages and the compliant layer are coupled to a redistribution layer. The compliant layer and the redistribution layer are bent such that the redistribution layer is non-planar.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: May 14, 2019
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed
  • Patent number: 10283446
    Abstract: A wiring board includes a base board and a plurality of wiring layers formed of a resin insulating film on the base board, wherein at least one of the wiring layers includes a fine wiring, a barrier film, which is not in contact with the fine wiring, is formed at a more outer side from the base board than the wiring layer including the fine wiring, and different types of resin insulating films are used for a wiring layer at an inner side of the barrier film close to the base board and a wiring layer at an outer side of the barrier film, respectively.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: May 7, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Junya Ikeda, Tsuyoshi Kanki
  • Patent number: 10252452
    Abstract: A method for sealing a fastener employs a mold which provided with an inlet port for molding material. The mold is then positioned over a fastener and the mold is sealed against a structure. A moisture cured polyurethane reactive adhesive (MCRPA) as a molding material is then heated and injected into the mold. Upon solidification of the MCRPA, the mold is then removed to expose the MCRPA to atmospheric moisture and cured to leave an in-situ molded cap formed over the fastener and sealed to the structure.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: April 9, 2019
    Assignee: The Boeing Company
    Inventor: Weidong Song
  • Patent number: 10251263
    Abstract: A method of producing a wired circuit board including an insulating layer and a conductive pattern, including: (1), an insulating layer having an inclination face, (2), a metal thin film provided at least on the inclination face, (3), a photoresist provided on the surface of the metal thin film, (4), a light shield portion of a photomask disposed so that a first portion, where the conductive pattern is to be provided in the photoresist, is shielded from light, and the photoresist is exposed to light through the photomask, (5), the first portion of the photoresist is removed to expose the metal thin film corresponding to the first portion, and (6), the conductive pattern is provided on the surface of the metal thin film exposed from the photoresist.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: April 2, 2019
    Assignee: NITTO DENKO CORPORATION
    Inventors: Yuu Sugimoto, Yoshito Fujimura, Hiroyuki Tanabe
  • Patent number: 10249559
    Abstract: Ball grid assembly (BGA) bumping solder is formed on the back side of a laminate panel within a patterned temporary resist. Processes such as singulation and flip chip module assembly are conducted following BGA bumping with the temporary resist in place. The resist is removed from the back side of the singulated laminate panel prior to card assembly. Stand-off elements having relatively high melting points can be incorporated on the BGA side of the laminate panel to ensure a minimum assembly solder collapse height. Alignment assemblies are formed on the socket-facing side of an LGA module using elements having relatively high melting points and injected solder.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jae-Woong Nah, Charles L. Reynolds, Katsuyuki Sakuma
  • Patent number: 10251270
    Abstract: A printed circuit board having multiple layers of circuitry, the printed circuit board including a first layer having a first cylindrical opening with a first diameter, the first cylindrical opening formed through at least the first layer and formed about a particular axis; and a second layer having a second cylindrical opening with a second diameter, the second cylindrical opening formed through at least the second layer and formed about the particular axis, where the first cylindrical opening is a portion of a conductive via, and where the second diameter is smaller than the first diameter.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: April 2, 2019
    Assignee: Innovium, Inc.
    Inventor: Yongming Xiong
  • Patent number: 10199329
    Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a pattern layer disposed on the encapsulant and covering at least portions of the encapsulant adjacent to the inactive surface of the semiconductor chip; vias penetrating through the encapsulant and connecting the pattern layer and the inactive surface of the semiconductor chip to each other; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: February 5, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Moon Hee Yi, Joo Hwan Jung, Yul Kyo Chung
  • Patent number: 10201082
    Abstract: The invention relates to a transparent conductive layer comprising non-conductive areas and conductive areas, wherein the conductive areas comprise an interconnected network of electrically conductive nanoobjects and in the non-conductive areas the nanoobjects are converted into particles and wherein the thickness of the conductive areas and the non-conductive areas differs less than 10 nm. The invention further relates to a process for producing a patterned transparent conductive film, the film comprising a substrate and a transparent conductive layer, and to a process for producing the patterned transparent conductive film.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: February 5, 2019
    Assignee: BASF SE
    Inventors: Rui Zhang, Garo Khanarian, Herve Dietsch, Andreas Kuehner
  • Patent number: 10187972
    Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and columns of via patterns formed in the plurality of layers, wherein via patterns in adjacent columns are offset in a direction of the columns, each of the via patterns comprising: first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; and at least one conductive shadow via located between the first and second signal vias of the differential pair. In some embodiments, at least one conductive shadow via is electrically connected to a conductive surface film.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: January 22, 2019
    Assignee: Amphenol Corporation
    Inventors: Marc Robert Charbonneau, Jose Ricardo Paniagua
  • Patent number: 10181663
    Abstract: A connector system is provided that includes a first connector and a second connector that are both coupled by a plurality of cables. The first connector is a stacked connector and includes a first terminal pair and a second terminal pair that are positioned in spaced apart card slots. The second connector includes a third and a fourth terminal pairs and the first and second terminal pairs are fixably connected to the third and fourth terminal pairs by the plurality of cables.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: January 15, 2019
    Assignee: Molex, LLC
    Inventor: Kent E. Regnier
  • Patent number: 10178776
    Abstract: A method for wiring differential signal lines and a PCB are disclosed. The wiring method includes: providing a rectangle-shaped glass fiber fabric formed of glass fibers which are woven and interlaced with each other and an adhesive filled therebetween; determining a wiring direction and obtaining a glass fiber bundle number of the glass fiber fabric in the wiring direction; equally dividing the glass fiber fabric into glass fiber units, and obtaining a width of each glass fiber unit according to a size of the glass fiber fabric in a direction perpendicular to the wiring direction and the number of the glass fiber units; determining a line distance and line widths of the differential signal lines; and according to the line distance and the line widths, forming the differential signal lines on a metal layer along the wiring direction to make the differential signal lines meet predetermined requirements.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: January 8, 2019
    Assignee: ZTE CORPORATION
    Inventors: Tao Guo, Fengchao Ma, Yuanwang Zhang
  • Patent number: 10133414
    Abstract: The invention provides a layered body for a touch panel in which metal migration is suppressed and changes in the electrical resistance of a fine metal wire are suppressed, and a touch panel. The layered body for a touch panel of the invention is a layered body for a touch panel including a substrate, fine metal wires which are disposed on the substrate, and an adhesive layer which is disposed on the fine metal wires, in which the amount of the metal contained per unit area in the fine metal wire is in a range of 0.01 g/m2 to 10 g/m2, the adhesive layer contains a benzotriazole-based compound, and the content of the benzotriazole-based compound is in a range of 0.05 mass % to 1.5 mass % with respect to the total mass of the adhesive layer.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: November 20, 2018
    Assignee: FUJIFILM Corporation
    Inventors: Kenji Naoi, Toshiaki Hayashi
  • Patent number: 10128903
    Abstract: A method includes providing a first circuit trace and a second circuit trace on a printed circuit board, determining a far end cross-talk (FEXT) response associated with the first circuit trace, determining a time delay associated with the second circuit trace, estimating a floquet response associated with the time delay, comparing the FEXT response with an interface frequency associated with the first circuit trace, comparing the floquet response with the interface frequency, and determining whether the floquet response cancels the FEXT response on the first circuit trace at the interface frequency.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: November 13, 2018
    Assignee: DELL PRODUCTS, LP
    Inventors: Arun R. Chada, Bhyrav M. Mutnury
  • Patent number: 10123414
    Abstract: A process of manufacturing a multilayer circuit board includes patterning insulating substrates on which conductors are formed to provide a signal conductor, a first ground conductor, and a second ground conductor. The insulating substrates including the signal conductor, the first ground conductor, and the second ground conductor are stacked and thermally crimped to form a laminate. An interlayer connection conductor is formed on a surface of the laminate by a Laser Direct Structuring process.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: November 6, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kuniaki Yosui, Bunta Okamoto, Isamu Morita, Jun Sasaki
  • Patent number: 10117337
    Abstract: Electrically isolating an electrical or electronic assembly having a carrier and one or more electrical or electronic components mechanically and electrically connected with the carrier, includes coating the carrier or at least one of the components or both entirely or partially with powder. The powder includes powder particles of electrically isolating material that have an average particle diameter of less than 1000 micrometers.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: October 30, 2018
    Assignee: VACUUMSCHMELZE GMBH & CO. KG
    Inventor: Harald Hundt
  • Patent number: 10092974
    Abstract: One aspect of the invention relates to a method for producing a circuit carrier. For this purpose, an electrically insulating carrier is provided, having an upper side and also an underside opposite from the upper side. A first metal foil and a hardening material are likewise provided. Then, an upper metallization layer, which is arranged on the upper side and has a hardening area, is produced. In this case, at least one contiguous portion of the hardening area is created by at least part of the hardening material being diffused into the first metal foil.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 9, 2018
    Assignee: Infineon Technologies AG
    Inventors: Mark Essert, Marianna Nomann, Thomas Nuebel, Guido Strotmann
  • Patent number: 10085339
    Abstract: Disclosed is a method of manufacturing an electroconductive nanowire network using an electron beam, the method comprising: forming a nanowire network using electroconductive nanowires; and welding junctions of the electroconductive nanowires by irradiating an electron beam on the nanowire network, wherein the electroconductive nanowires comprise silver (Ag) nanowires and the forming of the nanowire network comprises forming the nanowire network by spin-coating a suspension in which isopropyl alcohol (IPA) and the Ag nanowires are mixed.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: September 25, 2018
    Assignee: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)
    Inventors: Hyung Wook Park, Ji Soo Kim, Myoung Hoon Song, Yun Seok Nam
  • Patent number: 10068960
    Abstract: There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size and/or utilize the side surface of an assembled flexible display.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: September 4, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Yunho Ki, SieHyug Choi, YoungMin Yu, Sungwoo Kim, YoonDong Cho, SeYeoul Kwon
  • Patent number: 10061170
    Abstract: According to one embodiment, a method of manufacturing an electronic device, includes preparing a first substrate including a first basement and a first conductive layer, and a second substrate includes a second basement and a second conductive layer, opposing the first conductive layer and spaced from the first conductive layer, providing a protection layer on the second substrate, forming a first hole penetrating the second substrate by irradiating the second substrate with a laser beam in a position overlapping the protection layer, removing the protection layer and forming a connecting material electrically connecting the first conductive layer and the second conductive layer to each other via the first hole after removing the protection layer.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: August 28, 2018
    Assignee: Japan Display Inc.
    Inventors: Shuichi Osawa, Yoshikatsu Imazeki, Yoichi Kamijo, Yoshihiro Watanabe
  • Patent number: 10049989
    Abstract: A packaged semiconductor device includes a substrate and a contact pad disposed on the semiconductor substrate. The packaged semiconductor device also includes a dielectric layer disposed over the contact pad, the dielectric layer including a first opening over the contact pad, and an insulator layer disposed over the dielectric layer, the insulator layer including a second opening over the contact pad. The packaged semiconductor device also includes a molding material disposed around the substrate, the dielectric layer, and the insulator layer and a wiring over the insulator layer and extending through the second opening, the wiring being electrically coupled to the contact pad.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Po-Hao Tsai, Jui-Pin Hung, Jing-Cheng Lin
  • Patent number: 10037960
    Abstract: There is provided a connection structure of a circuit member including: a first circuit member having a first main surface provided with a first electrode; a second circuit member having a second main surface provided with a second electrode; and a joining portion which is interposed between the first main surface and the second main surface, in which the joining portion has a solder portion which electrically connects the first electrode and the second electrode to each other, in which the solder portion contains a bismuth-indium alloy, and in which an amount of bismuth contained in the bismuth-indium alloy exceeds 20% by mass and is equal to or less than 80% by mass.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: July 31, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Arata Kishi, Hiroki Maruo
  • Patent number: 9992859
    Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Mathew Manusharow, Krishna Bharath, Zhichao Zhang, Yidnekachew S. Mekonnen, Aleksandar Aleksov, Henning Braunisch, Feras Eid, Javier Soto
  • Patent number: 9955579
    Abstract: A printed circuit board includes first and second insulating layers, a wiring trace, a metal thin film, and a connection terminal. The wiring trace is formed on the first insulating layer. The metal thin film is formed on the wiring trace, and has a thickness larger than 0 nm and not more than 150 nm. The second insulating layer is formed on the first insulating layer to cover the metal thin film. The connection terminal is formed on the first insulating layer to be electrically connected to the wiring trace and exposed from the second insulating layer.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: April 24, 2018
    Assignee: NITTO DENKO CORPORATION
    Inventors: Hiroyuki Tanabe, Daisuke Yamauchi
  • Patent number: 9913373
    Abstract: A suspension board with circuit includes a metal supporting board, a conductor layer having a terminal capable of being electrically connected to the piezoelectric element and disposed above the metal supporting board at spaced intervals thereto, a first insulating layer disposed between the metal supporting board and the conductor layer so as to support the conductor layer, and a second insulating layer disposed on the first insulating layer and the conductor layer so as to expose the terminal. The first insulating layer includes a first portion including the terminal viewed from a thickness direction of the metal supporting board and a second portion disposed in a position different from that of the first portion viewed from the thickness direction. The thickness of the first portion is thinner than that of the second portion.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: March 6, 2018
    Assignee: NITTO DENKO CORPORATION
    Inventor: Yoshito Fujimura
  • Patent number: 9888569
    Abstract: A printed circuit board includes a core insulating layer including an isotropic resin, a first circuit pattern filled in a circuit pattern groove at an upper portion or a lower portion of the core insulating layer, a first insulating layer provided in a top surface thereof with a circuit pattern groove and covering the first circuit pattern, and a second circuit pattern to fill the circuit pattern groove of the first insulating layer. A material, such as polyimide, having an isotropic structure is employed for the core insulating layer, thereby preventing the substrate from being bent without glass fiber. Since the glass fiber is not included, the buried pattern is formed at the upper portion or the lower portion of the core insulating layer, so that the thin substrate is fabricated.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: February 6, 2018
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Sang Myung Lee, Byeong Ho Kim, Jae Seok Park, Yeong Uk Seo, Hyun Seok Seo, Chang Woo Yoo, Kyu Won Lee
  • Patent number: 9820391
    Abstract: A wiring board includes first insulating layers; first wiring layers; first via wirings; second insulating layers; second wiring layers; second via wirings; and a solder resist layer, wherein the first insulating layers are composed of non-photosensitive resin, wherein the second insulating layers, and the solder resist layer are composed of photosensitive resin, respectively, wherein the first surface of the uppermost first insulating layer and the first end surface of the first via wiring embedded in the uppermost first insulating layer are polished surfaces, wherein the first end surface of the first via wiring embedded in the uppermost first insulating layer is flush with the first surface of the uppermost first insulating layer, and wherein the wiring density of the second wiring layers is higher than the wiring density of the first wiring layers.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: November 14, 2017
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Noriyoshi Shimizu, Shoji Watanabe, Toshinori Koyama, Akio Rokugawa
  • Patent number: 9798419
    Abstract: A touch-sensitive display includes a plurality of electrodes configured to detect a touch input received at the touch-sensitive display device. A plurality of touch wires formed on a substrate are electrically connected to the electrodes and configured to detect a touch input received at the touch-sensitive display device. A plurality of first conductive patterns on the substrate are each connected to a touch wire and extend in a first direction from the corresponding touch wire. An insulation layer is disposed on the plurality of touch wires and first conductive patterns, and a plurality of second conductive patterns are disposed on the insulation layer. Each second conductive pattern contacts one of the touch wires via a contact hole in the insulation layer and at least partially overlaps a corresponding one of the first conductive patterns, while being separated from the corresponding one of the first conductive patterns by the insulation layer.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: October 24, 2017
    Assignee: LG Display Co., Ltd.
    Inventors: Seunghyun Kim, Jinyeol Kim, Sungpil Choi
  • Patent number: 9780043
    Abstract: A wiring board includes: a first insulating layer which is made of an insulating resin containing a thermosetting resin as a main component; a recess portion formed in an upper surface of the first insulating a layer; a first wiring layer formed in the recess portion and comprising an upper surface exposed from the first insulating layer; a via wiring penetrating the first insulating layer in a thickness direction thereof and comprising an upper end surface exposed from the first insulating layer; a second wiring layer formed on the upper surface of the first insulating layer to contact the upper end surface of the via wiring and the upper surface of the first wiring layer; and a second insulating layer which is made of an insulating resin containing a photosensitive resin as a main component and which is formed on the upper surface of the first insulating layer.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: October 3, 2017
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Wataru Kaneda, Noriyoshi Shimizu
  • Patent number: 9775231
    Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns comprising: dual diameter first and second signal vias forming a differential signal pair, the first and second signal vias being configured to accept contact tails of signal conductors of a connector; dual diameter ground shadow vias adjacent to each of the first and second signal vias, wherein the dual diameter shadow ground vias have a reversed diameter configuration with respect to the dual diameter first and second signal vias; and ground vias configured to accept contact tails of ground conductors of the connector.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: September 26, 2017
    Assignee: Amphenol Corporation
    Inventor: Marc B. Cartier, Jr.
  • Patent number: 9741650
    Abstract: A wiring board includes a wiring layer including a surface on which a recess is formed and a metal layer formed on a bottom surface of the recess. A surface of the metal layer facing away from the bottom surface of the recess is closer to the bottom surface of the recess than is the surface of the wiring layer.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: August 22, 2017
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Tatsuro Yoshida
  • Patent number: 9698390
    Abstract: The present disclosure relates to an extremely deformable structure comprising a basic displacement unit having an embedded form, in which m polygonal basic unit cells are disposed adjacent to each other, m separation parts are formed among the m basic unit cells, a junction part connecting the basic unit cells to each other is formed between the basic unit cells in which the junction part has a junction part pattern in which an external junction part disposed at the outer portion of the basic unit cell and an internal junction part which is not in contact with the outer portion of the basic unit cell are sequentially repeated, and the relative positions of the m basic unit cells are changed according to the junction part pattern, and thus, are activated (here, m is an integer of 4 or 6). Further, the present disclosure relates to a lithium secondary battery made from the extremely deformable structure.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: July 4, 2017
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Insuk Choi, Kee-Bum Kim, Kyu Hwan Oh
  • Patent number: 9699902
    Abstract: A printed circuit board is formed from a plurality of thinner PCBs stacked on top of each other with an intermediate metal interconnect material selectively positioned between adjacent PCBs. The metal interconnect material is selectively positioned on surface contact points of correspondingly aligned plated through holes on the adjacent printed circuit boards. The stacked printed circuit boards and intermediate metal interconnect material are laminated, thereby sintering the metal interconnect material and the surface contact points of the plated through holes to form electrical interconnects between plated through holes on adjacent printed circuit boards. The metal interconnect material is preferably the same as the plating material used to plate the through holes, such as copper.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: July 4, 2017
    Assignee: Flextronics AP, LLC
    Inventors: Weifeng Liu, David Geiger, Anwar Mohammed
  • Patent number: 9693448
    Abstract: A flexible circuit board includes a wiring layer, two photosensitive resin layers, and two electromagnetic interference shielding layers. The wiring layer includes at least one signal line, two ground lines and at least two gaps. Each gap includes two opening portions. The two photosensitive resin layers cover the signal line and the opening portions, and are connected to each end of each ground line. Each electromagnetic interference shielding layer covers one photosensitive resin layer away from the signal line, portions of the two ground lines not connected to the photosensitive resin layer, and portions of the gaps not covered by the two photosensitive resin layers, thereby causing the portions of each gap not covered by the two photosensitive resin layers to define a receiving chamber. Each end of each receiving chamber communicates with one opening portion of the corresponding gap to define a cavity.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: June 27, 2017
    Assignees: FuKui Precision Component (Shenzhen) Co., Ltd., HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., GARUDA TECHNOLOGY CO., LTD.
    Inventors: Xian-Qin Hu, Ming-Jaan Ho
  • Patent number: 9671542
    Abstract: Provided herein is a method for producing a nano polaroid film using a one-pack type or two-pack type blackening ink so that a single layer film may replace a conventional polaroid film generally produced by superposing various types of optical films, and especially, a method for producing a nano polaroid film consisting of one film and having excellent observability by coating a transparent nano pattern substrate with a functional ink that contains a blackening material, and then removing particles formed on protruding portions using an etching solution, and refilling the functional ink into grooves.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: June 6, 2017
    Assignee: InkTec Co., Ltd.
    Inventors: Kwang-Choon Chung, Insook Yi, MinHee Kim, Ji Hoon Yoo
  • Patent number: 9668345
    Abstract: A multilayer wiring board includes a first metal foil wiring layer that has at least two or more layers of metal foil wiring lines and is arranged on a mounting surface side for mounting a surface mount type component, a wire wiring layer that is arranged on an opposite side of the mounting surface, and in which an insulation coating wire is wired, and a first interlayer conduction hole that has a conduction part which electrically connects the metal foil wiring line positioned on a surface of the first metal foil wiring layer to at least one of the metal foil wiring line in an inner layer of the first metal foil wiring layer and the insulation coating wire of the wire wiring layer. A hole diameter of the first interlayer conduction hole varies in a board thickness direction of the multilayer wiring board.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: May 30, 2017
    Assignee: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Hiroyuki Yamaguchi, Seiichi Kurihara, Hiroshi Sakurai, Shunsuke Nukina
  • Patent number: 9661758
    Abstract: Cost effective and efficient methods to maximize printed circuit board (PCB) utilization with minimized signal degradation are provided. The methods include electrically isolating a segmented via structure by controlling the formation of a conductive material within a plated via structure by utilizing different diameter drills within a via structure for trimming the conductive material at the via shoulder (i.e., the rim of a drilled two diameter hole boundary). The trimmed portion may be voided in the via structure for allowing electrically isolated plated through-hole (PTH) segments. One or more areas of trimmed rims within the via structure are used to form multiple stair like diameter holes to create one or more voids in the via structure. As a result, the formation of conductive material within the via structure may be limited to those areas necessary for the transmission of electrical signals.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: May 23, 2017
    Assignee: SANMINA CORPORATION
    Inventors: Douglas Ward Thomas, Shinichi Iketani
  • Patent number: 9655246
    Abstract: An electronic component includes a multilayer capacitor and an interposer The multilayer capacitor includes an element body and a pair of external electrodes. The interposer includes a substrate, a pair of first electrodes, and is pair of second electrodes. The substrate includes first and second principal faces. The pair of first electrodes are disposed on the first principal face. The pair of second electrodes are disposed on the second principal thee. The element body includes a first portion and a pair of second portions. The first portion is covered by the external electrodes. The pair of second portions are located on both sides or the first portion and separated from the interposer. A width in a second direction of the pair of external electrodes is smaller than a width in the second direction of the element body and larger than a width in the second direction of the second portion.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: May 16, 2017
    Assignee: TDK CORPORATION
    Inventors: Masahiro Mori, Atsushi Sato, Tomoyoshi Fujimura
  • Patent number: 9633775
    Abstract: An electronic device mounting apparatus to be mounted with multiple electronic components, each of which includes at least one wire. The electronic device mounting apparatus includes a base unit and multiple pin units. The base unit includes a base wall and two side walls extending from the base wall. Each of the side walls has a first surface. The pin units are correspondingly mounted in the side walls and are spaced apart from one another. Each of the pin units has a wire-connecting segment having a connection portion that projects from the first surface, and two projecting portions that project from the connection portion and that define a slit therebetween. The slit is for a corresponding wire to be clamped therein by the projecting portions.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: April 25, 2017
    Assignee: BOTHHAND ENTERPRISE INC.
    Inventors: Chung-Cheng Fan, Yung-Ming Pan
  • Patent number: 9627255
    Abstract: A method for forming a semiconductor device package substrate including a fiducial mark is provided. The method of forming the package substrate includes forming a dielectric layer over a lower portion of the package substrate. A metal layer is formed over a fiducial region of the package substrate. The metal layer is etched to form a first signal line in the fiducial region. A passivation layer is formed over the first signal line. The passivation layer is etched over the first signal line to form a fiducial mark.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: April 18, 2017
    Assignee: NXP USA, INC.
    Inventor: Steven A. Atherton
  • Patent number: 9572251
    Abstract: Provided is a printed circuit board consisting of laminated substrates each with a fiberglass cloth contained in its resin and with a wiring arranged onto at least one of its surfaces, wherein, in at least one of substrates provided with a wiring for transmitting a higher speed signal than that transmitted by wirings arranged onto the other substrates, a fiberglass cloth having a different property from that of the other substrates is contained.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: February 14, 2017
    Assignee: NEC CORPORATION
    Inventors: Akihiro Ueda, Shinji Tanaka
  • Patent number: 9521743
    Abstract: A printed circuit board comprising conductive layers separated by insulation layers of dielectric material, at least one conductive layer being patterned and having at least one signal line embedded in insulation material. The at least one signal line is covered by a dielectric film, followed by a thin conductive layer, whereby the dielectric film covers at least one surface and both sides of the at least one signal line and the thin conductive layer extends, separated by the dielectric film, over the at least one surface of the signal line and at least partially over the height of both sides of the signal line.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: December 13, 2016
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Martin Fischeneder, Mikael Tuominen
  • Patent number: 9515027
    Abstract: A printed circuit board includes a printed circuit board, a semiconductor device mounted on the printed circuit board, a capacitor element mounted on the printed circuit board 2, a ground conductor plane to which a ground terminal of the semiconductor device is connected, and first and second power source conductor planes which are arranged so as not to contact with each other. The second power source conductor plane and the ground conductor plane are arranged so as to oppose to each other to form a planar capacitor. The printed circuit board has a first connecting conductor which connects a power source terminal of the semiconductor device with the second power source conductor plane, and a second connecting conductor which connects the first power source conductor plane with the second power source conductor plane through a first terminal of the capacitor element. Thereby, an electromagnetic radiation noise is reduced.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: December 6, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hiroto Tamaki
  • Patent number: 9413097
    Abstract: A cabled midplane includes a first support plate along a plane between a first connector set and a second connector set that connect to line cards on either side of the cabled midplane. The first connector set and the second connector set include connector slices. A wiring sub-layer includes cable slices to provide a connection between the first connector slice of a connector of the first connector set to the first connector slice of a connector of the second connector set, such that the first wiring sub-layer connects each connector of the first connector set, through one cable slice, to a connector of the second connector set. Additional wiring sub-layers are added, and a second support plate, parallel to the first support plate, is provided to encase and support the wiring sub-layers between the first support plate and the second support plate. Other apparatuses and methods are described.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: August 9, 2016
    Assignee: Intel Corporation
    Inventors: Vladimir Tamarkin, Wayne Genetti, Keith Mease, Mark Wessel
  • Patent number: 9414492
    Abstract: A printed wiring board including a connection part that is connected to a projecting portion of an external member by soldering, the connection part including a first hole in which the projecting portion is inserted, a main land to which the projecting portion is soldered, a metallic pattern that is drawn from the main land, and a sub-land that is connected to the main land through the metallic pattern, wherein the main land is constructed with a metallic film configured to cover a peripheral region of the first hole in at least a front face of the printed wiring board including the front face and a back face, the front face to which the soldering is performed and the back face on a side opposite to the front face, and the metallic film is not formed on a sidewall forming the first hole, and where the sub-land is constructed with a metallic film configured to cover a sidewall formed by a second hole piercing the printed wiring board and a peripheral region of the second hole in both the front face and the bac
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: August 9, 2016
    Assignee: OMRON Corporation
    Inventor: Akihiro Hozumi
  • Patent number: 9408297
    Abstract: A patterned transparent conductor includes: (1) a substrate; (2) first additives at least partially embedded into a surface of the substrate within a first area of the surface corresponding to a lower sheet resistance portion; and (3) second additives at least partially embedded into the surface of the substrate within a second area of the surface corresponding to a higher sheet resistance portion. A sheet resistance of the higher sheet resistance portion is at least 100 times a sheet resistance of the lower sheet resistance portion.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: August 2, 2016
    Assignee: TPK HOLDING CO., LTD.
    Inventors: Arjun Daniel Srinivas, Matthew R. Robinson, Alexander Chow Mittal, Michael Eugene Young, David Buchanan, Joseph George, Yuka Yoshioka
  • Patent number: 9374894
    Abstract: A micro-wire rib structure includes a substrate and a cured layer formed on or over the substrate, the cured layer having a cured-layer surface. A micro-channel is imprinted in the cured layer, the micro-channel having a micro-channel depth, a micro-channel bottom, first and second micro-channel sides, and one or more ribs having opposing rib sides and a rib top defining a rib height less than the micro-channel depth. Each rib is located between the first and second micro-channel sides and extends from the micro-channel bottom toward the cured-layer surface. A cured electrical conductor forming a micro-wire is formed in the micro-channel. The micro-wire extends continuously from the first micro-channel side, over the micro-channel bottom, the rib side(s) and rib top(s) to the second micro-channel side forming a continuous electrical conductor from the first micro-channel side to the second micro-channel side.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: June 21, 2016
    Assignee: EASTMAN KODAK COMPANY
    Inventors: Ronald Steven Cok, Mitchell Stewart Burberry