With Encapsulated Wire Patents (Class 174/251)
  • Patent number: 10996785
    Abstract: A touch display device and a touch display panel are provided. The touch display panel includes a bend area adjacent to the periphery of the touch display panel, and touch lines disposed in the bend area have zigzag shapes that extend at angles with respect to a bend axis about which the bend area is bent. A first dielectric layer includes a compensation pattern that is located in the bend area and includes an opening that extends in a direction parallel to the bend axis. A second dielectric layer protrudes into the opening of the compensation pattern in a depth direction. During bending of the bend area, this configuration disperses force applied to portions of the touch lines and the dielectric layers in the bend area. This can consequently prevent both cracking due to bending and moisture permeation due to cracks.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: May 4, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: Yangsik Lee, JiHyun Jung, DeukSu Lee, JaeGyun Lee, Ruda Rhe, Jeonghoon Lee, Su Chang An
  • Patent number: 10993329
    Abstract: A first board includes a first insulating substrate including a first main surface, a first electrode pad, and a first resist film. The first electrode pad is a conductor pattern provided on the first main surface. The first resist film is provided on the first main surface and is located closer to the first electrode pad than any conductor provided on the first main surface. The first resist film is spaced away from the first electrode pad with a gap provided between the first resist film and the first electrode pad. The first resist film is thicker than the first electrode pad.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: April 27, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kuniaki Yosui, Daisuke Tonaru, Hideyuki Taguchi, Genro Kato
  • Patent number: 10986733
    Abstract: A method for manufacturing an electromechanical structure, includes producing conductors and/or graphics on a substantially flat film, attaching electronic elements on the said film in relation to the desired three-dimensional shape of the film, forming the said film housing the electronic elements into a substantially three-dimensional shape, and using the substantially three-dimensional film as an insert in an injection molding process by molding substantially on said film, wherein a preferred layer of material is attached on the surface of the film. A corresponding arrangement for carrying out the method is also presented.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: April 20, 2021
    Assignee: TACTOTEK OY
    Inventors: Mikko Heikkinen, Jarmo Sääski, Jarkko Torvinen, Paavo Niskala, Mikko Sippari, Pasi Raappana, Antti Keränen
  • Patent number: 10986734
    Abstract: A method for manufacturing an electromechanical structure, includes producing conductors and/or graphics on a substantially flat film, attaching electronic elements on the said film in relation to the desired three-dimensional shape of the film, forming the said film housing the electronic elements into a substantially three-dimensional shape, and using the substantially three-dimensional film as an insert in an injection molding process by molding substantially on said film, wherein a preferred layer of material is attached on the surface of the film. A corresponding arrangement for carrying out the method is also presented.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: April 20, 2021
    Assignee: TACTOTEK OY
    Inventors: Mikko Heikkinen, Jarmo Sääski, Jarkko Torvinen, Paavo Niskala, Mikko Sippari, Pasi Raappana, Antti Keränen
  • Patent number: 10973420
    Abstract: The present invention relates, generally, to a component containing a composite of at least two layers that are connected to each other, in which the first layer comprises a hole and the second layer has a thickness in the range of 1 to 50 ?m. The first and second layers each contain at least one metal and compositions of the first and second layers are different. Further objects of the present invention include a method for producing a component containing at least two layers that are connected to each other and have the aforementioned features, a method for producing a component containing at least three layers that are connected to each other and have the aforementioned features, as well as a component that is obtained by one of the aforementioned methods and a device containing at least one of the aforementioned components for use in a living body.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: April 13, 2021
    Assignee: HERAEUS DEUTSCHLAND GMBH & CO. KG
    Inventors: Nicholas Baltos, Oliver Keitel, Lena Weber, Andreas Reisinger
  • Patent number: 10955442
    Abstract: Elastic sleeve (1) for electrically insulating a HV/MV power conductor in a power network, comprising a) a shrinkable or expandable elastic sleeve body (10); b) a receiving space (20) in the sleeve body, for receiving the power conductor; c) a cavity (30) formed in the sleeve body; and d) a divider assembly (40), arranged, at least partially, in the cavity and comprising a plurality of discrete impedance elements, operable as a voltage divider for sensing a voltage of an inner conductor of the power conductor.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: March 23, 2021
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Mark Gravermann, Gunther A. J. Stollwerck, Michael H. Stalder, Gerhard Lohmeier, Bernd Schubert, Rainer Reeken, Jens Weichold
  • Patent number: 10912194
    Abstract: Generally, the present disclosure provides example embodiments relating to a printed circuit board (PCB). In an embodiment, a structure includes a PCB including insulating layers with respective metal layers being disposed therebetween. Each of first layers of the insulating layers includes a first fiberglass content. A second layer of the insulating layers has a second fiberglass content less than the first fiberglass content. For example, in some embodiments, the second insulating layer does not include a fiberglass matrix.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: February 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Haw Tsao, Tsung-Hsing Lu, Li-Huan Chu
  • Patent number: 10881008
    Abstract: A multi-layered circuit board proofed against conductor loss or diminution when heated includes first and second circuit base boards. Each first circuit base board includes a first dielectric layer and a first wiring layer formed thereon and a first stepped paste block as a conductor formed in the first dielectric layer. The first stepped paste block is electrically connected to the first dielectric layer. Each second circuit base board includes a second dielectric layer and a second wiring layer, a second stepped paste block as a conductor is formed in the second dielectric layer. When pressed together for an electrical interconnection, the paste blocks are sealed and thus captive between the first and second circuit base boards.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: December 29, 2020
    Assignees: Avary Holding (Shenzhen) Co., Limited., QING DING PRECISION ELECTRONICS (HUAIAN) CO., LTD
    Inventors: Zhi Guo, Chao-Feng Huang
  • Patent number: 10873043
    Abstract: A flexible display apparatus can have a flexible substrate including: an active area including a plurality of driving TFTs and a plurality of organic emission elements, and an inactive area including a first inactive area adjacent to the active area, a second inactive area for a circuit board, and a bending area between the first inactive area and the second inactive area; a component disposed on at least a part of the first inactive area; a plurality of wiring lines extending from the plurality of driving TFTs to the first inactive area, the bending area and the second inactive area; and a support layer disposed across the active area, the first inactive area, the bending area, and the second inactive area, in which a portion the support layer includes at least one cut portion overlapping with the bending area of the flexible substrate.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: December 22, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Jaehyun Jin
  • Patent number: 10872860
    Abstract: A semiconductor package includes a connection structure including an insulating layer, a wiring layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the wiring layer. A frame is disposed on the connection structure and has one or more through-holes. A semiconductor chip and passive components are disposed in the one or more through-holes of the frame on the connection structure. A first encapsulant covers at least portions of the passive components and the frame. A frame wiring layer is disposed on the frame, and a location identifying mark is disposed around the semiconductor chip on the frame and is spaced apart from the frame wiring layer. At least a portion of the location identifying mark is not covered by the first encapsulant.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: December 22, 2020
    Assignee: SAMSUNG ELECTRONICS CO.. LTD.
    Inventor: Min Sek Jang
  • Patent number: 10868221
    Abstract: A method for manufacturing a chip-mounting substrate includes a pre-coating step of forming a precoat on a substrate including a plurality of conductive portions and an insulating portion interposed between the conductive portions, an etching step of etching at least a portion of the precoat through a laser to form a pattern, and a step of forming a metal layer on the substrate. The pattern is disposed on at least one of the conductive portions, and the metal layer is formed in the pattern.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: December 15, 2020
    Assignee: POINT ENGINEERING CO., LTD.
    Inventors: Bum Mo Ahn, Seung Ho Park, Tae Hwan Song
  • Patent number: 10788531
    Abstract: An improved package device simulator for the testing of testing sockets, the package device simulator being formed of a first layer of non-conductive rigid substrate with a second layer formed of a plurality of electrically conductive traces being added thereto. A third layer of non-conductive rigid substrate is adhered to the first layer with the second layer being sealed there between. The third layer having a plurality of openings therein, wherein the openings align with and expose a portion of the electrically conductive traces of the second layer. Conductive binding material and contact balls are added to the openings and the chip is cured thereby fusing the contact balls with the exposed portions of the traces. Next, the exposed surfaces are coated with a hardening conductive material, such as layers of Nickel and/or Gold. In this way an improved package device simulator is formed that is durable, easier to manufacture and less expensive than a solid metallic package device simulator.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: September 29, 2020
    Assignee: MODUS TEST, LLC
    Inventors: Lynwood Adams, Bruce Rogers, Jack Lewis, Tim Conner, Jay Williams, Mike Young, Dawn Ritz
  • Patent number: 10743405
    Abstract: The present disclosure provides a printed circuit board including a plurality of conductive layers separated by insulating medium and a plurality of connection structures. Each connection structure penetrates each of the conductive layers. The plurality of conductive layers comprises a first conductive layer in which first signal lines are located and a second conductive layer in which second signal lines are located, and the first and second signal lines are connected via the connection structures. Anti-pads surrounding the connection structures are provided on others of the plurality of conductive layers except the first and the second conductive layers. For a same connection structure, the anti-pads surrounding the connection structure include adjacent anti-pads and nonadjacent anti-pads. Size of the adjacent anti-pads in any direction parallel to the conductive layers is smaller than that of the nonadjacent anti-pads. The present disclosure also provides a display apparatus.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: August 11, 2020
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Enming Xie, Xiaolong Wei, Chun Cao, Wenchao Bao
  • Patent number: 10741482
    Abstract: A semiconductor device package includes a carrier, a first conductive post and a first adhesive layer. The first conductive post is disposed on the carrier. The first conductive post includes a lower surface facing the carrier, an upper surface opposite to the lower surface and a lateral surface extended between the upper surface and the lower surface. The first adhesive layer surrounds a portion of the lateral surface of the first conductive post. The first adhesive layer comprises conductive particles and an adhesive. The first conductive post has a height measured from the upper surface to the lower surface and a width. The height is greater than the width.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 11, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Yu-Ying Lee
  • Patent number: 10717806
    Abstract: A packaging material is provided. The packaging material includes (a) epoxy silsesquioxane, (b) epoxy resin, and (c) siloxane-imide-containing benzoxazine compound. (a) Epoxy silsesquioxane and (b) epoxy resin have a weight ratio of 0.3:1 to 10:1. The total weight of (a) epoxy silsesquioxane and (b) epoxy resin and the weight of (c) siloxane-imide-containing benzoxazine compound have a ratio of 100:20 to 100:150.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: July 21, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Wen-Bin Chen, Kai-Chi Chen, Shu-Chen Huang
  • Patent number: 10720724
    Abstract: Embodiments related to electrical connectors including superelastic components are described. The high elastic limit of superelastic materials compared to conventional connector materials may allow for designs which provide reliable connections and high frequency operation. Superelastic components also may enable connector designs with higher densities of connections. In some embodiments, a connector includes one or more superelastic elongated members forming the mating contacts of the connector. The superelastic elongated members deform within one or more conductive receptacles to generate a suitable contact force. The conductive receptacles may include a plurality of protrusions arranged to deflect the superelastic elongated members during mating. A superelastic component may also be provided in a receiving portion of a connector, and may form a portion of a conductive receptacle.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: July 21, 2020
    Assignee: Amphenol Corporation
    Inventors: Tom Pitten, Mark W. Gailus, Marc B. Cartier, Jr., David Levine, Donald A. Girard, Jr.
  • Patent number: 10679931
    Abstract: Ball grid assembly (BGA) bumping solder is formed on the back side of a laminate panel within a patterned temporary resist. Processes such as singulation and flip chip module assembly are conducted following BGA bumping with the temporary resist in place. The resist is removed from the back side of the singulated laminate panel prior to card assembly. Stand-off elements having relatively high melting points can be incorporated on the BGA side of the laminate panel to ensure a minimum assembly solder collapse height. Alignment assemblies are formed on the socket-facing side of an LGA module using elements having relatively high melting points and injected solder.
    Type: Grant
    Filed: March 31, 2019
    Date of Patent: June 9, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jae-Woong Nah, Charles L. Reynolds, Katsuyuki Sakuma
  • Patent number: 10672755
    Abstract: An example substrate includes a surface, a plurality of thin film layers disposed on the surface, and a conductive layer disposed on the surface. The conductive layer includes a bending structure. The bending structure includes a wavy edge and includes a plurality of openings, where a shape of at least one opening of the plurality of openings has a contour having a first curved portion, and a curvature of a portion of the wavy edge is different from a curvature of the first curved portion.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: June 2, 2020
    Assignee: InnoLux Corporation
    Inventor: Yuan-Lin Wu
  • Patent number: 10671196
    Abstract: A touch substrate, a method for forming the same and a touch display device are provided. The touch substrate includes: a primary touch region, a secondary touch region, a peripheral region, primary touch electrodes at the primary touch region, secondary touch electrodes at the secondary touch region, a plurality of bonding terminals, a plurality of primary touch signal channels and a plurality of secondary touch signal channels configured to transmit touch signals to the secondary touch electrodes at the peripheral region, where each bonding terminal is coupled to a corresponding primary touch electrode via a signal transmission line, and configured to provide the primary touch signal channel to transmit the touch signal to the corresponding primary touch electrode, where at least a part of the primary touch signal channels is reused as the secondary touch signal channels.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: June 2, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiaojuan Hu, Jing Wang, Guiyu Zhang, Qitao Zheng, Min He, Xiaodong Xie, Jian Tian, Zouming Xu, Lei Zhang
  • Patent number: 10667394
    Abstract: A method for manufacturing a double-sided, single conductor laminate includes providing a laminated substrate that includes a conductive layer, an adhesive layer and a support layer; dry milling a trace pattern in the laminated substrate by removing selected areas of the conductive layer and the adhesive layer; and attaching a first cover layer using a first adhesive layer to the conductive layer. The first cover layer includes one or more precut access holes that align with one or more traces of the trace pattern.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: May 26, 2020
    Assignee: Gentherm Inc.
    Inventor: Michael Peter Ciaccio
  • Patent number: 10667393
    Abstract: A circuit board assembly of an information handling system has stepped diameter vias that carry communication signals through printed circuit board (PCB) substrates. Each stepped diameter via has a first barrel portion of a first diameter that is drilled through a first portion of the PCB substrates and that is at least lined with a conductive material to electrically conduct a selected one of: (i) a direct current and (ii) a communication signal from an outer layer to an internal layer of the more than one PCB substrate. Each stepped diameter via further includes a second barrel portion that extends from the first barrel portion deeper into the PCB substrates. The second barrel portion has a second diameter that is less than the first diameter and the smaller second diameter improves signal integrity (SI).
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: May 26, 2020
    Assignee: Dell Products, L.P.
    Inventors: Umesh Chandra, Bhyrav M. Mutnury, Mallikarjun Vasa
  • Patent number: 10638606
    Abstract: A composite circuit board includes an insulation layer, an inner circuit layer, a first conductive layer and a second conductive layer embedded in the insulation layer, a third conductive layer and a fourth conductive layer formed on opposite surfaces of the insulation layer. The third conductive layer electrically connects with the first conductive layer. The fourth conductive layer electrically connects with the second conductive layer. The inner circuit layer is in a middle portion of the insulation layer. The first conductive layer and the second conductive layer respectively forms on opposite sides of the inner circuit layer. The insulation layer forms a plurality of first through holes between the first conductive layer and the inner circuit layer, a plurality of second through holes between the second conductive layer and the inner circuit layer.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: April 28, 2020
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventors: Xian-Qin Hu, Mei Yang, Cheng-Jia Li
  • Patent number: 10617002
    Abstract: A circuit board is obtained by providing a wiring pattern on an insulating board. The circuit board includes a first region and a second region. In the first region, a first wiring pattern is provided on which a first surface treatment is applied. In the second region, a second wiring pattern is provided on which a second surface treatment having a cutting fluid resistance and/or a humidity resistance lower than the first surface treatment is applied.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: April 7, 2020
    Assignee: FANUC CORPORATION
    Inventor: Norihiro Saido
  • Patent number: 10609769
    Abstract: One example includes a system that is comprised of a transparent protective panel, a transparent electrically conductive thin film, a transparent pane, and an adhesive. The transparent electrically conductive thin film is fixed to the transparent protective panel, the transparent protective panel and the transparent electrically conductive film together forming a composite transparent panel. The adhesive adhesively couples the composite transparent panel to the transparent pane, the adhesive failing adhesively at an interface between the adhesive and the transparent pane.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: March 31, 2020
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventor: Charles R. Smith
  • Patent number: 10589494
    Abstract: Provided are a far infrared reflective film including a support, and a fibrous silver particles-containing layer provided on the support, in which the fibrous silver particles-containing layer includes fibrous silver particles, and a sol-gel hardened material obtained by hydrolysis and polycondensation of a metal coupling agent including a functional group capable of interacting with the fibrous silver particles, and an alkoxide compound, which has excellent heat insulating properties, film hardness, and surface properties; a dispersion for forming a far infrared reflective film; a manufacturing method of a far infrared reflective film; a far infrared reflective glass; and a window.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: March 17, 2020
    Assignee: FUJIFILM Corporation
    Inventor: Yuki Nakagawa
  • Patent number: 10580971
    Abstract: A method includes depositing a magnetic track layer on a seed layer, depositing an alloy layer on the magnetic track layer, depositing a tunnel barrier layer on the alloy layer, depositing a pinning layer on the tunnel barrier layer, depositing a synthetic antiferromagnetic layer spacer on the pinning layer, depositing a pinned layer on the synthetic antiferromagnetic spacer layer and depositing an antiferromagnetic layer on the pinned layer, and another method includes depositing an antiferromagnetic layer on a seed layer, depositing a pinned layer on the antiferromagnetic layer, depositing a synthetic antiferromagnetic layer spacer on the pinned layer, depositing a pinning layer on the synthetic antiferromagnetic layer spacer, depositing a tunnel barrier layer on the pinning layer, depositing an alloy layer on the tunnel barrier layer and depositing a magnetic track layer on alloy layer.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: March 3, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, INDUSTRIAL TECHNOLOGY RESEARCH
    Inventors: Guohan Hu, Cheng-Wei Chien
  • Patent number: 10580569
    Abstract: An electronic component 100 includes: a circuit board module 104 which is composed of a plurality of layers, and in which a primary circuit 120 and secondary circuits 122, 124 are each formed using wring patterns of a first layer L1 to an eighth layer L8; and a magnetic core 106 which magnetically couples the primary circuit 120 and the secondary circuits 122, 124. The circuit board module 104 includes: cutout portions 104b which are formed in a cutout shape from side edge portions toward an inner side and which position the magnetic core 106 at a predetermined attachment position in a state of housing the magnetic core 106; and widened portions 104c which continue from the cutout portions 104b and are formed in a cutout shape from the side edge portions toward the inner side of the circuit board module 104, and which are formed on sides of the magnetic core 106 so as to be larger than a width W1 for housing of the cutout portions 104b.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: March 3, 2020
    Assignee: TAMURA CORPORATION
    Inventors: Hiroo Ogawa, Tomohiko Yoshino
  • Patent number: 10512155
    Abstract: A wiring board that includes a first dielectric layer having a rectangular plate form, a ground conductor wiring, a pair of signal conductor wirings, a ground conductor layer, and a second dielectric layer having a rectangular plate form. The ground conductor wiring is positioned on a first face of the first dielectric layer. The pair of signal conductor wirings carrying out signal transmission is positioned on the first face of the first dielectric layer. The ground conductor layer is positioned on a second face of the first dielectric layer. A first end portion of the signal conductor wiring extends to a first side of the first face. The region of the ground conductor layer where the first end portion of the signal conductor wiring is positioned in plan view is cut away inwardly from a first side of the second face opposing the first side of the first face.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: December 17, 2019
    Assignee: KYOCERA Corporation
    Inventor: Toshihiko Kitamura
  • Patent number: 10488993
    Abstract: Metal cases are increasingly in popularity in electronics such as smart phones, tablets, portable speakers, etc., since the look and feel of a metal case are appealing to the consumer. Unfortunately, the metal case is generally incompatible traditional capacitive sensing electrodes, which are usually provided on a printed circuit board or flex circuit and are only usable with plastic cases. To provide capacitive sensing with a metal case, a specialized material stack can be fabricated to embed capacitive sensors with the metal case. Specifically, a conductor (a conductive pad, or conductive layer) can be deposited over an oxide layer formed on the metal case (e.g., through anodization). An outer coating can be provided to protect the conductor. A further conductor and dielectric can be included in the material stack to form a double layer capacitive sensor.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: November 26, 2019
    Assignee: ANALOG DEVICES, INC.
    Inventor: Isaac Chase Novet
  • Patent number: 10432032
    Abstract: An electrically conductive material configured having at least one opening of various unlimited geometries extending through its thickness is provided. The opening is designed to modify eddy currents that form within the surface of the material from interaction with magnetic fields that allow for wireless energy transfer therethrough. The opening may be configured as a cut-out, a slit or combination thereof that extends through the thickness of the electrically conductive material. The electrically conductive material is configured with the cut-out and/or slit pattern positioned adjacent to an antenna configured to receive or transmit electrical energy wirelessly through near-field magnetic coupling (NFMC). A magnetic field shielding material, such as a ferrite, may also be positioned adjacent to the antenna. Such magnetic shielding materials may be used to strategically block eddy currents from electrical components and circuitry located within a device.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: October 1, 2019
    Assignee: NuCurrent, Inc.
    Inventors: Alberto Peralta, Md. Nazmul Alam, Vinit Singh, Sina Haji Alizad
  • Patent number: 10426042
    Abstract: An approach for through-hole component soldering for a PCB, and a resulting PCB assembly, that eliminates protruding solder joints, is provided. The approach comprises back-drilling, from a bottom surface of a PCB, one or more through-holes, wherein each back-drilled through-hole is back-drilled to a depth partially through the PCB and at a diameter that is larger than the diameter of the through hole. Solder paste is applied to the PCB. The components are placed on the PCB, inserting each pin into a corresponding through-hole. The PCB is passed through a solder process, whereby, within each through-hole having a component pin inserted therein, the solder paste is wicked into the through-hole, and forms a solder joint with the respective pin. Each solder joint of a back-drilled through-hole is situated within the through-hole in a manner whereby the solder joint does not protrude beyond the bottom surface of the PCB.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: September 24, 2019
    Assignee: DISH Technologies L.L.C.
    Inventors: Andros X Thomson, Jr., Yt Ho
  • Patent number: 10392076
    Abstract: Propulsion unit for an electric pedal assisted cycle (EPAC) comprising an electric machine having a stator and a rotor, rotatable about a motor axis, said rotor (16) being operatively connected to a crank pin, defining a crank axis, mechanically connected to the pedals, wherein the propulsion unit comprises at least an electronic unit for operating and controlling the functioning of the electric machine, wherein the propulsion unit comprises at least a pair of housings defining a containment space which houses the electric machine and at least partially the crank pin, wherein the propulsion unit comprises transmission means of the motion from the rotor to the crank pin, wherein the electronic unit is contained and supported inside said containment space by an intermediate support element.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: August 27, 2019
    Assignee: PIAGGIO & C. S.p.A
    Inventors: Paolo Capozzella, Luca Carmignani, Luca Nuti, Giorgio Prosperini
  • Patent number: 10361224
    Abstract: A display device comprises: a display panel; a metallic wiring formed in the display panel; and a semiconductor integrated circuit element connected to the display panel through a UV curing anisotropy conductive film, wherein the semiconductor integrated circuit element includes a plurality of bumps, the metallic wiring is electrically connected to the bumps through the UV curing anisotropy conductive film, the metallic wiring includes a plurality of openings, and at least one of the bumps is disposed between two adjacent openings closest to each other in the plurality of openings.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: July 23, 2019
    Assignee: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
    Inventor: Yuuichi Takenaka
  • Patent number: 10362675
    Abstract: Disclosed is a flexible circuit board having a three-layer dielectric body and four-layer ground layer structure. A flexible circuit board having a three-layer dielectric body and four-layer ground layer structure, according to the present invention, comprises: a first dielectric body; a second dielectric body facing the flat surface of the first dielectric body; a third dielectric body facing the bottom side of the first dielectric body; a signal line formed on the flat surface of the first dielectric body; a pair of first ground layers laminated on the flat surface of the first dielectric body and having the signal line therebetween; second ground layers laminated on the bottom side of the first dielectric body so as to correspond to the first ground layers; a third ground layer laminated on the flat surface of the second dielectric body; and a fourth ground layer laminated on the bottom side of the third dielectric body.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: July 23, 2019
    Assignee: GIGALANE CO., LTD.
    Inventors: Sang Pil Kim, Da Yeon Lee, Hwang Sub Koo, Hyun Je Kim, Hee Seok Jung
  • Patent number: 10314179
    Abstract: A manufacturing method of a circuit board structure is described as follows. An inner circuit structure including a core layer having an upper and an opposite lower surface, a first patterned circuit layer disposed on the upper surface and a second patterned circuit layer disposed on the lower surface is provided. An insulating material layer is formed on a portion of the first patterned circuit layer. A laser resisting layer is formed on at least a portion of the insulating material layer. A release layer is adhered to the laser resisting layer. A build-up process is performed so as to laminate a first and a second build-up circuit structures on the first and the second patterned circuit layers, respectively. A laser ablation process is performed on the first build-up circuit structure so as to form a cavity at least exposing a portion of the upper surface of the core layer.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: June 4, 2019
    Assignee: Unimicron Technology Corp.
    Inventors: Hung-Lin Chang, Ming-Hao Wu, Syun-Siao Chang, Cheng-Po Yu, Chi-Min Chang
  • Patent number: 10305066
    Abstract: There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size and/or utilize the side surface of an assembled flexible display.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: May 28, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Haejoon Son, JoungHo Ryu, SieHyug Choi
  • Patent number: 10290589
    Abstract: A foldable microelectronic assembly and a method for forming the same are provided. One or more packages comprising encapsulated microelectronic elements are formed, along with a compliant layer. The packages and the compliant layer are coupled to a redistribution layer. The compliant layer and the redistribution layer are bent such that the redistribution layer is non-planar.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: May 14, 2019
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed
  • Patent number: 10283446
    Abstract: A wiring board includes a base board and a plurality of wiring layers formed of a resin insulating film on the base board, wherein at least one of the wiring layers includes a fine wiring, a barrier film, which is not in contact with the fine wiring, is formed at a more outer side from the base board than the wiring layer including the fine wiring, and different types of resin insulating films are used for a wiring layer at an inner side of the barrier film close to the base board and a wiring layer at an outer side of the barrier film, respectively.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: May 7, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Junya Ikeda, Tsuyoshi Kanki
  • Patent number: 10252452
    Abstract: A method for sealing a fastener employs a mold which provided with an inlet port for molding material. The mold is then positioned over a fastener and the mold is sealed against a structure. A moisture cured polyurethane reactive adhesive (MCRPA) as a molding material is then heated and injected into the mold. Upon solidification of the MCRPA, the mold is then removed to expose the MCRPA to atmospheric moisture and cured to leave an in-situ molded cap formed over the fastener and sealed to the structure.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: April 9, 2019
    Assignee: The Boeing Company
    Inventor: Weidong Song
  • Patent number: 10251263
    Abstract: A method of producing a wired circuit board including an insulating layer and a conductive pattern, including: (1), an insulating layer having an inclination face, (2), a metal thin film provided at least on the inclination face, (3), a photoresist provided on the surface of the metal thin film, (4), a light shield portion of a photomask disposed so that a first portion, where the conductive pattern is to be provided in the photoresist, is shielded from light, and the photoresist is exposed to light through the photomask, (5), the first portion of the photoresist is removed to expose the metal thin film corresponding to the first portion, and (6), the conductive pattern is provided on the surface of the metal thin film exposed from the photoresist.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: April 2, 2019
    Assignee: NITTO DENKO CORPORATION
    Inventors: Yuu Sugimoto, Yoshito Fujimura, Hiroyuki Tanabe
  • Patent number: 10251270
    Abstract: A printed circuit board having multiple layers of circuitry, the printed circuit board including a first layer having a first cylindrical opening with a first diameter, the first cylindrical opening formed through at least the first layer and formed about a particular axis; and a second layer having a second cylindrical opening with a second diameter, the second cylindrical opening formed through at least the second layer and formed about the particular axis, where the first cylindrical opening is a portion of a conductive via, and where the second diameter is smaller than the first diameter.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: April 2, 2019
    Assignee: Innovium, Inc.
    Inventor: Yongming Xiong
  • Patent number: 10249559
    Abstract: Ball grid assembly (BGA) bumping solder is formed on the back side of a laminate panel within a patterned temporary resist. Processes such as singulation and flip chip module assembly are conducted following BGA bumping with the temporary resist in place. The resist is removed from the back side of the singulated laminate panel prior to card assembly. Stand-off elements having relatively high melting points can be incorporated on the BGA side of the laminate panel to ensure a minimum assembly solder collapse height. Alignment assemblies are formed on the socket-facing side of an LGA module using elements having relatively high melting points and injected solder.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jae-Woong Nah, Charles L. Reynolds, Katsuyuki Sakuma
  • Patent number: 10199329
    Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a pattern layer disposed on the encapsulant and covering at least portions of the encapsulant adjacent to the inactive surface of the semiconductor chip; vias penetrating through the encapsulant and connecting the pattern layer and the inactive surface of the semiconductor chip to each other; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: February 5, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Moon Hee Yi, Joo Hwan Jung, Yul Kyo Chung
  • Patent number: 10201082
    Abstract: The invention relates to a transparent conductive layer comprising non-conductive areas and conductive areas, wherein the conductive areas comprise an interconnected network of electrically conductive nanoobjects and in the non-conductive areas the nanoobjects are converted into particles and wherein the thickness of the conductive areas and the non-conductive areas differs less than 10 nm. The invention further relates to a process for producing a patterned transparent conductive film, the film comprising a substrate and a transparent conductive layer, and to a process for producing the patterned transparent conductive film.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: February 5, 2019
    Assignee: BASF SE
    Inventors: Rui Zhang, Garo Khanarian, Herve Dietsch, Andreas Kuehner
  • Patent number: 10187972
    Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and columns of via patterns formed in the plurality of layers, wherein via patterns in adjacent columns are offset in a direction of the columns, each of the via patterns comprising: first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; and at least one conductive shadow via located between the first and second signal vias of the differential pair. In some embodiments, at least one conductive shadow via is electrically connected to a conductive surface film.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: January 22, 2019
    Assignee: Amphenol Corporation
    Inventors: Marc Robert Charbonneau, Jose Ricardo Paniagua
  • Patent number: 10181663
    Abstract: A connector system is provided that includes a first connector and a second connector that are both coupled by a plurality of cables. The first connector is a stacked connector and includes a first terminal pair and a second terminal pair that are positioned in spaced apart card slots. The second connector includes a third and a fourth terminal pairs and the first and second terminal pairs are fixably connected to the third and fourth terminal pairs by the plurality of cables.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: January 15, 2019
    Assignee: Molex, LLC
    Inventor: Kent E. Regnier
  • Patent number: 10178776
    Abstract: A method for wiring differential signal lines and a PCB are disclosed. The wiring method includes: providing a rectangle-shaped glass fiber fabric formed of glass fibers which are woven and interlaced with each other and an adhesive filled therebetween; determining a wiring direction and obtaining a glass fiber bundle number of the glass fiber fabric in the wiring direction; equally dividing the glass fiber fabric into glass fiber units, and obtaining a width of each glass fiber unit according to a size of the glass fiber fabric in a direction perpendicular to the wiring direction and the number of the glass fiber units; determining a line distance and line widths of the differential signal lines; and according to the line distance and the line widths, forming the differential signal lines on a metal layer along the wiring direction to make the differential signal lines meet predetermined requirements.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: January 8, 2019
    Assignee: ZTE CORPORATION
    Inventors: Tao Guo, Fengchao Ma, Yuanwang Zhang
  • Patent number: 10133414
    Abstract: The invention provides a layered body for a touch panel in which metal migration is suppressed and changes in the electrical resistance of a fine metal wire are suppressed, and a touch panel. The layered body for a touch panel of the invention is a layered body for a touch panel including a substrate, fine metal wires which are disposed on the substrate, and an adhesive layer which is disposed on the fine metal wires, in which the amount of the metal contained per unit area in the fine metal wire is in a range of 0.01 g/m2 to 10 g/m2, the adhesive layer contains a benzotriazole-based compound, and the content of the benzotriazole-based compound is in a range of 0.05 mass % to 1.5 mass % with respect to the total mass of the adhesive layer.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: November 20, 2018
    Assignee: FUJIFILM Corporation
    Inventors: Kenji Naoi, Toshiaki Hayashi
  • Patent number: 10128903
    Abstract: A method includes providing a first circuit trace and a second circuit trace on a printed circuit board, determining a far end cross-talk (FEXT) response associated with the first circuit trace, determining a time delay associated with the second circuit trace, estimating a floquet response associated with the time delay, comparing the FEXT response with an interface frequency associated with the first circuit trace, comparing the floquet response with the interface frequency, and determining whether the floquet response cancels the FEXT response on the first circuit trace at the interface frequency.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: November 13, 2018
    Assignee: DELL PRODUCTS, LP
    Inventors: Arun R. Chada, Bhyrav M. Mutnury
  • Patent number: 10123414
    Abstract: A process of manufacturing a multilayer circuit board includes patterning insulating substrates on which conductors are formed to provide a signal conductor, a first ground conductor, and a second ground conductor. The insulating substrates including the signal conductor, the first ground conductor, and the second ground conductor are stacked and thermally crimped to form a laminate. An interlayer connection conductor is formed on a surface of the laminate by a Laser Direct Structuring process.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: November 6, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kuniaki Yosui, Bunta Okamoto, Isamu Morita, Jun Sasaki