With Encapsulated Wire Patents (Class 174/251)
  • Patent number: 11977710
    Abstract: A position detection sensor includes a base made of a flexible material. The base includes a terminal section having a plurality of terminal conductors disposed on a first surface of the base. The base includes a sensor pattern section including a plurality of electrode conductors arranged in predetermined patterns in an area that does not overlap with the terminal section on the first surface of the base. End portions of the plurality of electrode conductors are positioned so as to be connectable to corresponding ones of the terminal conductors in the terminal section. The first surface of the base includes a region of the terminal section, a region of the sensor pattern section, and a bendable region between these two regions. Each of the plurality of electrode conductors, which is electrically connected to each of the plurality of terminal conductors, is disposed so as to be extensible in the bendable region.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: May 7, 2024
    Assignee: Wacom Co., Ltd.
    Inventor: Yoshiharu Matsumoto
  • Patent number: 11804327
    Abstract: A coil component includes: a body including a magnetic material and a coil of which both ends are externally exposed; intermetallic compounds disposed on the exposed both ends of the coil; and external electrodes disposed on the body to cover the intermetallic compounds. The external electrodes include: conductive resin layers disposed on outer surfaces of the body to contact the exposed both ends of the coil and including base resins, a plurality of metal particles disposed in the base resins, and conductive connecting parts surrounding the plurality of metal particles and contacting the intermetallic compounds. The coil component further includes electrode layers disposed on the conductive resin layers and contacting the conductive connecting parts.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: October 31, 2023
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yoon Hee Lee, Bon Seok Koo, Yeon Tae Kim, Chang Hak Choi, Jung Min Kim
  • Patent number: 11775099
    Abstract: A touch sensing module includes a sensing coil, a metal portion disposed to be spaced apart from the sensing coil, and a first bracket having one surface, on which the metal portion is disposed, and an other surface, opposing the one surface, on which a pad having a capacitance, configured to vary as a touch is applied, is disposed.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: October 3, 2023
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hee Sun Oh, Gye Won Lee, Hong Seok Lee, Chang Ju Lee, Jong Yun Kim
  • Patent number: 11758643
    Abstract: A printed circuit board includes a front layer including frame ground regions on which connectors to be connected with external apparatuses or communication cables are mounted and which are connected with a ground, a signal ground region which is separated from the frame ground regions at the front layer, on which electronic devices configured to receive signals from the connectors are mounted, and which is connected with a ground, and a static electricity removal ground region separated from the frame ground regions and the signal ground region at the front layer, situated outside the frame ground regions, and connected with a ground.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: September 12, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yo Kobayashi, Koji Hirai
  • Patent number: 11756872
    Abstract: A package structure includes a carrier substrate, a die, and a first redistribution structure. The carrier substrate has a first surface and a second surface opposite to the first surface. The carrier substrate includes an insulating body and through carrier vias (TCV) embedded in the insulating body. The die is disposed over the firs surface of the carrier substrate. The die is electrically connected to the TCVs. The first redistribution structure is disposed on the second surface of the carrier substrate.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Yueh Wu, Chien-Ling Hwang, Jen-Chun Liao, Ching-Hua Hsieh, Pei-Hsuan Lee, Chia-Hung Liu
  • Patent number: 11756945
    Abstract: A method includes forming a redistribution structure on a carrier substrate, coupling a first side of a first interconnect structure to a first side of the redistribution structure using first conductive connectors, where the first interconnect structure includes a core substrate, where the first interconnect structure includes second conductive connectors on a second side of the first interconnect structure opposite the first side of the first interconnect structure, coupling a first semiconductor device to the second side of the first interconnect structure using the second conductive connectors, removing the carrier substrate, and coupling a second semiconductor device to a second side of the redistribution structure using third conductive connectors, where the second side of the redistribution structure is opposite the first side of the redistribution structure.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun Yi Wu, Chen-Hua Yu
  • Patent number: 11700688
    Abstract: The present disclosure provides a display substrate, a method for manufacturing the display substrate, and a display device. The display substrate includes a first conductive line extending in a first direction on a base substrate, a second conductive line extending in a second direction crossing the first direction on the base substrate, and an insulation layer arranged between the first conductive line and the second conductive line. The display substrate further includes a buffer layer arranged between the first conductive line and the base substrate, a groove extending in the first direction is formed in the buffer layer, the first conductive line is arranged in the groove, and a surface of the first conductive line away from the base substrate is flush with a surface of the buffer layer away from the base substrate.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: July 11, 2023
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yongchao Huang, Qinghe Wang, Haitao Wang, Jun Liu, Jun Cheng, Ce Zhao, Liangchen Yan
  • Patent number: 11676904
    Abstract: A semiconductor package includes a first sub-semiconductor device, an interposer, and a second sub-semiconductor device stacked on each other, and a heat sink covering the second sub-semiconductor device. The first sub-semiconductor device includes a first substrate and a first semiconductor chip. The interposer includes a dielectric layer, a thermal conductive layer in contact with a bottom surface of the dielectric layer, a first thermal conductive pad in contact with a top surface of the dielectric layer, and thermal conductive vias penetrating the dielectric layer to connect the thermal conductive layer to the first thermal conductive pad. A bottom surface of the thermal conductive layer is adjacent to and connected to a top surface of the first semiconductor chip. The second sub-semiconductor device is disposed on the dielectric layer without overlapping the first thermal conductive pad. The heat sink further covers the first thermal conductive pad to be connected thereto.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: June 13, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jiwon Shin, Donguk Kwon, Kwang Bok Woo, Minseung Ji
  • Patent number: 11664240
    Abstract: The method for producing a laminate having a patterned metal foil includes masking the whole surface of a first metal foil in a laminate having the first metal foil, a first insulating resin layer having a thickness of 1 to 200 ?m and a second metal foil laminated in this order, and patterning the second metal foil.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: May 30, 2023
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Syunsuke Hirano, Yoshihiro Kato, Takaaki Ogashiwa, Kazuaki Kawashita, Makoto Murakami
  • Patent number: 11665820
    Abstract: Disclosure provides an adapter board and a method for making the adapter board, which includes providing a mold in which a plurality of first fixing plates and second fixing plates are provided, providing a plurality of wires sequentially passed through the plurality of first fixing plates and the second fixing plate, injecting a non-conductive material into the cavity to form a body, and cutting the body along both sides of the first fixing plates and the second fixing plates to obtain a plurality of board bodies. The first fixing plates are provided with a plurality of first fixing holes, and the second fixing plates are provided with a plurality of second fixing holes. The board body includes a first surface and a second surface. A plurality of first connection pads are formed on the first surface, and a plurality of second connection pads are formed on the second surface.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: May 30, 2023
    Assignees: QING DING PRECISION ELECTRONICS (HUAIAN) CO., LTD, Avary Holding (Shenzhen) Co., Limited.
    Inventors: Man-Zhi Peng, Rui-Wu Liu, Ming-Jaan Ho
  • Patent number: 11646157
    Abstract: A component built-in substrate includes a multilayer body and a substrate including a multilayer ceramic electronic component embedded therein. The multilayer ceramic electronic component includes a first connection portion that protrudes from the first external electrode, and a second connection portion that protrudes from the second external electrode. The substrate includes a core material. The multilayer ceramic electronic component including the first connection portion and the second connection portion includes a surface covered by the core material and embedded in the substrate. The first connection portion protrudes toward a surface of the substrate, and is not exposed at the surface of the substrate. The second connection portion protrudes toward the surface of the substrate, and is not exposed at the surface of the substrate.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: May 9, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yuichiro Tanaka, Hiroki Awata
  • Patent number: 11627658
    Abstract: A printed wiring board includes a first insulating layer, a conductor layer on the first insulating layer, and a second insulating layer formed on the first insulating layer and covering the conductor layer. The conductor layer includes first, second and third circuits, the first circuit has first width of 15 ?m or less, the first and second circuits have second space between the first and second circuits such that the second space has second width of 14 ?m or less, the first and third circuits have third space between the first and third circuits such that the third space has third width of 20 ?m or more, and the first circuit has first lower and upper surfaces, and second and third side walls such that second angle between the second wall and the first lower surface is larger than third angle between the third wall and the first lower surface.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: April 11, 2023
    Assignee: IBIDEN CO., LTD.
    Inventor: Kyohei Yoshikawa
  • Patent number: 11616026
    Abstract: A device includes an interconnect device attached to a redistribution structure, wherein the interconnect device includes conductive routing connected to conductive connectors disposed on a first side of the interconnect device, a molding material at least laterally surrounding the interconnect device, a metallization pattern over the molding material and the first side of the interconnect device, wherein the metallization pattern is electrically connected to the conductive connectors, first external connectors connected to the metallization pattern, and semiconductor devices connected to the first external connectors.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: March 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jiun Yi Wu, Chen-Hua Yu
  • Patent number: 11581500
    Abstract: A mobile terminal according to an embodiment includes a display panel having flexibility, and a support plate configured to support the display panel and to include a curved edge, at least a part of which is surrounded by the display panel. The display panel includes a base substrate, a light-emitting layer provided on the base substrate and configured to include a light-emitting element, a thin-film encapsulation layer configured to seal the light-emitting element, and a thin-film transistor (TFT) film configured to supply a signal to the light-emitting element, a polarizing film provided on the light-emitting layer, and a protective film provided on the polarizing film. The TFT film is extended from the base substrate at the curved edge to cover an edge of the base substrate.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: February 14, 2023
    Assignee: LG ELECTRONICS INC.
    Inventors: Insu Song, Kyungsoo Son, Jihoon Lee, Kiseong Mun, Jaewook Lee
  • Patent number: 11541640
    Abstract: A circuit-including film comprising: a resin film (1); and a conductive fine wire circuit (A) and a conductive circuit (B) independent of the conductive fine wire circuit (A), which are arranged on one surface of the resin film (1), wherein the resin film (1) contains at least one resin selected from the group consisting of a polyvinyl acetal resin, an ionomer resin and an ethylene-(vinyl acetate) copolymer resin.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: January 3, 2023
    Assignee: Kuraray Europe GmbH
    Inventors: Yuhi Shimazumi, Koichiro Isoue, Jun Koishikawa
  • Patent number: 11538798
    Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip mounted on the first redistribution substrate, a first molding layer on the first redistribution substrate and covering a top surface and lateral surfaces of the first semiconductor chip, a second redistribution substrate on the first molding layer, and an adhesive film between the second redistribution substrate and the first molding layer. The adhesive film is spaced apart from the first semiconductor chip and covers a top surface of the first molding layer. A lateral surface of the adhesive film is coplanar with a lateral surface of the second redistribution substrate.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: December 27, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeonjeong Hwang, Kyoung Lim Suk, Seokhyun Lee, Jaegwon Jang
  • Patent number: 11530308
    Abstract: A method of manufacturing a modified liquid crystal polymer includes: providing a liquid crystal polymer having a first melting point; heating the liquid crystal polymer to a first temperature and maintaining at the first temperature for a first time period, in which the first temperature is lower than or equal to the first melting point; and cooling the liquid crystal polymer to a second temperature to form a first modified liquid crystal polymer, the second temperature being lower than the first temperature, the first modified liquid crystal polymer having a second melting point, in which the second melting point is higher than the first melting point.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: December 20, 2022
    Assignee: AZOTEK CO., LTD.
    Inventor: Hung-Jung Lee
  • Patent number: 11516910
    Abstract: A circuit board structure includes a redistribution structure layer, a build-up circuit structure layer, and a connection structure layer. The redistribution structure layer has a first and second surface, and includes an inner and outer dielectric layer, first connecting pads, and chip pads. A bottom surface of each first connecting pad is aligned with the first surface, and the chip pads are protruded from and located on the second surface. The build-up circuit structure layer includes second connecting pads. The connection structure layer is disposed between the redistribution structure layer and the build-up circuit structure layer and includes a substrate and conductive paste pillars penetrating the substrate. The first connecting pads are electrically connected to the second connecting pads via the conductive paste pillars, respectively. A top surface of each conductive paste pillar is aligned with the first surface of the redistribution structure layer.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: November 29, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Chia-Yu Peng, John Hon-Shing Lau, Kai-Ming Yang, Pu-Ju Lin, Cheng-Ta Ko, Tzyy-Jang Tseng
  • Patent number: 11504945
    Abstract: An item may be formed from structures that include holes. Stitching may be used to form a seam that joins the structures. The stitching may be formed from a chain stitch that passes through the holes. The holes may be formed from loops of knit fabric or other holes. Leather layers, polymer layers, fabric layers, and other structures with holes may be joined using the stitching. During fabrication, a layer of material with holes may be placed on an adjustable-shape fixture having a bed of needles. The shape of the bed of nails in the adjustable-shape fixture may then be changed. After the fixture has been used to transform the shape of one or more of the structures, the structures may be placed on needles in an assembly fixture and the stitching between the structures may be formed. The item may be an electronic device cover or other item.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: November 22, 2022
    Assignee: Apple Inc.
    Inventors: Sofiane Berlat, Aedhan M. Loomis, Peter F. Coxeter, Sarah J. Montplaisir, Timon A. Wright, Yohji Hamada, Patrick Perry, Chad J. Miller, Andrew L. Rosenberg, Daniel A. Podhajny, Daniel D. Sunshine, Jessica J. Lu, Lia M. Uesato, Donald L. Olmstead
  • Patent number: 11468800
    Abstract: A back-film structure may include a first back-film portion which serves as a first circle upon rolling and a second back-film portion arranged side by side with the first back-film portion in the rolling direction, wherein a thickness of the first back-film portion increases in the rolling direction. This solution can ensure that the inner surface of the tail end of the first back-film portion is located as close as possible to the inner surface of the head end of the first back-film portion after the rolling.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: October 11, 2022
    Assignee: Beijing BOE Technology Development Co., Ltd.
    Inventors: Tao Wang, Song Zhang
  • Patent number: 11450598
    Abstract: A package that includes an integrated device, a substrate coupled to the integrated device, and an encapsulation layer coupled to the substrate. The encapsulation layer encapsulates the integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects located in the at least one dielectric layer, wherein at least one of the interconnects has a rectangular side cross-section having at least one corner with a corner radius less than a corner radius threshold.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: September 20, 2022
    Assignee: Qualcomm Incorporated
    Inventor: Sebastian Brunner
  • Patent number: 11419222
    Abstract: A method of manufacturing a circuit board includes: providing a substrate including a bottom layer and a resin layer over the bottom layer, the resin layer including a first surface in contact with the bottom layer and a second surface opposite to the first surface; forming a plurality of vias through the resin layer; depositing a first metal layer in the vias, the first metal layer filling a portion of each of the vias; depositing a second metal layer over the first metal layer and in the vias; forming a patterned metal layer over the second metal layer and extending from each of the vias to a position over the second surface; separating the bottom layer and the resin layer; and removing a portion of the resin layer from the first surface, so that the first metal layer protrudes from the resin layer.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: August 16, 2022
    Assignee: Unimicron Technology Corp.
    Inventor: Hsin-Chi Hu
  • Patent number: 11373779
    Abstract: Proposed is a conductive particle used for a testing socket electrically connecting a lead of a device to be tested and a pad of a test board by being arranged between the device to be tested and the test board, wherein the conductive particle has a predetermined depth d and has a length l that is greater than a width w, the conductive particle having a body part in a pillar shape, a first convex part having an upper surface, formed in a top of the body part, and a second convex part having a lower surface, formed in a bottom of the body part.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: June 28, 2022
    Assignee: SNOW CO., LTD.
    Inventor: Gyu Sun Kim
  • Patent number: 11342259
    Abstract: An electronic module includes an electronic part including a bottom surface and lands, the bottom surface including a first region and a third region surrounding the first region, the first lands being disposed in the third region, a printed wiring board including a main surface and second lands, the main surface including a second region and a fourth region surrounding the second region, the main surface facing the bottom surface of the electronic part, the second lands being disposed in the fourth region, solder bonding portions respectively bonding the first lands to the second lands, and a resin portion containing a cured product of a thermosetting resin and being in contact with the solder boding portions. A recess portion is provided in the second region. The resin portion is not provided in the recess portion.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: May 24, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Shingo Ishiguri, Mitsutoshi Hasegawa, Kunihiko Minegishi, Takashi Sakaki
  • Patent number: 11335217
    Abstract: A display device and a method for manufacturing a display device is provided. The display device includes a display panel. The display panel includes a bending portion, a first non-bending portion and a second non-bending portion, positioned at two opposite sides of the bending portion. The second non-bending portion is positioned by bending the bending portion in an asymmetric and non-180 degree way toward a back side of the first non-bending portion. The present disclosure solves the issues of the conventional art, which cannot narrow down the width of the side frame.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: May 17, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Cuilin Zhu
  • Patent number: 11319398
    Abstract: Method for the production of polyoxazolidinone compounds, comprising the reaction of at least one biscarbamate compound (A) with at least one bisepoxide compound (B) in the presence of at least one base (D), at least one Lewis acid catalyst (E), and optionally at least one compound (C), wherein the compound (C) comprising a mono-carbamate group, a mono-isocyanate group and/or a mono-epoxide group, and wherein the base (D) having a pKb-value of ?9. The invention is also related to the resulting polyoxazolidinone compounds.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: May 3, 2022
    Assignee: Covestro Deutschland AG
    Inventors: Thomas Ernst Müller, Christoph Gürtler, Carsten Koopmans, Volker Marker, Claudine Rangheard, Walter Leitner
  • Patent number: 11304309
    Abstract: A printed circuit board according to an embodiment of the present disclosure includes a base film having an insulating property, and a conductive pattern that is stacked on at least one surface of the base film and that includes a plurality of wiring parts arranged in parallel. The plurality of wiring parts have an average width of 5 ?m or more and 15 ?m or less. The plurality of wiring parts have an electroless plating layer and an electroplating layer stacked on the electroless plating layer. A void density at an interface between the electroless plating layer and the electroplating layer in a section of the plurality of wiring parts in a thickness direction is 0.01 ?m2/?m or less.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: April 12, 2022
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shoichiro Sakai, Eiko Imazaki, Koji Nitta
  • Patent number: 11297722
    Abstract: A multi-layered circuit board proofed against conductor loss or diminution when heated includes first and second circuit base boards. Each first circuit base board includes a first dielectric layer and a first wiring layer formed thereon and a first stepped paste block as a conductor formed in the first dielectric layer. The first stepped paste block is electrically connected to the first dielectric layer. Each second circuit base board includes a second dielectric layer and a second wiring layer, a second stepped paste block as a conductor is formed in the second dielectric layer. When pressed together for an electrical interconnection, the paste blocks are sealed and thus captive between the first and second circuit base boards.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: April 5, 2022
    Assignees: Avary Holding (Shenzhen) Co., Limited., QING DING PRECISION ELECTRONICS (HUAIAN) CO., LTD
    Inventors: Zhi Guo, Chao-Feng Huang
  • Patent number: 11276630
    Abstract: Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Robert L. Sankman, Sanka Ganesan
  • Patent number: 11227823
    Abstract: A wiring structure is provided. The wiring structure includes an upper redistribution structure, a lower redistribution structure, a conductive structure, an upper bonding layer and a lower bonding layer. The conductive structure is disposed between and electrically connected to the upper redistribution structure and the lower redistribution structure. The upper bonding layer is disposed between the upper redistribution structure and the conductive structure to bond the upper redistribution structure and the conductive structure together. The lower bonding layer is disposed between the lower redistribution structure and the conductive structure to bond the lower redistribution structure and the conductive structure together.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: January 18, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tang-Yuan Chen, Chih-Pin Hung
  • Patent number: 11227714
    Abstract: A coil component includes: a body including a magnetic material and a coil of which both ends are externally exposed; intermetallic compounds disposed on the exposed both ends of the coil; and external electrodes disposed on the body to cover the intermetallic compounds. The external electrodes include: conductive resin layers disposed on outer surfaces of the body to contact the exposed both ends of the coil and including base resins, a plurality of metal particles disposed in the base resins, and conductive connecting parts surrounding the plurality of metal particles and contacting the intermetallic compounds. The coil component further includes electrode layers disposed on the conductive resin layers and contacting the conductive connecting parts.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: January 18, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yoon Hee Lee, Bon Seok Koo, Yeon Tae Kim, Chang Hak Choi, Jung Min Kim
  • Patent number: 11211316
    Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a conductive structure and at least one conductive through via. The conductive structure includes a plurality of dielectric layers and a plurality of circuit layers in contact with the dielectric layers. The conductive through via extends through at least a portion of the conductive structure. At least one of the circuit layers includes a first portion in contact with the conductive through via and a second portion in contact with the dielectric layer. A surface roughness of the first portion of the circuit layer is greater than a surface roughness of the second portion of the circuit layer.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: December 28, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Patent number: 11205642
    Abstract: A twistable light emitting diode display module including a twistable substrate, an electrode pattern layer, an insulating layer, a circuit layer, and a plurality of light emitting diode devices. The electrode pattern layer is disposed on the twistable substrate. The insulating layer is disposed on the electrode pattern layer, where an edge of the insulating layer has an opening, located at an edge of the twistable substrate and exposing a part of the electrode pattern layer. The circuit layer is disposed on the insulating layer and on sidewalls of the opening, and is connected to the electrode pattern layer. The plurality of light emitting diode devices are disposed on the circuit layer and are electrically connected to the circuit layer respectively, wherein each of the plurality of light emitting diode devices includes a driving circuit.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: December 21, 2021
    Assignee: National Taipei University of Technology
    Inventors: Syang-Peng Rwei, Tzu-Wei Chou
  • Patent number: 11183319
    Abstract: A wire harness includes: an electrical wire including a core wire and an insulating covering for covering the core wire; and a sheet material in which the electrical wire is disposed on a resin main surface, and a part of the main surface having contact with the electrical wire is welded to the insulating covering of the electrical wire, thereby forming an electrical wire fixing part. A largest thickness dimension in the electrical wire fixing part in the sheet material is formed larger than a thickness dimension in a part of the sheet material where the electrical wire is not disposed.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: November 23, 2021
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Housei Mizuno, Daichi Fukushima, Miyu Aramaki
  • Patent number: 11183446
    Abstract: X.5 layer substrates that do not use an embedded traces substrate process during formation may produce a high yield with relaxed L/S in a short manufacturing time (only 4× lamination process without a detach process) at a low cost. For example, a substrate may include an mSAP, two landing pads, two escape lines, two bump pads, and a photo-imageable dielectric layer on the mSAP patterned substrate.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: November 23, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Jaehyun Yeon, Suhyung Hwang, Hong Bok We, Kun Fang
  • Patent number: 11152274
    Abstract: A semiconductor device package includes a semiconductor device, a conductive bump, a first encapsulant and a second encapsulant. The semiconductor device has a first surface, a second surface and a lateral surface. The second surface is opposite to the first surface. The lateral surface extends between the first surface and the second surface. The semiconductor device comprises a conductive pad adjacent to the first surface of the semiconductor device. The conductive bump is electrically connected to the conductive pad. The first encapsulant covers the first surface of the semiconductor device and a first portion of the lateral surface of the semiconductor device, and surrounds the conductive bump. The second encapsulant covers the second surface of the semiconductor device and a second portion of the lateral surface of the semiconductor device.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: October 19, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Hsuan Lee, Sung-Mao Li, Ming-Han Wang, Ian Hu
  • Patent number: 11096278
    Abstract: A ceramic circuit board includes a ceramic substrate and metal layers provided to both surfaces of the ceramic substrate and containing Al and/or Cu, wherein a measurement value ?1 of a linear thermal expansion coefficient at 25° C. to 150° C. is 5×10?6 to 9×10?6/K, a ratio ?1/?2 of the ?1 to a theoretical value ?2 of the linear thermal expansion coefficient at 25° C. to 150° C. is 0.7 to 0.95, and at least one of the metal layers forms a metal circuit.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: August 17, 2021
    Assignee: DENKA COMPANY LIMITED
    Inventors: Atsushi Sakai, Hideki Hirotsuru, Kohki Ichikawa, Yoshitaka Taniguchi
  • Patent number: 11079886
    Abstract: A display substrate includes a substrate, a first insulator, a metal film, a second insulator, an alignment film, a line, and film forming area defining recesses. The substrate includes a display area and a non-display area. The metal film is disposed in a layer upper than the first insulator. The second insulator is disposed upper than the metal film and has a thickness smaller than a thickness of the first insulator. The alignment film is disposed upper than the second insulator. The line extends to straddle the display area and the non-display area and includes a section of the metal film. The film forming area defining recesses in the non-display area to extend in a direction crossing an extending direction of the line but not to overlap the line include recessed sections of the first insulator to define a forming area of the alignment film.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: August 3, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masaki Maeda, Yoshihito Hara
  • Patent number: 11037846
    Abstract: A semiconductor package structure includes a substrate, a die electrically connected to the substrate, and a first encapsulant. The die has a front surface and a back surface opposite to the front surface. The first encapsulant is disposed between the substrate and the front surface of the die. The first encapsulant contacts the front surface of the die and the substrate.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: June 15, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Hsu-Chiang Shih, Cheng-Yuan Kung, Hung-Yi Lin
  • Patent number: 10996785
    Abstract: A touch display device and a touch display panel are provided. The touch display panel includes a bend area adjacent to the periphery of the touch display panel, and touch lines disposed in the bend area have zigzag shapes that extend at angles with respect to a bend axis about which the bend area is bent. A first dielectric layer includes a compensation pattern that is located in the bend area and includes an opening that extends in a direction parallel to the bend axis. A second dielectric layer protrudes into the opening of the compensation pattern in a depth direction. During bending of the bend area, this configuration disperses force applied to portions of the touch lines and the dielectric layers in the bend area. This can consequently prevent both cracking due to bending and moisture permeation due to cracks.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: May 4, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: Yangsik Lee, JiHyun Jung, DeukSu Lee, JaeGyun Lee, Ruda Rhe, Jeonghoon Lee, Su Chang An
  • Patent number: 10993329
    Abstract: A first board includes a first insulating substrate including a first main surface, a first electrode pad, and a first resist film. The first electrode pad is a conductor pattern provided on the first main surface. The first resist film is provided on the first main surface and is located closer to the first electrode pad than any conductor provided on the first main surface. The first resist film is spaced away from the first electrode pad with a gap provided between the first resist film and the first electrode pad. The first resist film is thicker than the first electrode pad.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: April 27, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kuniaki Yosui, Daisuke Tonaru, Hideyuki Taguchi, Genro Kato
  • Patent number: 10986733
    Abstract: A method for manufacturing an electromechanical structure, includes producing conductors and/or graphics on a substantially flat film, attaching electronic elements on the said film in relation to the desired three-dimensional shape of the film, forming the said film housing the electronic elements into a substantially three-dimensional shape, and using the substantially three-dimensional film as an insert in an injection molding process by molding substantially on said film, wherein a preferred layer of material is attached on the surface of the film. A corresponding arrangement for carrying out the method is also presented.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: April 20, 2021
    Assignee: TACTOTEK OY
    Inventors: Mikko Heikkinen, Jarmo Sääski, Jarkko Torvinen, Paavo Niskala, Mikko Sippari, Pasi Raappana, Antti Keränen
  • Patent number: 10986734
    Abstract: A method for manufacturing an electromechanical structure, includes producing conductors and/or graphics on a substantially flat film, attaching electronic elements on the said film in relation to the desired three-dimensional shape of the film, forming the said film housing the electronic elements into a substantially three-dimensional shape, and using the substantially three-dimensional film as an insert in an injection molding process by molding substantially on said film, wherein a preferred layer of material is attached on the surface of the film. A corresponding arrangement for carrying out the method is also presented.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: April 20, 2021
    Assignee: TACTOTEK OY
    Inventors: Mikko Heikkinen, Jarmo Sääski, Jarkko Torvinen, Paavo Niskala, Mikko Sippari, Pasi Raappana, Antti Keränen
  • Patent number: 10973420
    Abstract: The present invention relates, generally, to a component containing a composite of at least two layers that are connected to each other, in which the first layer comprises a hole and the second layer has a thickness in the range of 1 to 50 ?m. The first and second layers each contain at least one metal and compositions of the first and second layers are different. Further objects of the present invention include a method for producing a component containing at least two layers that are connected to each other and have the aforementioned features, a method for producing a component containing at least three layers that are connected to each other and have the aforementioned features, as well as a component that is obtained by one of the aforementioned methods and a device containing at least one of the aforementioned components for use in a living body.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: April 13, 2021
    Assignee: HERAEUS DEUTSCHLAND GMBH & CO. KG
    Inventors: Nicholas Baltos, Oliver Keitel, Lena Weber, Andreas Reisinger
  • Patent number: 10955442
    Abstract: Elastic sleeve (1) for electrically insulating a HV/MV power conductor in a power network, comprising a) a shrinkable or expandable elastic sleeve body (10); b) a receiving space (20) in the sleeve body, for receiving the power conductor; c) a cavity (30) formed in the sleeve body; and d) a divider assembly (40), arranged, at least partially, in the cavity and comprising a plurality of discrete impedance elements, operable as a voltage divider for sensing a voltage of an inner conductor of the power conductor.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: March 23, 2021
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Mark Gravermann, Gunther A. J. Stollwerck, Michael H. Stalder, Gerhard Lohmeier, Bernd Schubert, Rainer Reeken, Jens Weichold
  • Patent number: 10912194
    Abstract: Generally, the present disclosure provides example embodiments relating to a printed circuit board (PCB). In an embodiment, a structure includes a PCB including insulating layers with respective metal layers being disposed therebetween. Each of first layers of the insulating layers includes a first fiberglass content. A second layer of the insulating layers has a second fiberglass content less than the first fiberglass content. For example, in some embodiments, the second insulating layer does not include a fiberglass matrix.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: February 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Haw Tsao, Tsung-Hsing Lu, Li-Huan Chu
  • Patent number: 10881008
    Abstract: A multi-layered circuit board proofed against conductor loss or diminution when heated includes first and second circuit base boards. Each first circuit base board includes a first dielectric layer and a first wiring layer formed thereon and a first stepped paste block as a conductor formed in the first dielectric layer. The first stepped paste block is electrically connected to the first dielectric layer. Each second circuit base board includes a second dielectric layer and a second wiring layer, a second stepped paste block as a conductor is formed in the second dielectric layer. When pressed together for an electrical interconnection, the paste blocks are sealed and thus captive between the first and second circuit base boards.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: December 29, 2020
    Assignees: Avary Holding (Shenzhen) Co., Limited., QING DING PRECISION ELECTRONICS (HUAIAN) CO., LTD
    Inventors: Zhi Guo, Chao-Feng Huang
  • Patent number: 10872860
    Abstract: A semiconductor package includes a connection structure including an insulating layer, a wiring layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the wiring layer. A frame is disposed on the connection structure and has one or more through-holes. A semiconductor chip and passive components are disposed in the one or more through-holes of the frame on the connection structure. A first encapsulant covers at least portions of the passive components and the frame. A frame wiring layer is disposed on the frame, and a location identifying mark is disposed around the semiconductor chip on the frame and is spaced apart from the frame wiring layer. At least a portion of the location identifying mark is not covered by the first encapsulant.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: December 22, 2020
    Assignee: SAMSUNG ELECTRONICS CO.. LTD.
    Inventor: Min Sek Jang
  • Patent number: 10873043
    Abstract: A flexible display apparatus can have a flexible substrate including: an active area including a plurality of driving TFTs and a plurality of organic emission elements, and an inactive area including a first inactive area adjacent to the active area, a second inactive area for a circuit board, and a bending area between the first inactive area and the second inactive area; a component disposed on at least a part of the first inactive area; a plurality of wiring lines extending from the plurality of driving TFTs to the first inactive area, the bending area and the second inactive area; and a support layer disposed across the active area, the first inactive area, the bending area, and the second inactive area, in which a portion the support layer includes at least one cut portion overlapping with the bending area of the flexible substrate.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: December 22, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Jaehyun Jin
  • Patent number: 10868221
    Abstract: A method for manufacturing a chip-mounting substrate includes a pre-coating step of forming a precoat on a substrate including a plurality of conductive portions and an insulating portion interposed between the conductive portions, an etching step of etching at least a portion of the precoat through a laser to form a pattern, and a step of forming a metal layer on the substrate. The pattern is disposed on at least one of the conductive portions, and the metal layer is formed in the pattern.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: December 15, 2020
    Assignee: POINT ENGINEERING CO., LTD.
    Inventors: Bum Mo Ahn, Seung Ho Park, Tae Hwan Song