Abstract: There is provided a connection structure of a circuit member including: a first circuit member having a first main surface provided with a first electrode; a second circuit member having a second main surface provided with a second electrode; and a joining portion which is interposed between the first main surface and the second main surface, in which the joining portion has a solder portion which electrically connects the first electrode and the second electrode to each other, in which the solder portion contains a bismuth-indium alloy, and in which an amount of bismuth contained in the bismuth-indium alloy exceeds 20% by mass and is equal to or less than 80% by mass.

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

Abstract: A printed circuit board includes first and second insulating layers, a wiring trace, a metal thin film, and a connection terminal. The wiring trace is formed on the first insulating layer. The metal thin film is formed on the wiring trace, and has a thickness larger than 0 nm and not more than 150 nm. The second insulating layer is formed on the first insulating layer to cover the metal thin film. The connection terminal is formed on the first insulating layer to be electrically connected to the wiring trace and exposed from the second insulating layer.

Abstract: A suspension board with circuit includes a metal supporting board, a conductor layer having a terminal capable of being electrically connected to the piezoelectric element and disposed above the metal supporting board at spaced intervals thereto, a first insulating layer disposed between the metal supporting board and the conductor layer so as to support the conductor layer, and a second insulating layer disposed on the first insulating layer and the conductor layer so as to expose the terminal. The first insulating layer includes a first portion including the terminal viewed from a thickness direction of the metal supporting board and a second portion disposed in a position different from that of the first portion viewed from the thickness direction. The thickness of the first portion is thinner than that of the second portion.

Abstract: A printed circuit board includes a core insulating layer including an isotropic resin, a first circuit pattern filled in a circuit pattern groove at an upper portion or a lower portion of the core insulating layer, a first insulating layer provided in a top surface thereof with a circuit pattern groove and covering the first circuit pattern, and a second circuit pattern to fill the circuit pattern groove of the first insulating layer. A material, such as polyimide, having an isotropic structure is employed for the core insulating layer, thereby preventing the substrate from being bent without glass fiber. Since the glass fiber is not included, the buried pattern is formed at the upper portion or the lower portion of the core insulating layer, so that the thin substrate is fabricated.

Abstract: A wiring board includes first insulating layers; first wiring layers; first via wirings; second insulating layers; second wiring layers; second via wirings; and a solder resist layer, wherein the first insulating layers are composed of non-photosensitive resin, wherein the second insulating layers, and the solder resist layer are composed of photosensitive resin, respectively, wherein the first surface of the uppermost first insulating layer and the first end surface of the first via wiring embedded in the uppermost first insulating layer are polished surfaces, wherein the first end surface of the first via wiring embedded in the uppermost first insulating layer is flush with the first surface of the uppermost first insulating layer, and wherein the wiring density of the second wiring layers is higher than the wiring density of the first wiring layers.

Abstract: A touch-sensitive display includes a plurality of electrodes configured to detect a touch input received at the touch-sensitive display device. A plurality of touch wires formed on a substrate are electrically connected to the electrodes and configured to detect a touch input received at the touch-sensitive display device. A plurality of first conductive patterns on the substrate are each connected to a touch wire and extend in a first direction from the corresponding touch wire. An insulation layer is disposed on the plurality of touch wires and first conductive patterns, and a plurality of second conductive patterns are disposed on the insulation layer. Each second conductive pattern contacts one of the touch wires via a contact hole in the insulation layer and at least partially overlaps a corresponding one of the first conductive patterns, while being separated from the corresponding one of the first conductive patterns by the insulation layer.

Abstract: A wiring board includes: a first insulating layer which is made of an insulating resin containing a thermosetting resin as a main component; a recess portion formed in an upper surface of the first insulating a layer; a first wiring layer formed in the recess portion and comprising an upper surface exposed from the first insulating layer; a via wiring penetrating the first insulating layer in a thickness direction thereof and comprising an upper end surface exposed from the first insulating layer; a second wiring layer formed on the upper surface of the first insulating layer to contact the upper end surface of the via wiring and the upper surface of the first wiring layer; and a second insulating layer which is made of an insulating resin containing a photosensitive resin as a main component and which is formed on the upper surface of the first insulating layer.

Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns comprising: dual diameter first and second signal vias forming a differential signal pair, the first and second signal vias being configured to accept contact tails of signal conductors of a connector; dual diameter ground shadow vias adjacent to each of the first and second signal vias, wherein the dual diameter shadow ground vias have a reversed diameter configuration with respect to the dual diameter first and second signal vias; and ground vias configured to accept contact tails of ground conductors of the connector.

Abstract: A wiring board includes a wiring layer including a surface on which a recess is formed and a metal layer formed on a bottom surface of the recess. A surface of the metal layer facing away from the bottom surface of the recess is closer to the bottom surface of the recess than is the surface of the wiring layer.

Abstract: A printed circuit board is formed from a plurality of thinner PCBs stacked on top of each other with an intermediate metal interconnect material selectively positioned between adjacent PCBs. The metal interconnect material is selectively positioned on surface contact points of correspondingly aligned plated through holes on the adjacent printed circuit boards. The stacked printed circuit boards and intermediate metal interconnect material are laminated, thereby sintering the metal interconnect material and the surface contact points of the plated through holes to form electrical interconnects between plated through holes on adjacent printed circuit boards. The metal interconnect material is preferably the same as the plating material used to plate the through holes, such as copper.

Abstract: The present disclosure relates to an extremely deformable structure comprising a basic displacement unit having an embedded form, in which m polygonal basic unit cells are disposed adjacent to each other, m separation parts are formed among the m basic unit cells, a junction part connecting the basic unit cells to each other is formed between the basic unit cells in which the junction part has a junction part pattern in which an external junction part disposed at the outer portion of the basic unit cell and an internal junction part which is not in contact with the outer portion of the basic unit cell are sequentially repeated, and the relative positions of the m basic unit cells are changed according to the junction part pattern, and thus, are activated (here, m is an integer of 4 or 6). Further, the present disclosure relates to a lithium secondary battery made from the extremely deformable structure.

Abstract: A flexible circuit board includes a wiring layer, two photosensitive resin layers, and two electromagnetic interference shielding layers. The wiring layer includes at least one signal line, two ground lines and at least two gaps. Each gap includes two opening portions. The two photosensitive resin layers cover the signal line and the opening portions, and are connected to each end of each ground line. Each electromagnetic interference shielding layer covers one photosensitive resin layer away from the signal line, portions of the two ground lines not connected to the photosensitive resin layer, and portions of the gaps not covered by the two photosensitive resin layers, thereby causing the portions of each gap not covered by the two photosensitive resin layers to define a receiving chamber. Each end of each receiving chamber communicates with one opening portion of the corresponding gap to define a cavity.

Abstract: Provided herein is a method for producing a nano polaroid film using a one-pack type or two-pack type blackening ink so that a single layer film may replace a conventional polaroid film generally produced by superposing various types of optical films, and especially, a method for producing a nano polaroid film consisting of one film and having excellent observability by coating a transparent nano pattern substrate with a functional ink that contains a blackening material, and then removing particles formed on protruding portions using an etching solution, and refilling the functional ink into grooves.

Abstract: A multilayer wiring board includes a first metal foil wiring layer that has at least two or more layers of metal foil wiring lines and is arranged on a mounting surface side for mounting a surface mount type component, a wire wiring layer that is arranged on an opposite side of the mounting surface, and in which an insulation coating wire is wired, and a first interlayer conduction hole that has a conduction part which electrically connects the metal foil wiring line positioned on a surface of the first metal foil wiring layer to at least one of the metal foil wiring line in an inner layer of the first metal foil wiring layer and the insulation coating wire of the wire wiring layer. A hole diameter of the first interlayer conduction hole varies in a board thickness direction of the multilayer wiring board.

Abstract: Cost effective and efficient methods to maximize printed circuit board (PCB) utilization with minimized signal degradation are provided. The methods include electrically isolating a segmented via structure by controlling the formation of a conductive material within a plated via structure by utilizing different diameter drills within a via structure for trimming the conductive material at the via shoulder (i.e., the rim of a drilled two diameter hole boundary). The trimmed portion may be voided in the via structure for allowing electrically isolated plated through-hole (PTH) segments. One or more areas of trimmed rims within the via structure are used to form multiple stair like diameter holes to create one or more voids in the via structure. As a result, the formation of conductive material within the via structure may be limited to those areas necessary for the transmission of electrical signals.

Abstract: An electronic component includes a multilayer capacitor and an interposer The multilayer capacitor includes an element body and a pair of external electrodes. The interposer includes a substrate, a pair of first electrodes, and is pair of second electrodes. The substrate includes first and second principal faces. The pair of first electrodes are disposed on the first principal face. The pair of second electrodes are disposed on the second principal thee. The element body includes a first portion and a pair of second portions. The first portion is covered by the external electrodes. The pair of second portions are located on both sides or the first portion and separated from the interposer. A width in a second direction of the pair of external electrodes is smaller than a width in the second direction of the element body and larger than a width in the second direction of the second portion.

Abstract: An electronic device mounting apparatus to be mounted with multiple electronic components, each of which includes at least one wire. The electronic device mounting apparatus includes a base unit and multiple pin units. The base unit includes a base wall and two side walls extending from the base wall. Each of the side walls has a first surface. The pin units are correspondingly mounted in the side walls and are spaced apart from one another. Each of the pin units has a wire-connecting segment having a connection portion that projects from the first surface, and two projecting portions that project from the connection portion and that define a slit therebetween. The slit is for a corresponding wire to be clamped therein by the projecting portions.

Abstract: A method for forming a semiconductor device package substrate including a fiducial mark is provided. The method of forming the package substrate includes forming a dielectric layer over a lower portion of the package substrate. A metal layer is formed over a fiducial region of the package substrate. The metal layer is etched to form a first signal line in the fiducial region. A passivation layer is formed over the first signal line. The passivation layer is etched over the first signal line to form a fiducial mark.

Abstract: Provided is a printed circuit board consisting of laminated substrates each with a fiberglass cloth contained in its resin and with a wiring arranged onto at least one of its surfaces, wherein, in at least one of substrates provided with a wiring for transmitting a higher speed signal than that transmitted by wirings arranged onto the other substrates, a fiberglass cloth having a different property from that of the other substrates is contained.

Abstract: A printed circuit board comprising conductive layers separated by insulation layers of dielectric material, at least one conductive layer being patterned and having at least one signal line embedded in insulation material. The at least one signal line is covered by a dielectric film, followed by a thin conductive layer, whereby the dielectric film covers at least one surface and both sides of the at least one signal line and the thin conductive layer extends, separated by the dielectric film, over the at least one surface of the signal line and at least partially over the height of both sides of the signal line.

Abstract: A printed circuit board includes a printed circuit board, a semiconductor device mounted on the printed circuit board, a capacitor element mounted on the printed circuit board 2, a ground conductor plane to which a ground terminal of the semiconductor device is connected, and first and second power source conductor planes which are arranged so as not to contact with each other. The second power source conductor plane and the ground conductor plane are arranged so as to oppose to each other to form a planar capacitor. The printed circuit board has a first connecting conductor which connects a power source terminal of the semiconductor device with the second power source conductor plane, and a second connecting conductor which connects the first power source conductor plane with the second power source conductor plane through a first terminal of the capacitor element. Thereby, an electromagnetic radiation noise is reduced.

Abstract: A cabled midplane includes a first support plate along a plane between a first connector set and a second connector set that connect to line cards on either side of the cabled midplane. The first connector set and the second connector set include connector slices. A wiring sub-layer includes cable slices to provide a connection between the first connector slice of a connector of the first connector set to the first connector slice of a connector of the second connector set, such that the first wiring sub-layer connects each connector of the first connector set, through one cable slice, to a connector of the second connector set. Additional wiring sub-layers are added, and a second support plate, parallel to the first support plate, is provided to encase and support the wiring sub-layers between the first support plate and the second support plate. Other apparatuses and methods are described.

Abstract: A printed wiring board including a connection part that is connected to a projecting portion of an external member by soldering, the connection part including a first hole in which the projecting portion is inserted, a main land to which the projecting portion is soldered, a metallic pattern that is drawn from the main land, and a sub-land that is connected to the main land through the metallic pattern, wherein the main land is constructed with a metallic film configured to cover a peripheral region of the first hole in at least a front face of the printed wiring board including the front face and a back face, the front face to which the soldering is performed and the back face on a side opposite to the front face, and the metallic film is not formed on a sidewall forming the first hole, and where the sub-land is constructed with a metallic film configured to cover a sidewall formed by a second hole piercing the printed wiring board and a peripheral region of the second hole in both the front face and the bac

Abstract: A patterned transparent conductor includes: (1) a substrate; (2) first additives at least partially embedded into a surface of the substrate within a first area of the surface corresponding to a lower sheet resistance portion; and (3) second additives at least partially embedded into the surface of the substrate within a second area of the surface corresponding to a higher sheet resistance portion. A sheet resistance of the higher sheet resistance portion is at least 100 times a sheet resistance of the lower sheet resistance portion.

Abstract: A micro-wire rib structure includes a substrate and a cured layer formed on or over the substrate, the cured layer having a cured-layer surface. A micro-channel is imprinted in the cured layer, the micro-channel having a micro-channel depth, a micro-channel bottom, first and second micro-channel sides, and one or more ribs having opposing rib sides and a rib top defining a rib height less than the micro-channel depth. Each rib is located between the first and second micro-channel sides and extends from the micro-channel bottom toward the cured-layer surface. A cured electrical conductor forming a micro-wire is formed in the micro-channel. The micro-wire extends continuously from the first micro-channel side, over the micro-channel bottom, the rib side(s) and rib top(s) to the second micro-channel side forming a continuous electrical conductor from the first micro-channel side to the second micro-channel side.

Abstract: Certain pyridine-ketone compounds have been found to provide anticorrosion properties when incorporated into silver nanowire containing films. Such compounds may be incorporated into one or more silver nanowire containing layers or in one or more layers disposed adjacent to the silver nanowire containing layers.

Abstract: A semiconductor apparatus has one or more semiconductor chips. The semiconductor apparatus may include a power supply pad; power lines disposed on one side of the power supply pad, and including a first power line and a second power line; and connection lines connecting the power supply pad and the power lines. The connection lines may include a plurality of first connection lines connecting the power supply pad and the first power line, and a plurality of second connection lines connecting the power supply pad and the second power line, and disposed between the first connection lines. One or more pair of adjacent first connection lines may have a connection part by which the pair of adjacent first connection lines are connected with each other.

Abstract: A lightweight radio/Audio player for vehicular application includes a case and frontal interface formed of polymer based material molded to provide details to accept audio devices and radio receivers, as well as the circuit boards required for electrical control and display. The case and frontal interface are of composite structure, including an insert molded electrically conductive wire mesh screen that has been pre-formed to contour with the molding operation. The wire mesh provides shielding and grounding of the circuit boards via exposed wire mesh pads and adjacent ground clips.

Abstract: In some embodiments, a printed circuit board (PCB) comprises a substrate comprising an insulating material. The PCB further comprises a plurality of conductive tracks attached to at least one surface of the substrate. The PCB further comprises a multi-layer coating deposited on the at least one surface of the substrate. The multi-layer coating (i) covers at least a portion of the plurality of conductive tracks and (ii) comprises at least one layer formed of a halo-hydrocarbon polymer. The PCB further comprises at least one electrical component connected by a solder joint to at least one conductive track, wherein the solder joint is soldered through the multi-layer coating such that the solder joint abuts the multi-layer coating.

Abstract: A method produces a multilayer element with a substrate and at least one conductor structure connected in an areal manner to the substrate, which has first regions of electrically conductive material, which is present in accordance with a prescribed pattern, while electrically non-conductive second regions lie between the first regions.

Abstract: A method of manufacturing a wiring substrate, includes obtaining a laminated body in which a first copper tin alloy layer and a copper layer are arranged in sequence on a first coupling agent layer, on a first insulating resin layer, forming a seed layer on the copper layer, forming a plating resist in which an opening portion is provided on the seed layer, forming a metal plating layer in the opening portion of the plating resist by applying an electroplating that utilizes the seed layer as a plating power feeding path, removing the plating resist, and forming a first wiring layer on the first coupling agent layer by etching the seed layer, the copper layer, and the first copper tin alloy layer while using the metal plating layer as a mask.

Abstract: A substrate package includes a woven fabric having electrically non-conductive strands woven between electrically conductive strands including wire strands, co-axial strands, and/or an inductor pattern of strands. The package may be formed by an inexpensive and high throughput process that first weaves the non-conductive strands (e.g., glass) between the conductive strands to form a circuit board pattern of conductive strands in a woven fabric. Next, the woven fabric is impregnated with a resin material to form an impregnated fabric, which is then cured to form a cured fabric. The upper and lower surfaces of the cured fabric are subsequently planarized. Planarizing segments and exposes ends of the wire, co-axial, and inductor pattern strands. Since the conductive strands were formed integrally within the planarized woven fabric, the substrate has a high mechanical stability and provides conductor strand based electrical components built in situ in the substrate package.

Abstract: Embodiments of the invention provide a printed circuit board having a structure in which a plurality of insulating layers having a metal wiring formed on one surface thereof are stacked, wherein a metal layer is interposed in the insulating layers, in order to improve warpage property of the board.

Abstract: According to one embodiment, a flexible printed wiring board includes a first conductor layer formed on the first surface of an insulation base, a second conductor layer formed on the second surface of the insulation base, a first insulation layer covering the first conductor layer, and a second insulation layer covering the second conductor layer. The first insulation layer has an opening formed in a position corresponding to a connecting terminal portion to expose the first conductor layer. A metal layer is provided in a region ranging from the connecting terminal portion to a bending presumed portion. The metal layer is positioned behind the opening between the second surface and the second insulation layer to avoid the first conductor layer.

Abstract: A multilayer wiring board has a strip structure comprising a core material in which a ground pattern is disposed on one side of an insulating layer and a strip line is disposed on the other side, a prepreg disposed on the strip line of the core material, and a ground pattern disposed on the prepreg. In this multilayer wiring board, the core material is formed with a high frequency-adaptive base material, and the prepreg is formed with a general-purpose material.

Abstract: [Objective] To provide a multilayer wiring substrate in which, even when a core substrate is thinned, the core substrate can reliably accommodate a capacitor. [Means for Solution] A multilayer wiring substrate 10 includes a sheetlike capacitor element 101, a resin filler 92, and via conductors 43 and 47. A sheetlike capacitor element 101 has an element main-surface 102 and an element back-surface 103, is configured such that a dielectric layer 107 is sandwiched directly between a main-surface-side electrode layer 105 exposed at the element main-surface 102 side and a back-surface-side electrode layer 106 exposed at the element back-surface 103 side, and is accommodated at least partially in an accommodation hole 90 such that a core main-surface 12 and the element main-surface 102 face the same direction. A resin filler 92 is charged into a gap between the sheetlike capacitor element 101 and an inner wall surface 91 of the accommodation hole 90.

Abstract: A connecting member such as a terminal base is used in connection with a printed circuit board unit in which circuit elements such as a power module are mounted on a printed circuit board. The connecting member connects the circuit element of an electrical circuit including the printed circuit board, to an electrical wire. The connecting member includes a terminal connecting section to be directly connected to terminal pins of the circuit element; a wire connecting section to be connected to the electrical wire; and attachment sections for attaching the connecting member to the printed circuit board.

Abstract: A printed circuit substrate may be configured with at least one internal lead designed and shaped to reduce solder bridging. The printed circuit substrate can have a plurality of internal leads that each has a continuously curvilinear boundary that defines an isolation channel. The isolation channel may be configured with a uniform distance that separates a first internal lead from an adjacent second internal lead.

Abstract: A method includes fabricating a printed circuit board. The fabricating includes forming at least one conductive layer on top a first dielectric layer. The fabricating includes forming a second dielectric layer on top of the at least one conductive layer. The fabricating includes forming a thermal pad on top of the second dielectric layer. The fabricating includes forming a first through hole through the thermal pad, the second dielectric layer, the at least one conductive layer, and the first dielectric layer. The fabricating includes filling the first through hole with a conductive material to form a plated through hole. The fabricating includes topdrilling the plated through hole to remove a top portion of the conductive material from a top of the plated through hole, wherein a bottom portion of the conductive material remains in the plated through hole after removal of the top portion.

Abstract: A printed circuit board includes a first layer stack and a second layer stack coupled to the first layer stack. The first layer stack includes a first electrically-insulating layer, a first electrically-conductive layer, and a cut-out area defining a void that extends therethrough. The first electrically-insulating layer includes a first surface and an opposite second surface. The first electrically-conductive layer is disposed on the first surface of the first electrically-insulating layer. The second layer stack includes a second electrically-insulating layer. The second electrically-insulating layer includes a first surface and an opposite second surface. One or more electrically-conductive traces are disposed on the first surface of the second electrically-insulating layer. The printed circuit board further includes a device at least partially disposed within the cut-out area.

Abstract: A semiconductor package substrate includes an insulating substrate, a circuit pattern on the insulating substrate, a protective layer formed on the insulating substrate to cover the circuit pattern on the insulating substrate, a pad formed on the protective layer while protruding from a surface of the protective layer, and an adhesive member on the pad.

Abstract: A packaging substrate having an embedded through-via interposer is provided, including an encapsulant layer, a through-via interposer embedded in the encapsulant layer and having a plurality of conductive through-vias therein, a redistribution layer embedded in the encapsulant layer and formed on the through-via interposer so as to electrically connect with first end surfaces of the conductive through-vias, and a built-up structure formed on the encapsulant layer and the through-via interposer for electrically connecting second end surfaces of the conductive through-vias.

Abstract: A board for mechanically supporting and electrically connecting electronic components includes a non-conductive substrate, a plurality of electrically conductive traces and pads disposed on the non-conductive substrate, and a solder mask applied to the non-conductive substrate and covering the traces. Metal lines are disposed on the non-conductive substrate under the solder mask and along at least two sides of the pads disposed in corners of the non-conductive substrate, so that a metal line is interposed between the pads in the corners of the non-conductive substrate and each adjacent pad. The metal lines form a raised region in the solder mask along the metal lines which prevents solder bridging in the corners of the non-conductive substrate during solder reflow. A corresponding semiconductor package and semiconductor assembly with such solder bridging prevention structures are also provided.

Abstract: A semiconductor package may include: a substrate including a core layer having a first surface and a second surface which is opposite to the first surface, a wiring layer formed over the first and second surfaces and in an inside of the core layer, and having a first electrode disposed in the inside of the core layer and exposed from the core layer and a second electrode disposed over the first surface, and a passivation layer formed over the first and second surface of the core layer such that the first and the second electrodes are exposed; a first semiconductor chip disposed over the first surface of the core layer; a second semiconductor chip stacked over the first semiconductor chip; a first connection member for connecting the first semiconductor chip with the first electrode; and a second connection member for connecting the second semiconductor chip with the second electrode.

Abstract: A semiconductor package substrate includes an insulating substrate; a circuit pattern on the insulating substrate; a protective layer on the insulating substrate, the protective layer covering the circuit pattern on the insulating substrate; a pad on the protective layer; and an adhesive member on the protective layer, wherein the pad includes a first pad buried in the protective layer, and a second pad on the first pad, the second pad protruding over the protective layer.

Abstract: A printed wiring board includes a core substrate including a resin insulating layer and multiple conductor layers, a first wiring structure formed on a first surface of the core substrate and including a conductor layer and a resin insulating layer, and a second wiring structure formed on a second surface of the core substrate and including a conductor layer and a resin insulating layer. The core substrate is interposed between the first wiring structure and the second wiring structure such that the resin insulating layers and conductor layers in the core substrate, first wiring structure and second wiring structure are alternately laminated, the resin insulating layer in the first wiring structure has a vol % of resin which is larger than a vol % of resin in the resin insulating layer in the second wiring structure such that a difference in the vol % of resin in the first and second wiring structures is in the range of from 0.5% to 5.0%.

Abstract: Disclosed herein is a printed circuit board having an improved structure of a dummy part to improve warpage strength of the printed circuit board, the printed circuit board including: a plurality of insulating layers built-up therein, the plurality of insulating layers including copper clad layers; and a product zone and a dummy zone formed at a central part and along an edge part of the insulating layers, respectively, wherein the copper clad layers included in each insulating layer are arranged in the dummy zone at predetermined intervals in a longitudinal direction.

Abstract: A flex-rigid wiring board includes a flexible substrate, a non-flexible substrate positioned such that the non-flexible substrate is extending in horizontal direction of the flexible substrate, a first wiring layer on first surface sides of the flexible and non-flexible substrates, a second wiring layer on second surface sides of the flexible and non-flexible substrates, a first insulating layer covering the first sides of the flexible and non-flexible substrates and having an opening exposing a portion of the first side of the flexible substrate, and a second insulating layer covering the second sides of the flexible and non-flexible substrates and having an opening exposing a portion of the second side of the flexible substrate. The first wiring layer includes first conductor pattern on the first side of the flexible substrate, and the second wiring layer includes second conductor pattern extending across the second sides of the flexible and non-flexible substrates.

Abstract: Disclosed herein are a core substrate and a method for manufacturing the same. According to a preferred embodiment of the present invention, a core substrate includes: a porous scaffold formed with a void; an insulating material formed to fill a void of the porous scaffold; and an electronic device embedded into the porous scaffold and the insulating material and having internal electrodes exposed on both surfaces thereof.