Conducting (e.g., Ink) Patents (Class 174/257)
  • Patent number: 11139262
    Abstract: A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Mark E. Tuttle, John F. Kaeding, Owen R. Fay, Eiichi Nakano, Shijian Luo
  • Patent number: 11140778
    Abstract: A multilayer ceramic substrate according to the present disclosure has ceramic layers and a patterned conductor, and a cavity is formed in the multilayer ceramic substrate. The cavity reaches to any one of principal surfaces of the multilayer ceramic substrate and forms an opening, and the opening is covered with a sealing member at the principal surface of the multilayer ceramic substrate.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: October 5, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Issei Yamamoto
  • Patent number: 11118055
    Abstract: A phosphorus-containing resin composition comprises a first phosphorus-containing compound, a second phosphorus-containing compound and a maleimide resin; wherein the first phosphorus-containing compound comprises a compound of Formula (I), a compound of Formula (II), or a combination thereof, and wherein the second phosphorus-containing compound is different from the first phosphorus-containing compound, and the second phosphorus-containing compound is absent of a group capable of reacting with the maleimide resin.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: September 14, 2021
    Assignee: ELITE MATERIAL CO., LTD.
    Inventor: Chen-Yu Hsieh
  • Patent number: 11121487
    Abstract: A car window glass includes a glass plate having a conductor layer, a connection terminal, and a power line. The connection terminal includes metal-plate first and second join parts joined to the conductor layer via the first and second solder layers, a metal-plate bridge section connected to the first and second join parts and spaced apart from the conductor layer, and a fixing part for fixing the power line to a bridge section main surface. The power line extends from the fixing part along a glass plate main surface, and the side opposite of the side facing the glass plate main surface is free of the bridge section, and the starting point of the power line extending from the fixing part is positioned in the upper direction of a virtual line connecting the center portions of the first and second join parts with each other.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: September 14, 2021
    Assignee: Central Glass Company, Limited
    Inventors: Kohei Seki, Jun Hamada, Kazunori Furuhashi
  • Patent number: 11109481
    Abstract: A method for manufacturing a printed wiring board includes forming a base insulating layer, forming a conductor layer on the base layer, forming a solder resist layer on the base layer such that the resist layer covers the conductor layer, forming first opening exposing a first pad of the conductor layer, forming second opening exposing a second pad of the conductor layer and having diameter smaller than diameter of the first opening, forming a first bump on the first pad, and forming a second bump on the second pad such that the second bump has diameter smaller than diameter of the first bump. The first bump includes a first base plating layer and a first top plating layer, and the second bump includes a second base plating layer and a second top plating layer having upper surface higher than the uppermost position of upper surface of the first top layer.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: August 31, 2021
    Assignee: IBIDEN CO., LTD.
    Inventors: Youhong Wu, Koji Sato, Yoshihiro Kodera
  • Patent number: 11101052
    Abstract: There is provided a conductive material in which, even when a conductive material is left for a certain period of time, solder of conductive particles can be efficiently placed on an electrode, and, in addition, even if an electrode width and an inter-electrode width are narrow, occurrence of migration can be effectively suppressed, and generation of voids can be effectively suppressed. The conductive material according to the present invention contains a plurality of conductive particles in which an outer surface portion of a conductive portion comprises solder, a thermosetting compound, an acid anhydride thermosetting agent, and an organophosphorus compound.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: August 24, 2021
    Assignee: SEKISUI CHEMICAL CO., LTD.
    Inventors: Sayaka Wakioka, Hidefumi Yasui, Shuujirou Sadanaga, Masahiro Itou, Shike Sou, Yuta Yamanaka
  • Patent number: 11089674
    Abstract: A wiring substrate includes a substrate including conductor layers and core insulating layers, and a laminate including insulating layers and conductor layers such that the conductor layers include first layer including first line pattern. The laminate includes first strip line including the first pattern, a pair of interlayer insulating layers sandwiching the first pattern, and a pair of conductor layers sandwiching the interlayer layers, the conductor layers in the substrate include second layer including second line pattern such that the substrate includes second strip line including the second pattern, a pair of core insulating layers sandwiching the second pattern, and a pair of conductor layers sandwiching the core insulating layers, and the pair of core insulating layers is thicker than the pair of interlayer layers, the second pattern is thicker than the first pattern, and line width of the second pattern is larger than line width of the first pattern.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: August 10, 2021
    Assignee: IBIDEN CO., LTD.
    Inventors: Tomoyuki Ikeda, Shigemitsu Kunikane
  • Patent number: 11089687
    Abstract: A method of manufacturing a power divider circuit includes milling a conductive material disposed upon a first substrate to form a signal trace. The signal trace includes a division from a single trace to two arm traces, with each of the two arm traces having a proximal end electrically connected to the single trace and a distal end electrically connected to each of two secondary traces. The method further includes depositing a resistive ink between the two distal ends to form a resistive electrical connection between the two arm traces, bonding a second substrate to the first substrate to substantially encapsulate the traces between the first substrate and the second substrate, and milling through at least one of the first substrate or the second substrate to provide access to at least one of the traces. A signal divider is further disclosed.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: August 10, 2021
    Assignee: RAYTHEON COMPANY
    Inventors: Jonathan E. Nufio-Molina, Thomas V. Sikina, James E. Benedict, Andrew R. Southworth, Semira M. Azadzoi
  • Patent number: 11089694
    Abstract: A printed wiring board includes a resin insulating layer, a conductor layer formed on a surface of the resin insulating layer, an outermost insulating layer formed on the resin insulating layer such that the outermost insulating layer is covering the conductor layer and has an opening extending to the conductor layer, and a metal post formed in the opening of the outermost insulating layer such that the metal post is protruding from the outermost insulating layer.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: August 10, 2021
    Assignee: IBIDEN CO., LTD.
    Inventor: Masashi Awazu
  • Patent number: 11053602
    Abstract: A micro-roughened electrodeposited copper foil and a copper foil substrate are provided. The micro-roughened electrodeposited copper foil includes a micro-rough surface. The micro-rough surface has a plurality of peaks, a plurality of V-shaped grooves and a plurality of micro-crystal clusters. Each of the V-shaped grooves is defined by adjacent two of the peaks and has an average depth less than 1 ?m. The micro-crystal clusters are correspondingly located on the tops of the peaks and each thereof has an average height less than 1.5 ?m. The micro-rough surface of the micro-roughened electrodeposited copper foil has an Rlr value less than 1.06.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: July 6, 2021
    Assignee: CO-TECH DEVELOPMENT CORP.
    Inventors: Yun-Hsing Sung, Chun-Yu Kao
  • Patent number: 11047061
    Abstract: A micro-roughened electrodeposited copper foil and a copper foil substrate are provided. The micro-roughened electrodeposited copper foil includes a micro-rough surface. The micro-rough surface has a plurality of peaks, a plurality of grooves and a plurality of micro-crystal clusters. Each of the grooves has a U-shaped or V-shaped cross-section profile, and the grooves have an average maximum width between 0.1 ?m and 4 ?m and an average depth less than or equal to 1.5 ?m. Each of the micro-crystal clusters is composed of a plurality of micro-crystals each having an average diameter less than or equal to 0.5 ?m grouped together. The micro-rough surface of the micro-roughened electrodeposited copper foil has an Rlr value less than 1.3. The micro-rough surface has good bonding strength relative to a substrate, and the copper foil substrate has good insertion loss performance to significantly reduce signal loss.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: June 29, 2021
    Assignee: CO-TECH DEVELOPMENT CORP.
    Inventors: Yun-Hsing Sung, Chun-Yu Kao, Zong-Xian Wu
  • Patent number: 11042076
    Abstract: A camera module includes an upper housing coupled to a lower housing to form an inner space, a lens module provided in the inner space and including a heating element, and a substrate configured to supply power to the heating element, wherein the lens module includes an inner barrel comprising one or more lenses, an outer barrel which is coupled to a portion of the inner barrel in an optical axis direction, and a holder in which the outer barrel is fixed, wherein the substrate is fixed to a portion of the holder, wherein the heating element is disposed between the inner barrel and the outer barrel, and is connected to the substrate by a power connection line, and wherein the power connection line is connected to the substrate through a coupling hole in the holder.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: June 22, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Joo Young Ha, Sang Hyo Seo, Dae Seob Kim, Cheong Hee Lee
  • Patent number: 11044802
    Abstract: A circuit board includes a first insulating structure, a first redistribution layer, a second insulating structure, and a second redistribution layer. The first insulating structure has an upper surface and includes a first liquid crystal polymer layer. The first redistribution layer is disposed on the upper surface of the first insulating structure. The second insulating structure is disposed on the upper surface of the first insulating structure and covers the first redistribution layer. The second insulating structure has a top surface opposite to the upper surface and includes a second liquid crystal polymer layer. The second redistribution layer is disposed on the top surface of the second insulating structure.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: June 22, 2021
    Assignees: AZOTEK CO., LTD., Career Technology (MFG.) Co., Ltd
    Inventors: Hung-Jung Lee, Mou-Lin Li
  • Patent number: 11024591
    Abstract: A wireless communication module with improved performance and a mobile object that is equipped with the wireless communication module with the improved performance are provided. The mobile object is equipped with a wireless communication module. The wireless communication module includes a substrate, a first element, and a second element. The substrate includes ground layers. The first element is arranged on the substrate and amplifies an input RF signal. The second element is arranged on the substrate and different from the first element. Each of the ground layers has a groove formed between the first element and the second element.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: June 1, 2021
    Assignee: KYOCERA CORPORATION
    Inventor: Takumi Ogata
  • Patent number: 11024573
    Abstract: A substrate structure, for connecting a semiconductor chip, including a high-density redistribution layer (RDL), a low-density RDL, and a middle-density RDL. The high-density RDL includes a fine conductive pattern. The semiconductor chip is disposed on the high-density RDL. The low-density RDL includes a coarse conductive pattern, and is disposed below the high-density RDL and away from the semiconductor chip. A layout density of the fine conductive pattern is denser than that of the coarse conductive pattern. The middle-density RDL is interposed between and electrically connected between the high-density and low-density RDLs. The middle-density RDL includes a middle dielectric layer, a middle conductive pattern disposed on the middle dielectric layer and close to the high-density RDL, and a middle conductive via penetrating the middle dielectric layer and including a top end connected to the middle conductive pattern and a bottom end protruding from a bottom surface of the middle dielectric layer.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: June 1, 2021
    Inventor: Dyi-Chung Hu
  • Patent number: 11018288
    Abstract: A metal-base substrate includes a metal plate, an adhesive layer; and a film substrate. The adhesive layer is interposed between the metal plate and the film substrate. The film substrate has a wiring layer on a first surface opposite to a second surface on which the adhesive layer is arranged, with a through hole piercing through the film substrate in a thickness direction of the film substrate.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: May 25, 2021
    Assignee: NICHSA CORPORATION
    Inventors: Tomohiro Ikeda, Masaaki Katsumata, Yohei Inayoshi, Yosuke Nakayama, Yumiko Kameshima
  • Patent number: 11013124
    Abstract: According to one aspect of the present invention, a printed circuit board includes: an insulating base film; a conductive pattern that is partially layered on a surface side of the base film; a coating layer that is layered on a surface of a layered structure including the base film and the conductive pattern and having an opening portion that partially exposes the conductive pattern; and a tin plating layer that is layered on a surface of the conductive pattern exposed from the opening portion, wherein an average peel length of the coating layer from the conductive pattern with an inner edge of the opening portion as a base end is less than or equal to 20 ?m.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: May 18, 2021
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Ryuta Ohsuka, Koji Nitta, Shoichiro Sakai, Junichi Okaue
  • Patent number: 11004817
    Abstract: A semiconductor device includes: an integrated circuit having an electrode pad; a first insulating layer disposed on the integrated circuit; a redistribution layer including a plurality of wirings and disposed on the first insulating layer, at least one of the plurality of wirings being electrically coupled to the electrode pad; a second insulating layer having a opening on at least a portion of the plurality of wirings; a metal film disposed on the opening and on the second insulating layer, and electrically coupled to at least one of the plurality of wirings; and a solder bump the solder bump overhanging at least one of the plurality of wirings not electrically coupled to the metal film.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: May 11, 2021
    Assignee: SOCIONEXT INC.
    Inventor: Hirohisa Matsuki
  • Patent number: 10999900
    Abstract: The present invention is one that intends to reduce the number of working processes necessary to provide a secondary conductor on the inner circumferential surface of a roll main body, and an induction heated roll apparatus including: a roll main body that is rotatably supported; and an induction heating mechanism that is provided inside the roll main body and has an induction coil for allowing the roll main body to inductively generate heat. In addition, on the inner circumferential surface of the roll main body, the secondary conductor is formed by build-up welding.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: May 4, 2021
    Assignee: TOKUDEN CO., LTD.
    Inventors: Yoshio Kitano, Osamichi Matsukawa, Toru Tonomura
  • Patent number: 10987764
    Abstract: It is an object of the present invention to provide a flux containing flux components homogeneously dispersed without precipitation of aggregates in addition to having an appropriate balance between fluidity and shape retention property, and a solder paste. A flux comprising 0.5 to 3.5 mass % of a sorbitol-type thixotropic agent selected from the group consisting of dibenzylidene sorbitol, bis(4-methylbenzylidene)sorbitol and a combination thereof, and 2 to 350 mass ppm of a sorbitol-type additive selected from the group consisting of sorbitol, monobenzylidene sorbitol, mono(4-methylbenzylidene)sorbitol and a combination thereof, and a glycol ether-type solvent.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: April 27, 2021
    Assignee: SENJU METAL INDUSTRY CO., LTD.
    Inventors: Hiroyoshi Kawasaki, Masato Shiratori, Ko Inaba, Hiroaki Kawamata, Kazuhiro Minegishi
  • Patent number: 10980127
    Abstract: A method is provided for forming a printed circuit board (PCB) assembly. The method may include drilling a first plurality of vias having a first diameter in a PCB and filling the first plurality of vias to form a first plurality of plated or filled vias. The method may also include drilling a second plurality of vias having a second diameter in the PCB, and filling the second plurality of vias to form a second plurality of plated or filled vias. The first plurality of plated or filled vias is mixed with the second plurality of plated or filled vias such that the spacing between the first plurality of plated or filled vias and the second plurality of plated or filled vias is less than the first diameter and the second diameter.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: April 13, 2021
    Assignee: TTM Technologies Inc.
    Inventors: Michael Len, Chong Mei, Michael Lugert, Raj Kumar
  • Patent number: 10967464
    Abstract: A solder alloy having an alloy composition consisting of, in mass %, Ag: 1% to 4%, Cu: 0.5% to 0.8%, Bi: more than 4.8% and 5.5% or less. Sb: more than 1.5% and 5.5% or less, Ni: 0.01% or more and less than 0.1%, Co: more than 0.001% and 0.1% or less, the balance being Sn. The alloy composition satisfies the following three relationships: 0.020%?Ni+Co?0.105%; 9.1%?Sb+Bi?10.4%; and 4.05×10?3?(Ni+Co)/(Bi+Sb)?1.00×10?2, where Ni, Co, Bi, and Sb each represent a content (mass %) thereof in the solder alloy.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: April 6, 2021
    Assignee: SENJU METAL INDUSTRY CO., LTD.
    Inventors: Naoko Izumita, Shunsaku Yoshikawa, Yoshie Tachibana
  • Patent number: 10964441
    Abstract: Conductive particles, articles including such particles, and methods of making such conductive particles, are provided; wherein the conductive particles include: a core particle including at least one of a glass, a glass-ceramic, or a metal; surface particles adhered to the core particle; and a metal coating disposed on at least a portion of the core and surface particles; wherein the core particle is larger than the surface particles.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: March 30, 2021
    Assignee: 3M Innovative Properties Company
    Inventors: Craig W. Lindsay, Kenton D. Budd, Dipankar Ghosh, Noah O. Shanti
  • Patent number: 10964445
    Abstract: The present disclosure relates to a method for manufacturing a heating element, which includes the steps of: preparing a first bonding film; forming a conductive heating pattern on the first bonding film; and laminating a second bonding film and a transparent substrate on the first bonding film, where the second bonding film is disposed on a surface opposite to the surface provided with the conductive heating pattern of the first bonding film, and the conductive heating pattern is formed by using an adhesive film having an adhesive strength decrement of 30% or greater by an external stimulus based on adhesive strength before the external stimulus.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: March 30, 2021
    Assignee: LG Chem, Ltd.
    Inventors: Ji Eun Myung, Jooyeon Kim, Seung Heon Lee, Jiehyun Seong, Kiseok Lee
  • Patent number: 10937744
    Abstract: A semiconductor package includes a substrate, a semiconductor die, dendrite, and a mold material. The substrate includes a die pad. The die pad includes roughening features. The semiconductor die is attached to the die pad such that the roughening features are adjacent to the semiconductor die. The dendrite is on the roughening features adjacent to the semiconductor die. The mold material encapsulates the semiconductor die, the dendrite, and at least a portion of the substrate.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: March 2, 2021
    Assignee: Infineon Technologies AG
    Inventors: Wern Ken Daryl Wee, Sock Chien Tey, Si Hao Vincent Yeo
  • Patent number: 10930615
    Abstract: Semiconductor device includes: substrate having substrate main surface and substrate rear surface facing opposite sides to each other in first direction, and substrate side surface facing in second direction orthogonal to the first direction; wiring layer having main surface electrode covering a portion of the substrate main surface, and side surface electrode connected to the main surface electrode and covering a portion of the substrate side surface; semiconductor element electrically connected to the main surface electrode and mounted on the substrate to face the substrate main surface; and sealing resin having resin side surface facing in the same direction as the substrate side surface, and covering the semiconductor element and the main surface electrode, wherein the side surface electrode has side exposed surface exposed from the sealing resin and facing in the same direction as the substrate side surface, the side exposed surface being flush with the resin side surface.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: February 23, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Taro Hayashi
  • Patent number: 10923252
    Abstract: A resistor includes materials including copper, nickel, and lanthanum boride. A content of the materials is 40% by mass or more with respect to a total material content of the resistor. The copper includes copper particles having a particle diameter of 2.5 ?m or more. In addition, a circuit board includes a substrate, the resistor on the substrate, a metal layer on the resistor and a glass layer on the resistor. Further, an electronic device includes the circuit board and an electronic component on the metal layer.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: February 16, 2021
    Assignee: KYOCERA Corporation
    Inventors: Shodai Takayoshi, Yoshio Ohashi, Takeyuki Arai
  • Patent number: 10879158
    Abstract: Certain aspects of the present disclosure generally relate to a chip package having a split conductive pad for coupling to a device terminal. An example chip package generally includes a layer, a first plurality of conductive pads disposed on the layer, at least one conductive trace disposed on the layer and between the first plurality of conductive pads, and an electrical component having a first terminal coupled to the first plurality of conductive pads and disposed above the at least one conductive trace.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: December 29, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Aniket Patil, Hong Bok We, Kuiwon Kang, Zhijie Wang
  • Patent number: 10833035
    Abstract: A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toyohiro Aoki, Takashi Hisada, Hiroyuki Mori, Eiji Nakamura, Yasumitsu Orii
  • Patent number: 10834810
    Abstract: A circuit board (10, 10?, 10?) includes at last one insulating substrate layer (SL1, SL2, SL3, SL4, SL5) and a plurality of electrically conductive copper coats (C1, C2, C3) arranged on the at least one insulating substrate layer (SL1, SL2, SL3, SL4, SL5), wherein at least one of the electrically conductive copper coats (C1, C2, C3) is coated at least on both sides with a layer (HSI, HS2, HS3) made of a material for inhibiting electromigration, wherein on a layer (HS1, HS2) made of a material for inhibiting electromigration a further metal layer (M1, M2, M3, M3?) is provided, which is in turn coated with a further layer (HS3, HS3?) made of a material for inhibiting electromigration.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: November 10, 2020
    Assignees: Schweizer Electronic AG, Continental Automotive GmbH
    Inventors: Hubert Trageser, Alexander Neumann
  • Patent number: 10804004
    Abstract: A conducting film of the present invention includes (A) graphene and/or graphene oxide, and/or derivatives thereof, and (B) a compound having a sulfonic acid group, and/or derivatives thereof, and has a volume resistivity of 1×104 ?·cm or less. A method for producing the conducting film of the present invention includes preparing a dispersion by dispersing a component including (A) graphene and/or graphene oxide, and/or derivatives thereof, and (B) a compound having a sulfonic acid group, and/or derivatives thereof in a dispersion medium, applying the dispersion on a substrate and drying it, and performing heat treatment at a temperature of 100° C. or more. Thereby, the present invention provides a conducting film that has high conductivity and can be applied to a wide range of composites including graphenes, and a method for producing the same.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: October 13, 2020
    Assignees: NATIONAL UNIVERSITY CORPORATION NAGOYA UNIVERSITY, FUJI POLYMER INDUSTRIES CO., LTD.
    Inventors: Shigeji Konagaya, Toshio Saruyama, Hitoshi Shibuya
  • Patent number: 10792489
    Abstract: The present invention provides a bio-electrode composition capable of forming a living body contact layer for a bio-electrode that is excellent in conductivity and biocompatibility, is light-weight, can be manufactured at low cost, and can control significant reduction in conductivity even though the bio-electrode is soaked in water or dried. The present invention is accomplished by a bio-electrode composition including an ionic material and a resin, in which the ionic material is a lithium salt, a sodium salt, a potassium salt, a calcium salt, or an ammonium salt of sulphonamide represented by the following general formula (1).
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: October 6, 2020
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Jun Hatakeyama, Takayuki Fujiwara, Motoaki Iwabuchi, Yasuyoshi Kuroda
  • Patent number: 10796928
    Abstract: A wiring structure includes a first unit, a second unit, a first insulation wall, a first redistribution layer and a third unit. The first unit is disposed at a first elevation and having a first circuit layer and a first dielectric layer surrounding the first circuit layer. The second unit is disposed at the first elevation and having a second circuit layer and a second dielectric layer surrounding the second circuit layer. The first insulation wall is disposed between the first unit and the second unit. The first redistribution layer is disposed on the first unit and the second unit, and electrically connected between the first unit and the second unit. The third unit is disposed on the first redistribution layer and having a third circuit layer and a third dielectric layer surrounding the third circuit layer.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: October 6, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Patent number: 10791631
    Abstract: Disclosed is a surface treated copper foil in which the dropping of the roughening particles from the roughening treatment layer provided on the surface of the copper foil is favorably suppressed. Also disclosed is a surface treated copper foil, comprising a copper foil, a roughening treatment layer on one surface, and/or another roughening treatment layer the other surface of the copper foil, wherein a height of roughening particles of the roughening treatment layer is 5 to 1000 nm from the surface, a color difference ?E*ab according to JIS Z 8730 of a surface of a side of the roughening treatment layer is 65 or less, and a glossiness of the TD of the surface of the side of the roughening treatment layer is 70% or less.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: September 29, 2020
    Assignee: JX Nippon Mining & Metals Corporation
    Inventors: Yuki Ori, Hideta Arai, Atsushi Miki, Ryo Fukuchi
  • Patent number: 10784203
    Abstract: In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Hsiu-Jen Lin, Hao-Yi Tsai, Ming Hung Tseng, Tsung-Hsien Chiang, Tin-Hao Kuo, Yen-Liang Lin
  • Patent number: 10765003
    Abstract: A multi-layer circuit board is formed by positioning a top sub having traces on at least one side to one or more pairs of composite layers, each composite layer comprising an interposer layer and a sub layer. Each sub layer which is adjacent to an interposer layer having an interconnection aperture, the interconnection aperture positioned adjacent to interconnections having a plated through via or pad on each corresponding sub layer. Each interposer aperture is filled with a conductive paste, and the stack of top sub and one or more pairs of composite layers are placed into a lamination press, the enclosure evacuated, and an elevated temperature and laminated pressure is applied until the conductive paste has melted, connecting the adjacent interconnections, and the boards are laminated together into completed laminated multi-layer circuit board.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: September 1, 2020
    Assignee: CATLAM, LLC
    Inventors: Kenneth S. Bahl, Konstantine Karavakis
  • Patent number: 10763031
    Abstract: There are provided an inductor and a method of manufacturing the same. The inductor includes: a body including a plurality of coil layers and high-rigidity insulating layers disposed on and beneath the plurality of coil layers; and external electrodes disposed on external surfaces of the body and connected to the coil layers. Build-up insulating layers are disposed between the high-rigidity insulating layers to cover the coil layers, and the high-rigidity insulating layers have a Young's modulus greater than that of the build-up insulating layers.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: September 1, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jong Yoon Jang, Seok Hwan Ahn, Jeong Min Cho, Tae Hoon Kim, Jin Gul Hyun, Se Woong Paeng
  • Patent number: 10756037
    Abstract: A package structure including a semiconductor die, an insulating encapsulant, a redistribution layer and a plurality of conductive terminals is provided. The semiconductor die includes a semiconductor substrate, a plurality of conductive pads and a plurality of conductive strips. The conductive pads are disposed on and connected to the plurality of conductive pads, wherein each of the conductive strips is physically connected to at least two conductive pads. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the insulating encapsulant and the semiconductor die, wherein the redistribution layer is electrically connected to the plurality of conductive strips. The plurality of conductive terminals is disposed on the redistribution layer.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hsien Huang, An-Jhih Su, Der-Chyang Yeh, Hua-Wei Tseng, Yueh-Ting Lin, Ming-Shih Yeh
  • Patent number: 10734248
    Abstract: A printed circuit board according to an embodiment includes: an insulating layer; a first pad disposed on a first surface of the insulating layer; a first conductive layer disposed on the first pad and including gold (Au); a second pad disposed on a second surface of the insulating layer; and a second conductive layer disposed on the second pad and including gold (Au), wherein the first conductive layer is a conductive layer connected to a wire, the second conductive layer is a conductive layer connected to a solder, and the first conductive layer is thicker than the second conductive layer.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: August 4, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Sung Oh Cho, Yoon Tai Kim
  • Patent number: 10721822
    Abstract: There is provided an electric connection member having a substrate, an insulating adhesive layer provided on the substrate, and a conductive interconnect, wherein the electric connection member is provided with a recess that opens at a side of the insulating adhesive layer, the conductive interconnect is disposed in the recess, a metal nano-ink is disposed on the conductive interconnect, and all of the metal nano-ink is contained inside the recess.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: July 21, 2020
    Assignee: JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITED
    Inventors: Junya Sato, Ryosuke Mitsui
  • Patent number: 10712453
    Abstract: A detection element can obtain a high-resolution radiation image having a high signal intensity and a high S/N ratio. A detection element including a substrate having a through hole, an insulating layer arranged inside of the through hole, a through electrode arranged further to the inner side of the through hole than the insulating layer, a resin layer having insulating properties and having an opening portion exposing the through electrode, a first electrode arranged above the through electrode and the resin layer, the first electrode being connected to the through electrode through the opening portion, and a second electrode arranged above the resin layer, the second electrode being separated from the first electrode.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: July 14, 2020
    Assignee: DAI NIPPON PRINTING Co., Ltd.
    Inventors: Kohei Ota, Tomohisa Motomura, Takamasa Takano, Koichi Nakayama
  • Patent number: 10653336
    Abstract: Methods of using subcutaneously implantable sensor devices and associated systems having a communication module that is controlled based upon the detection of a predetermined chemical agent.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Stanley Mo, Alexandra Zafiroglu, Giuseppe Raffa, Joshua Ratcliff, Jose Sia, Adam Jordan
  • Patent number: 10658925
    Abstract: A printed circuit board (1) for converting an input phase to at least one output phase (U,V,W), which has an input phase surface area with at least one conductive DC+ layer (28) and one conductive DC? layer (29) for each conductive DC+ layer (28), for conducting the input phase. There is at least one high-side power semiconductor (6) for each output phase (U, V, W) and one low-side power semiconductor (7) for each high-side power semiconductor (6), for switching the input phase. The at least one DC+ layer (28) corresponding to a respective DC? layer (29) is formed in a cover surface area (2), which covers at least 75% of the input phase surface area.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 19, 2020
    Assignee: ZF FRIEDRICHSHAFEN AG
    Inventors: Wilfried Lassmann, Jörg Kűhnl
  • Patent number: 10642429
    Abstract: The present disclosure provides a touch component, a method for manufacturing the touch component and a touch screen. The touch component includes a first metal mesh layer and a second metal mesh layer which are opposite to each other, the first metal mesh layer including a plurality of first touch channel areas, the first virtual wiring area including a plurality of first virtual wiring openings, the second metal mesh layer including a plurality of second touch channel areas and a plurality of second virtual wiring areas, the second virtual wiring area including a plurality of second virtual wiring openings. A projection of at least part of the first virtual wiring opening on the second metal mesh layer intersects with a grid line of the second metal mesh layer.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: May 5, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventors: Jiawei Xu, Qicheng Chen, Jun Li, Lei Zhang, Tsung Chieh Kuo
  • Patent number: 10639134
    Abstract: Methods and apparatuses for monitoring either or both the performance of an orthodontic appliance for repositioning a patient's teeth and/or the user compliance in wearing the appliance using a biosensor. The apparatuses described herein may include one or more sensors, including biosensors, electrical sensors, or both, configured to generate sensor data related to user compliance and/or repositioning of the patient's teeth by an orthodontic appliance.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: May 5, 2020
    Assignee: Align Technology, Inc.
    Inventors: Yaser Shanjani, Bruce Cam, John Y. Morton, Jun Sato
  • Patent number: 10619262
    Abstract: Electrodeposited copper foils having properties suitable for use as current collectors in lithium-ion secondary batteries are disclosed. The electrodeposited copper foils include a drum side and a deposited side. At least one of the deposited side or the drum side has a root mean square slope (R?q) in the range of about 0.03 to about 0.23. In this manner, the copper foil has good durability and workability, as well as good performance as current collectors in lithium-ion secondary batteries.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: April 14, 2020
    Assignee: CHANG CHUN PETROCHEMICAL CO., LTD.
    Inventors: Huei-Fang Huang, Yao-Sheng Lai, Jui-Chang Chou
  • Patent number: 10607848
    Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed on the substrate. A first passivation material layer is formed on sidewalls of the opening and on the substrate. A treatment process is performed to the first passivation material layer to form a second passivation material layer. A first surface of the second passivation material layer and a second surface (at an inner side) of the second passivation material layer are differ in a property, and the first surface is located at a side of the second passivation material layer relatively away from the material layer.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: March 31, 2020
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Yuan-Chieh Chiu, Shih-Ping Hong, Kuang-Chao Chen, Yen-Ju Chen
  • Patent number: 10609823
    Abstract: A method for manufacturing a multilayer wiring board includes a step (1) and a step (2). The step (1) disposes a hole for through-hole, a squirt of metal foils, and a lower space. The squirt of the metal foils on both the sides of the insulating layer is formed at an opening of the hole for through-hole. The lower space is formed between the squirt of the metal foils and an inner wall of the hole for through-hole. The step (2) plugs up the hole for through-hole by forming an electrolytic filled plating layer at an inside of the hole for through-hole and on the metal foils on both the sides of the insulating layer. The plugging of the hole for through-hole in the step (2) is performed by once decreasing a current density of an electrolytic filled plating in a middle of the electrolytic filled plating and then increasing the current density again.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: March 31, 2020
    Assignee: HITACHI CHEMICAL COMPANY, LTD.
    Inventor: Nobuyuki Yoshida
  • Patent number: 10602621
    Abstract: A method of manufacturing a circuit board includes: providing a substrate including a bottom layer and a resin layer over the bottom layer, the resin layer including a first surface in contact with the bottom layer and a second surface opposite to the first surface; forming a plurality of vias through the resin layer; depositing a first metal layer in the vias, the first metal layer filling a portion of each of the vias; depositing a second metal layer over the first metal layer and in the vias; forming a patterned metal layer over the second metal layer and extending from each of the vias to a position over the second surface; separating the bottom layer and the resin layer; and removing a portion of the resin layer from the first surface, so that the first metal layer protrudes from the resin layer.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: March 24, 2020
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventor: Hsin-Chi Hu
  • Patent number: 10601158
    Abstract: There is a problem that an oxide film or high resistance abrasion powder is formed at the contact interface due to micro sliding abrasion in a high temperature environment or temperature cycle to increase the contact resistance at the contact portion of a non-noble metal connection terminal. Provided is an in-vehicle electronic module, a connector, and a connection structure thereof, which have the same connection reliability as noble metals even when exposed to a harsh environment and can reduce cost of members.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: March 24, 2020
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Ryouichi Kajiwara, Toshiaki Ishii, Masaru Kamoshida