Conducting (e.g., Ink) Patents (Class 174/257)
  • Patent number: 10356900
    Abstract: A circuit board, a display device including the same, and a method of manufacturing a circuit board are provided. A circuit board includes a base substrate, a wiring line provided on the base substrate, a passivation layer provided on the wiring line, an elastic bump provided on the passivation layer, and a conductive layer provided on the elastic bump. The passivation layer includes a first opening and a second opening that expose a partial region of the wiring line, and the second opening is arranged in a region adjacent to the first opening.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: July 16, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jung Yun Jo, Jeong Do Yang
  • Patent number: 10356898
    Abstract: Provided herein is a carrier-attached copper foil having desirable fine circuit formability. The carrier-attached copper foil includes a carrier, an interlayer, and an ultrathin copper layer in this order. The maximum ridge height Sp as measured with a laser microscope according to ISO 25178 on the surface of the carrier-attached copper foil on the side of the ultrathin copper layer is 0.193 to 3.082 ?m.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: July 16, 2019
    Assignee: JX Nippon Mining & Metals Corporation
    Inventor: Nobuaki Miyamoto
  • Patent number: 10350872
    Abstract: The present invention is to provide an anisotropic conductive film that excels in dispersing conductive particles and trapping the particles, and maintains conduction reliability even between narrow-pitched terminals. By a method for manufacturing an anisotropic conductive film containing conductive particles, the conductive particles are buried in grooves in a sheet having the grooves regularly formed in the same direction, the conductive particles are arranged, a first resin film having a thermo-setting resin layer formed on a stretchable base film is laminated on the surface of the sheet on the side of the grooves to transfer and attach the conductive particles to the first resin film, the first resin film is uniaxially stretched in a direction other than the direction perpendicular to the array direction of the conductive particles, and a second resin film is laminated.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: July 16, 2019
    Assignee: DEXERIALS CORPORATION
    Inventor: Tomoyuki Ishimatsu
  • Patent number: 10349518
    Abstract: A method of manufacturing an embedded circuit board includes: a first adhesive coated copper is provided, which includes a first copper layer pre-formed with at least two first positioning holes and a first adhesive layer formed on a surface of the first copper layer; at least one first electronic element are adhered to the first adhesive layer, electrodes of the first electronic element face their corresponding first positioning hole; a second adhesive coated copper and a semi-cured film are provided, the first adhesive coated copper and the second adhesive coated copper are pressed on opposite surfaces of the semi-cured film, thereby embedding the first electronic elements in the semi-cured film; the first adhesive layer is partially removed to define first holes for exposing electrodes of the first electronic element; the electrodes are electrically connected with the first copper layer. A circuit board made by the method is also provided.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 9, 2019
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventors: Han-Pei Huang, Yong-Chao Wei
  • Patent number: 10346561
    Abstract: A computer-implemented method for determining a system layout of a photovoltaic (PV) system is implemented by a design automation computer system in communication with a memory. The method includes receiving a first selection of a system table, receiving a layout mode designation, identifying a system orientation, identifying a system spacing, receiving a layout detail designation, and applying a layout algorithm based on the first selection of a system table, the layout mode designation, the layout mode designation, the system orientation, the system spacing and the layout detail designation.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: July 9, 2019
    Assignee: FTC Solar, Inc.
    Inventors: Andrew Joseph Morse, Nagendra Srinivas Cherukupalli, Ravi Ranganathan, Krishnan Ramagopal
  • Patent number: 10349520
    Abstract: A multi-layer circuit board is formed by positioning a top sub having traces on at least one side to one or more pairs of composite layers, each composite layer comprising an interposer layer and a sub layer. Each sub layer which is adjacent to an interposer layer having an interconnection aperture, the interconnection aperture positioned adjacent to interconnections having a plated through via or pad on each corresponding sub layer. Each interposer aperture is filled with a conductive paste, and the stack of top sub and one or more pairs of composite layers are placed into a lamination press, the enclosure evacuated, and an elevated temperature and laminated pressure is applied until the conductive paste has melted, connecting the adjacent interconnections, and the boards are laminated together into completed laminated multi-layer circuit board.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: July 9, 2019
    Assignee: CATLAM, LLC
    Inventors: Konstantine Karavakis, Kenneth S. Bahl
  • Patent number: 10347628
    Abstract: Forming a semiconductor layer on a semiconductor substrate, a top surface of the semiconductor layer above a fin in a second region is higher than a top surface of the semiconductor layer in a first region, etching the semiconductor layer and a mask in the first region to expose a top surface of the semiconductor substrate to form a first stack, and etching the semiconductor layer and the mask in the second region to expose a top surface of the fin to form a second stack, epitaxially growing a semiconductor material on a top surface of the fin not covered by the second stack, recessing the first and second stack to expose a top surface of the semiconductor layer, a portion of the mask remains above the semiconductor layer in the first stack, top surfaces of each of the first and second stacks each are substantially flush with one another.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Charan V. V. S. Surisetty
  • Patent number: 10342135
    Abstract: Disclosed herein are a printed circuit board, a manufacturing method thereof, and a semiconductor package including the printed circuit board. The printed circuit board includes a base substrate including a plurality of circuit patterns, a cavity formed above the base substrate, a pad embedded in the base substrate and being exposed through the substrate bottom surface of the cavity, and an electronic component mounted in the cavity and electrically connected to the pad. According to the present invention, a cavity having a predetermined depth is formed in a base substrate of a printed circuit board so as to mount an electronic component therein, such that a gap between an upper semiconductor package and a lower semiconductor package may be obtained even if pitches between the balls are decreased for high density and high performance of the upper semiconductor package in the manufacturing of a semiconductor package having a PoP structure.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: July 2, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seong Ryul Choi, Suk Chang Hong, Sang Kab Park, Kwang Seop Youm
  • Patent number: 10325843
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: June 18, 2019
    Assignee: INTEL CORPORATION
    Inventors: Qinglei Zhang, Stefanie M. Lotz
  • Patent number: 10319651
    Abstract: The present disclosure provides a shorting bar structure and a method for manufacturing the same, and a Thin Film Transistor (TFT) substrate. The shorting bar structure comprises: a test wire; a test probe contact part connected to the test wire and configured to be able to contact with a test probe; and at least one PN junction structure located between the test wire and at least one wire under test, and configured to allow a test signal to be unidirectionally transmittable in a direction from the test wire to the wire under test.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: June 11, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yong Wang, Jaeyoung Joo, Hongyan Guo, Yang Yu, Cheong Yo Seop, Zongtian Xie, Zengyang Jiang, Cundui Tang, Huailiang Wu
  • Patent number: 10314020
    Abstract: According to certain embodiments, a method by a wireless device is provided for transmitting uplink control information (UCI) on a serving cell on the unlicensed spectrum. The method includes formatting the UCI as a shortened control signalling transmission and transmitting the UCI formatted as the shortened control signalling transmission to a network node. The shortened control signalling transmission is transmitted during a transmission opportunity on the serving cell on the unlicensed spectrum without performing channel sensing.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: June 4, 2019
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Yu Yang, Daniel Larsson
  • Patent number: 10306771
    Abstract: An anisotropic conductive film including conductive particles arranged uniformly in a single layer and capable of supporting fine-pitch connection is produced by: drying a coating film of a particle dispersion in which conductive particles are dispersed in a dilute solution of a thermoplastic resin that forms a coating after drying, whereby a conductive particle-containing layer is formed in which the coated conductive particles coated with the dried coating of the dilute solution of the thermoplastic resin and arranged in a single layer stick to the dried coating film; and laminating an insulating resin layer onto the conductive particle-containing layer.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: May 28, 2019
    Assignee: DEXERIALS CORPORATION
    Inventor: Kouichi Sato
  • Patent number: 10301443
    Abstract: Composite material, where the matrix material and the additive are held together by covalently or non-covalently bound ligands. The linker unit between matrix and additive has the structure Ligand1-LinkerL-Ligand 2, wherein Ligand1 and Ligand2 are a bond or a chemical entity that is capable of binding covalently or non-covalently to a structural entity, such as a polymer matrix or the additive (ex. CNT, graphene, carbon nanofiber, etc), and LinkerL is a chemical bond or entity that links Ligand1 and Ligand2.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: May 28, 2019
    Assignee: NANOCORE APS
    Inventors: Mikkel Dybro Lundorf, Henrik Pedersen, Tore Dehli
  • Patent number: 10297521
    Abstract: A circuit substrate is provided with a base formed of ceramics. It includes a first face a second face; and a through hole penetrating from the first face to the second face; a through conductor: containing silver and copper as main components; disposed inside the through hole; and including a plurality of surfaces; and a metal layer in contact with at least one of the plurality of surfaces. The through conductor includes a eutectic region of silver and copper, disposed in a metal layer side of a diametrically center region of the through conductor; and a non-eutectic region of silver and copper, disposed in a central region of the diametrically center region of the through conductor.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: May 21, 2019
    Assignee: KYOCERA CORPORATION
    Inventor: Yuuichi Abe
  • Patent number: 10269688
    Abstract: A semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: April 23, 2019
    Assignee: General Electric Company
    Inventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Shakti Singh Chauhan
  • Patent number: 10257923
    Abstract: A resin substrate includes a first portion including a plurality of resin sheets provided at one end in a stacking direction and a second portion including a plurality of resin sheets provided at the other end in the stacking direction. The thickness of the plurality of resin sheets is the same or substantially the same as the thickness of the first portion and the second portion. The density of planar conductor patterns of the first portion with respect to the volume of the first portion is lower than the density of planar conductor patterns of the second portion with respect to the volume of the second portion. The average of the diameters of the first interlayer connection conductor provided in the first portion is greater than the average of the diameters of the second interlayer connection conductor provided in the second portion.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: April 9, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Toshiro Adachi
  • Patent number: 10251264
    Abstract: A membrane circuit structure with function expandability is provided. The membrane circuit structure includes a substrate, a lower circuit layer and a covering layer. The substrate includes a first region and at least one second region. The at least one second region is arranged near the first region. The lower circuit layer is printed on the first region. The lower circuit layer is made of a first conductive material. The covering layer is electroplated on a portion of a surface of the lower circuit layer. The covering layer is made of a second conductive material. At least one expansion line is welded on the corresponding second region, and electrically connected with the covering layer and a corresponding function-expanding unit.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: April 2, 2019
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Bo-An Chen, Hsien-Tsan Chang
  • Patent number: 10244639
    Abstract: A stacked mounting structure and a method of manufacturing stacked mounting structure are provided. The stacked mounting structure includes a plurality of members provided with a mounting area which is necessary for installing and operating components to be mounted on at least one principal surface, and an area for connections for signal transfer for operating the components to be mounted, and an electroconductive member which is disposed on the area for connections between the mutually facing members, and a cross section of the electroconductive member is same as or smaller than the area for connections, and an end portion of the electroconductive member is extended from a principal surface of one member up to a principal surface of the other member, and a height of the electroconductive member regulates a distance of the mounting area.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: March 26, 2019
    Assignee: OLYMPUS CORPORATION
    Inventors: Mikio Nakamura, Yu Kondo
  • Patent number: 10233365
    Abstract: A composition for a bond ply, and a circuit subassembly that comprises such bond ply, are disclosed. The circuit subassembly can have a UL-94 rating of V-0. The composition of the bond ply layer comprises 25 to 45 volume percent of liquid resin; 10 to 40 weight percent of a bromine-containing or phosphorus-containing aromatic compound having a peak melting point of at least about 260° C.; and 5 to 35 volume percent inorganic filler.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: March 19, 2019
    Assignee: ROGERS CORPORATION
    Inventor: William F. Scholz
  • Patent number: 10224284
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a soluble self-aligned barrier first for interconnect structure and methods of manufacture. The structure includes: a self-aligning barrier layer lining a trench of an interconnect structure; and an alloy interconnect material over the self-aligned barrier layer. The alloy interconnect material is an alloy composed of metal interconnect material and pre-anneal material that also forms the self-aligning barrier layer.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: March 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Christian A. Witt
  • Patent number: 10225925
    Abstract: A radio frequency transmission structure couples a RF signal between a first and a second radiating elements arranged at a first and a second sides of a first dielectric substrate, respectively. The RF coupling structure comprises first and second coupling structures. Each coupling structure has a hole arranged through the first dielectric substrate, a first electrically conductive layer arranged on a first wall of the hole to electrically connect a first and a second signal terminals, a second electrically conductive layer arranged on a second wall of the hole opposite to the first wall to electrically connect a first and a second reference terminals. The first electrically conductive layer is separated from the second electrically conductive layer. The first and second coupling structures are symmetrically arranged with the first electrically conductive layers closer to each other than the second electrically conductive layers are to each other.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: March 5, 2019
    Assignee: NXP USA, Inc.
    Inventors: Li Qiang, Ralf Reuter, Bernhard Grote, Ljubo Radic, Ziqiang Tong
  • Patent number: 10225929
    Abstract: A ceramic circuit board includes an insulating substrate composed of stacked insulating layers of an alumina-based sintered body, internal leads containing Cu embedded in the insulating substrate, and one or a plurality of metal layers containing Cu embedded in the insulating substrate, at least one of the metal layers being located nearer than the internal leads to the surface of the insulating substrate in the stacking direction, wherein at least part of the metal layer overlaps the internal leads in plan view.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: March 5, 2019
    Assignee: Kyocera Corporation
    Inventor: Takafumi Kamei
  • Patent number: 10215726
    Abstract: A sensor element for detecting a level of a gas component in the measured gas or a temperature of the measured gas. The sensor element includes at least one solid electrolyte layer. The solid electrolyte layer has at least one plated-through hole. The sensor element further includes a conductive element, which produces an electrically conductive connection through the plated-through hole. In the plated-through hole, the solid electrolyte layer is electrically insulated from the conductive element by an insulating element. At least one opening region of the plated-through hole is stabilized against phase transition by a stabilizing element. The stabilizing element is made at least partially of a material, which includes a noble metal and an element selected from the group consisting of: V, Nb, Ta, Sb, Bi, Cr, Mo, W. A method for manufacturing the sensor element is also provided.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: February 26, 2019
    Assignee: ROBERT BOSCH GMBH
    Inventors: Alexander Bischoff, Andreas Rottmann, Antje Taeuber, Frank Buse, Jens Schneider, Oliver Dotterweich, Peter Alt, Thomas Juestel
  • Patent number: 10216340
    Abstract: One embodiment of the present invention provides a touch detection device comprising: a plurality of sensor pads disposed to form a plurality of rows and columns and forming a touch capacitance with a touch input tool; and a plurality of signal wirings for respectively connecting the plurality of sensor pads to a driving device, wherein at least one side of each of the plurality of sensor pads and at least one of the plurality of signal wirings include a plurality of segments forming an acute angle with a straight line parallel to the column direction.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: February 26, 2019
    Assignee: CRUCIALTEC CO., LTD.
    Inventors: Ick Chan Jeong, Jun Yun Kim
  • Patent number: 10217807
    Abstract: An anisotropic conductive film includes a conductive layer; a first resin insulating layer over a first surface of the conductive layer; and a second resin insulating layer over a second surface of the conductive layer, wherein the conductive layer comprises a plurality of conductive particles and a nano fiber connecting the plurality of conductive particles to each other, each of the plurality of conductive particles comprising a plurality of needle-shaped protrusions having a conical shape, and wherein the first resin insulating layer and the second resin insulating layer comprise a same material and have different thicknesses.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: February 26, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Chungseok Lee, Donghee Park, Cheolgeun An, Jihoon Oh, Euiyun Jang, Jeongho Hwang
  • Patent number: 10203819
    Abstract: A touch screen, a fabrication method thereof and a display device are provided. The method comprises: forming a touch electrode on a light emission side of a display panel after the display panel is formed; and forming an organic transparent insulation layer on the light emission side of the display panel where the touch electrode has been formed. An absolute value of a difference between a refractive index of the organic transparent insulation layer and a refractive index of the touch electrode is less than or equal to a predetermined value.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: February 12, 2019
    Assignees: BOE Technology Group Co., Ltd., Hefei BOE Optoelectronics Technology Co., Ltd.
    Inventors: Tianzhen Liu, Gaofei Shi, Chengcheng Wang
  • Patent number: 10187984
    Abstract: A circuit board film-plated against corrosion of conductive traces comprises a substrate, at least one conductive circuit layer attached to the substrate, at least one plating film attached to a surface of the conductive circuit layer away from the substrate, and a covering film. Each of the at least one plating film comprises a surface away from the conductive circuit layer, and at least one side surface. The circuit board defines at least one through hole. Each of the at least one through hole passes through substrate, conductive circuit layer, and the plating film. The covering film covers the conductive circuit layer, the side surface of the plating film, and the through hole. The film-covered conductive circuit layer and the film-covered side surface of the plating film cannot be corroded. A method for making the circuit board is also provided.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: January 22, 2019
    Assignees: Avary Holding (Shenzhen) Co., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co
    Inventors: Ning Hou, Si-Hong He, Biao Li, Mei-Hua Huang
  • Patent number: 10179953
    Abstract: Selective electropolymerization of conducting polymers using a hydrogel stamp is disclosed. The ability of this simple method to generate patterned films of conducting polymers with multiple surface chemistries in a single-step process and to incorporate biomolecules in these films is further described.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: January 15, 2019
    Assignee: The Penn State Research Foundation
    Inventors: Sheereen Majd, Mohammad Reza Abidian, Soohyun Park
  • Patent number: 10170410
    Abstract: A semiconductor package includes a frame having a through hole, an electronic component disposed in the through hole, a metal layer disposed on either one or both of an inner surface of the frame and an upper surface of the electronic component, a redistribution portion disposed below the frame and the electronic component, and a conductive layer connected to the metal layer.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: January 1, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Tae Hyun Kim, Thomas A. Kim, Kyu Bum Han, Tae Hoon Kim
  • Patent number: 10163844
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate including a plurality of conductive traces and a recess filled with a conductive material electrically coupled to at least one of the plurality of conductive traces. The semiconductor structure also includes semiconductor chip. The semiconductor chip includes a plurality of conductive pads correspondingly electrically connected with the plurality of conductive traces through a plurality of conductive bumps. A height of each of the plurality of conductive bumps is determined by a minimum distance between the plurality of conductive pads and the corresponding conductive traces thereof.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yen-Liang Lin, Tin-Hao Kuo, Sheng-Yu Wu, Chen-Shien Chen
  • Patent number: 10160869
    Abstract: A conductive composition that comprises a branched metal carboxylate and one or more solvents. The solvents may be an aromatic hydrocarbon solvent. In embodiments, the branched metal carboxylate is a silver carboxylate. The conductive composition may be used in forming conductive features on a substrate, including by inkjet printing, screen printing or offset printing.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: December 25, 2018
    Assignee: XEROX CORPORATION
    Inventors: Yiliang Wu, Ping Liu
  • Patent number: 10159149
    Abstract: A composite circuit board includes an insulation layer, an inner circuit layer, a first conductive layer and a second conductive layer embedded in the insulation layer, a third conductive layer and a fourth conductive layer formed on opposite surfaces of the insulation layer. The third conductive layer electrically connects with the first conductive layer. The fourth conductive layer electrically connects with the second conductive layer. The inner circuit layer is in a middle portion of the insulation layer. The first conductive layer and the second conductive layer respectively forms on opposite sides of the inner circuit layer. The insulation layer forms a plurality of first through holes between the first conductive layer and the inner circuit layer, a plurality of second through holes between the second conductive layer and the inner circuit layer.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: December 18, 2018
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co, Avary Holding (Shenzhen) Co., Limited.
    Inventors: Xian-Qin Hu, Mei Yang, Cheng-Jia Li
  • Patent number: 10141668
    Abstract: Printed flexible hybrid electronic systems may require electrical interconnection to peripheral elements. For example, a printed sensor tag with wireless communication may need to connect to a printed sensing electrode on a separated substrate. Frequently, it is desired that these interconnections be detachable in order to replace peripheral elements or to facilitate low cost and simplified assembly, test, rework, and repair. Unlike conventional printed circuit board, mounting a connector on a flexible substrate for detachable connection is challenging due to low temperature requirements. Provide is a teaching of a thin film or form of electrical connection for two circuit elements on separate flexible substrates. The connection is detachable and re-attachable for replacing different circuit elements. The detachable connection is in embodiments realized by selective deposition of fine patterns of conductive materials and non-conductive repositionable pressure-sensitive adhesive.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: November 27, 2018
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Ping Mei, David Eric Schwartz, Brent S. Krusor
  • Patent number: 10141090
    Abstract: A resin composition which includes (A) an epoxy resin, (B) a curing agent, and (C) carbon nanotubes, wherein the carbon nanotubes contain therein semiconducting single-walled carbon nanotubes in an amount of 70% by weight or more. A cured product of a paste made from the resin composition can be used to form a varistor element.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: November 27, 2018
    Assignee: NAMICS CORPORATION
    Inventors: Yoshitaka Kamata, Pawel Czubarow, Toshiyuki Sato, Takayuki Fujita
  • Patent number: 10141250
    Abstract: A chip includes a substrate and a die that are wrapped together by means of a packaging process. Multiple substrate cables corresponding to attachment points are laid out in the substrate. Solder joints in a solder joint matrix at a bottom of the substrate include a first solder joint group and a second solder joint group that are arranged along two parallel lines. Substrate cables connected to solder joints in the first solder joint group have an equal length. Substrate cables connected to solder joints in the second solder joint group have an equal length.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: November 27, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yuchen Xin, Nan Zhao, Chen Wang
  • Patent number: 10128175
    Abstract: Packaging methods and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging semiconductor devices includes forming first contact pads on a carrier, forming a wiring structure over the first contact pads, and forming second contact pads over the wiring structure. A first packaged semiconductor device is coupled to a first set of the second contact pads, and a second packaged semiconductor device is coupled to a second set of the second contact pads. The carrier is removed. The second packaged semiconductor device comprises a different package type than the first packaged semiconductor device.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: November 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jing-Cheng Lin, Jui-Pin Hung
  • Patent number: 10129980
    Abstract: A circuit board includes an insulating layer having a protrusion on a surface, and a connection pad formed on an upper surface of the protrusion. A peripheral portion of a lower surface of the connection pad is exposed from the protrusion.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: November 13, 2018
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Shoji Watanabe
  • Patent number: 10123420
    Abstract: A coil electronic component includes: a magnetic body including first and second coil parts spaced apart from each other, wherein the coil parts each include first and second coil conductors respectively disposed on first and second surfaces of a substrate, and a non-magnetic film disposed between the first and second coil parts.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: November 6, 2018
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Hae Jong Lee
  • Patent number: 10115692
    Abstract: A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: October 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Toyohiro Aoki, Takashi Hisada, Hiroyuki Mori, Eiji Nakamura, Yasumitsu Orii
  • Patent number: 10109571
    Abstract: A wiring substrate includes a laminated sheet including a first conductor pattern, an inorganic dielectric layer, and a second conductor pattern. The first conductor pattern, the inorganic dielectric layer, and the second conductor pattern are laminated in this order. Also, the first conductor pattern is divided into a plurality of regions.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: October 23, 2018
    Assignees: FUJITSU LIMITED, SONY CORPORATION
    Inventors: Kei Fukui, Kazuya Arai, Koji Komemura, Kazuhiko Iijima, Kenichiro Abe, Shinji Rokuhara, Shuichi Oka
  • Patent number: 10076032
    Abstract: A substrate for a printed circuit board includes a base film having an insulating property; a first conductive layer formed on at least one of surfaces of the base film by application of a conductive ink containing metal particles; and a second conductive layer formed, by plating, on a surface of the first conductive layer, the surface being on a side opposite to the base film, wherein a region near an interface between the base film and the first conductive layer contains a metal oxide species based on a metal of the metal particles and a metal hydroxide species based on the metal of the metal particles, the metal oxide species in the region near the interface between the base film and the first conductive layer has a mass per unit area of 0.1 ?g/cm2 or more and 10 ?g/cm2 or less, and a mass ratio of the metal oxide species to the metal hydroxide species is 0.1 or more.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: September 11, 2018
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Takashi Kasuga, Yoshio Oka, Shigeyoshi Nakayama, Jinjoo Park, Sumito Uehara, Kousuke Miura, Hiroshi Ueda
  • Patent number: 10068882
    Abstract: A high-frequency module includes a wiring substrate, a high-frequency circuit including circuit components disposed on the upper surface of the wiring substrate, a post made of metal and disposed on the upper surface of the wiring substrate, a sealing resin covering the circuit components, and an antenna substrate disposed on the upper surface of the sealing resin and having an antenna formed by a metal pattern. A groove is provided on the sealing resin, at least a part of the post is exposed from the groove, a central surface and two opposing side wall surfaces located higher than the central surface are formed at the upper side of the post, and a conductive adhesive is bonded to the central surface, the two side wall surfaces, and the antenna.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: September 4, 2018
    Assignee: ALPS ELECTRIC CO., LTD.
    Inventors: Masashi Nakagawa, Shoji Kai, Hideki Watanabe, Yoshihisa Shibuya, Shunji Kuwana
  • Patent number: 10068854
    Abstract: A semiconductor package device includes a substrate, a passive component, an active component and a package body. The passive component is disposed on the substrate. The active component is disposed on the substrate. The package body is disposed on the substrate. The package body includes a first portion covering the active component and the passive component, and a second portion covering the passive component. A top surface of the second portion of the package body is higher than a top surface of the first portion of the package body.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: September 4, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Hsuan Lee, Jaw-Ming Ding, Wei-Yu Chen
  • Patent number: 10070521
    Abstract: This surface-treated copper foil is characterized in that the amount of adhesion of Si on the copper foil surface is from 3.1 to 300 ?g/dm2, and the amount of adhesion of N on the copper foil surface is from 2.5 to 690 ?g/dm2. The objective of the present invention is to obtain a copper foil having improved peel strength in providing a copper foil for a flexible printed substrate (FPC), in which a copper foil is laminated to a liquid crystal polymer (LCP) suitable for high-frequency applications.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: September 4, 2018
    Assignee: JX Nippon Mining & Metals Corporation
    Inventor: Ryo Fukuchi
  • Patent number: 10064283
    Abstract: A method for forming a film on a conductive substrate, comprising immersing a substrate having a conductive portion in a solution comprising a metal ion ceramic precursor for the film and a peroxide; applying a voltage potential to the conductive portion with respect to a counter electrode in the solution, sufficient to protect the conductive portion from corrosion by the solution, and drive formation of a film on the substrate, controlling a pH of the solution while limiting a production of hydrogen by electrolysis of the solution proximate to the conductive portion; and maintaining the voltage potential for a sufficient duration to produce a film on the conductive portion. An electrode may be formed over the film to produce an electrical device. The film may be, for example, insulating, dielectric, resistive, semiconductive, magnetic, or ferromagnetic.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: August 28, 2018
    Assignee: The Research Foundation for the State University of New York
    Inventors: Junghyun Cho, Bahgat Sammakia, Mark D. Poliks, Roy Magnuson, Biplab Kumar Roy
  • Patent number: 10062473
    Abstract: A silver-coated copper alloy powder, which has a low volume resistivity and excellent storage stability (reliability), is produced by coating a copper alloy powder, which has a chemical composition comprising 1 to 50 wt % of at least one of nickel and zinc and the balance being copper and unavoidable impurities (preferably a copper alloy powder wherein a particle diameter (D50 diameter) corresponding to 50% of accumulation in cumulative distribution of the copper alloy powder, which is measured by a laser diffraction particle size analyzer, is 0.1 to 15 ?m), with 7 to 50 wt % of a silver containing layer, preferably a layer of silver or an silver compound.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: August 28, 2018
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Kenichi Inoue, Kozo Ogi, Atsushi Ebara, Yuto Hiyama, Takahiro Yamada, Toshihiko Ueyama
  • Patent number: 10059848
    Abstract: In this invention, processes which can be used to achieve stable doped carbon nanotubes are disclosed. Preferred CNT structures and morphologies for achieving maximum doping effects are also described. Dopant formulations and methods for achieving doping of a broad distribution of tube types are also described.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: August 28, 2018
    Assignee: Battelle Memorial Institute
    Inventors: Amy M. Heintz, Steven Risser, Joel D. Elhard, Bryon P. Moore, Tao Liu, Bhima R. Vijayendran
  • Patent number: 10038109
    Abstract: Solar cell conductor formulations made are from two silver powders having different particle size distributions, an aluminum powder, and two frit glass compositions having softening points in the range of 250-700° C. and whose softening points differ by at least 10° C.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: July 31, 2018
    Assignee: Heraeus Precious Metals North America Conshohocken LLC
    Inventors: Shahram Seyedmohammadi, Himal Khatri, Srinivasan Sridharan, Aziz S. Shaikh
  • Patent number: 10014274
    Abstract: A multi-chip system includes a top chip stack element comprising a top chip having two major surfaces and top solder pads arrayed along a plane of one of the major surfaces; a bottom chip stack element comprising a bottom substrate having two major surfaces and bottom solder pads arrayed along a plane of one of the major surfaces; one or more solder reservoir pads connected to one or more of the top solder pads or of the bottom solder pads; and solder material; and wherein at least one of the top solder pads is connected to one of the bottom solder pads by one of the solder material.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: July 3, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tymon Barwicz, Yves Martin, Jae-Woong Nah
  • Patent number: 10014246
    Abstract: A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: July 3, 2018
    Assignee: VIA Technologies, Inc.
    Inventor: Chen-Yueh Kung