Abstract: A method of forming a semiconductor package. Implementations include forming on a die backside an intermediate metal layer having multiple sublayers, each including a metal selected from the group consisting of titanium, nickel, copper, silver, and combinations thereof. A tin layer is deposited onto the intermediate metal layer and is then reflowed with a silver layer of a substrate to form an intermetallic layer having a melting temperature above 260 degrees Celsius and including an intermetallic consisting of silver and tin and/or an intermetallic consisting of copper and tin. Another method of forming a semiconductor package includes forming a bump on each of a plurality of exposed pads of a top side of a die, each exposed pad surrounded by a passivation layer, each bump including an intermediate metal layer as described above and a tin layer coupled to the intermediate metal layer is reflowed to form an intermetallic layer.

Abstract: A microphone assembly for exterior use on vehicles having a housing base including at least one compartment, a PCBA (printed circuit board assembly) with at least one acoustic membrane, a sealing cover to at least partially overlap with the compartment is disclosed. The sealing cover has at least one opening with said opening at least partially aligned with said acoustic membrane. The assembly has a housing cover including a first grid at least partially aligned with said opening in the sealing cover, and a shielding cover. The shielding cover has a second grid at least partially aligned with said opening in the sealing cover. The first grid and the second grid are aligned in offset in order to provide a labyrinth path without straight passthrough passages from the exterior of the microphone assembly to the acoustic membrane.

Abstract: A wiring board includes a wiring layer, an insulating layer, a plurality of opening portions, and a connection terminal. The insulating layer is laminated on the wiring layer and covers a wiring pattern. Each of the plurality of opening portions penetrates through the insulating layer to the wiring pattern. The connection terminal is formed on the respective opening portions and comes into contact with the upper surface of the wiring pattern. The wiring layer includes a first wiring pattern, and a second wiring pattern that is formed of a plurality of laminated metal layers and that is thicker than the first wiring pattern. An upper surface of a metal layer serving as an uppermost layer of the second wiring pattern is a contact surface with the connection terminal and has a same width as an upper surface of a metal layer serving as a layer other than the uppermost layer.

Abstract: An embedded circuit board, made without gas bubbles or significant internal gaps according to a manufacturing method which is provided, includes an inner layer assembly, an embedded element, and first and second insulating elements. The inner layer assembly comprises a first main portion with opposing first and second surfaces and a first groove not extending to the second surface is positioned at the first surface. A first opening penetrates the second surface, and the first opening and the first groove are connected. The first groove carries electronic elements for embedment. The first insulating element covers the first surface and a surface of the embedded element away from the second surface. The second insulating element covers the second surface and extends into the first opening to be in contact with the embedded element.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first dielectric structure having first inner sidewalls over an interlayer dielectric (ILD) structure. A second dielectric structure is over the first dielectric structure, where the first inner sidewalls are between second inner sidewalls of the second dielectric structure. A sidewall barrier structure is over the first dielectric structure and extends vertically along the second inner sidewalls. A lower bumping structure is between the second inner sidewalls and extends vertically along the first inner sidewalls and vertically along third inner sidewalls of the sidewall barrier structure. An upper bumping structure is over both the lower bumping structure and the sidewall barrier structure and between the second inner sidewalls, where an uppermost point of the upper bumping structure is at or below an uppermost point of the second dielectric structure.

Abstract: A flexible printed circuit board (FPCB), which is applied to various electronic display devices, may include a base, a first metal layer and a second metal layer on both surfaces of the base, a first plating layer on the first metal layer, a second plating layer on the second metal layer, and a first insulating pattern and a second insulating pattern respectively disposed on some region of the first plating layer and the second plating layer, wherein the first plating layer and the second plating layer may have different thicknesses.

Abstract: The present invention provides an organic bioelectronic HD device system for the effective removal of protein-bound substances, comprising PEDOT:PSS, a multiwall carbon nanotube, polyethylene oxide (PEO), and (3-glycidyloxypropyl)trimethoxysilane (GOPS). The composite nanofiber platform exhibited (i) long-term water-resistance; (ii) high adhesion strength on the PES membrane; (iii) enhanced electrical properties; and (iv) good anticoagulant ability and negligible hemolysis of red blood cells, suggesting great suitability for use in developing next-generation bioelectronic medicines for HD.

Abstract: A substrate for a printed wiring board, the substrate includes a base film containing polyimide as a main component and a sinter layer disposed on at least a portion of a surface of the base film and containing copper nanoparticles. The base film contains a nitrogen atom bonded to a copper atom of the copper nanoparticles, an average number of the nitrogen atom bonded to the copper atom per unit area of the surface of the base film on which the sinter layer is disposed is 2.6×1018 atoms/m2 to 7.7×1018 atoms/m2, and the average number is an average number calculated for a measurement region estimated to have a thickness of 3 nm from a measurement value of the surface of the base film measured by X-ray photoelectron spectroscopy.

Abstract: Provided are a surface-treated glass cloth that enables the reliability of a printed wiring board to be improved, a prepreg, and a printed wiring board. In the surface-treated glass cloth, a surface-treated layer contains a silane coupling agent, the amount of carbon attached of an adhering component of the surface-treated layer is in the range of 0.030 to 0.060% by mass, the arithmetic average height of the surface of the adhering component of the surface-treated layer is in the range of 1.0 to 3.0 nm, and the product of the amount of carbon attached of the adhering component and the arithmetic average height of the surface of the adhering component is in the range of 0.060 to 0.100.

Abstract: A circuit prearranged heat dissipation embedded packaging structure according to an embodiment of the present disclosure includes at least one chip and a support frame surrounding the at least one chip. The support frame may include a via pillar passing through the support frame in the height direction, a first wiring layer on a first surface of the support frame, and a heat dissipation layer on the back face of the chip. The first wiring layer is flush with or higher than the first surface, the first wiring layer is in conductive connection with the heat dissipation layer, a gap between the chip and the frame is completely filled with the dielectric material, a second wiring layer is formed on a terminal face of the chip, and the second wiring layer is in conductive connection with the first wiring layer through the via pillar.

Abstract: An embedded circuit board made without gas bubbles or significant internal gaps according to a manufacturing method which is here disclosed comprises an inner layer assembly, an embedded element, and first and second insulating elements. The inner layer assembly comprises a first main portion with opposing first and second surfaces, a first groove not extending to the second surface is positioned at the first surface. A first opening penetrates the second surface, and the first opening and the first groove are connected. The first groove carries electronic elements for embedment. The first insulating element covers the first surface and a surface of the embedded element away from the second surface. The second insulating element covers the second surface and extends into the first opening to be in contact with the embedded element.

Abstract: The present disclosure provides an array substrate and a manufacturing method thereof, a display panel and a backlight module. The manufacturing method of the array substrate includes: providing a base substrate; forming a metal wiring layer on a side of the base substrate, the metal wiring layer including a first copper metal layer; forming a planarization layer on a side of the metal wiring layer away from the base substrate; forming a drive lead layer on a side of the planarization layer away from the base substrate, the drive lead layer being electrically connected to the metal wiring layer, the drive lead layer including a second copper metal layer with a thickness larger than that of the first copper metal layer; forming a functional device layer on a side of the drive lead layer away from the base substrate.

Abstract: Provided are interconnect circuits and methods of forming thereof. A method may involve laminating a substrate to a conductive layer followed by patterning the conductive layer. This patterning operation forms individual conductive portions, which may be also referred to as traces or conductive islands. The substrate supports these portions relative to each other during and after patterning. After patterning, an insulator may be laminated to the exposed surface of the patterned conductive layer. At this point, the conductive layer portions are also supported by the insulator, and the substrate may optionally be removed, e.g., together with undesirable portions of the conductive layer. Alternatively, the substrate may be retained as a component of the circuit and the undesirable portions of the patterned conductive layer may be removed separately. These approaches allow using new patterning techniques as well as new materials for substrates and/or insulators.

Abstract: A semiconductor apparatus includes a heatsink plate, a substrate disposed on the heatsink plate, a circuit pattern disposed on the substrate, a semiconductor chip disposed on the circuit pattern, a case fixed to the heatsink plate and surrounding an outer perimeter of the substrate, a terminal attached to the case, and a wire configured to electrically connect the terminal to the circuit pattern or to the semiconductor chip. In a plan view as viewed in the thickness direction of the heatsink plate, a portion of the circuit pattern overlaps the terminal.

Abstract: Disclosed herein is a semiconductor device including a conductive member that has a main surface facing in a thickness direction, a semiconductor element that has a plurality of pads facing the main surface, a plurality of electrodes that are individually formed with respect to the plurality of pads and protrude from the plurality of pads toward the main surface, and a bonding layer for electrically bonding the main surface to the plurality of electrodes. The bonding layer includes a first region having conductivity and a second region having electrical insulation. The first region includes a metal portion. At least a part of the second region includes a resin portion.

Abstract: Audio device, electronic circuit, and related methods, in particular a method of manufacturing an electronic circuit for an audio device is disclosed, the method comprising providing a circuit board; mounting one or more electronic components including a first electronic component on the circuit board; applying a first insulation layer outside the first electronic component; and applying a first shielding layer outside the first insulation layer.

Abstract: A method of manufacturing package structures includes providing a carrier including a supporting layer, a metal layer, and a release layer between the supporting layer and the metal layer at first. Afterwards, a composite layer of a non-conductor inorganic material and an organic material is disposed on the metal layer. Then, a chip embedded substrate is bonded on the composite layer. Afterwards, an insulating protective layer having openings is formed on the circuit layer structure and exposes parts of the circuit layer structure in the openings. Afterwards, the supporting layer and the release layer are removed to form two package substrates. Then, each of the package substrates is cut.

Abstract: A coil component includes a body including a first surface and a second surface opposing each other, and a first side surface and a second side surface opposing each other and connecting the first surface of the body to the second surface of the body; a support substrate embedded in the body and including a first surface and a second surface opposing each other; coil portion disposed on the support substrate; and a recognition pattern disposed on the first surface of the body, wherein the recognition pattern extends, from an edge region in which the first surface of the body is in contact with the first side surface of the body, toward an edge region in which the first surface of the body is in contact with the second side surface of the body.

Abstract: A solder alloy is provided which can withstand the severe characteristics of a temperature cycle between a low temperature of ?40° C. and a high temperature of 125° C., withstand an external force applied due to, for example, riding on a curb or collision with a vehicle ahead for a long period of time, and can suppress change in viscosity of a solder paste over time. In addition, a solder paste, a solder ball, and a solder preform in which the solder alloy is used; a solder joint formed through the use thereof; and an on-board electronic circuit, an ECU electronic circuit, an on-board electronic circuit device, and an ECU electronic circuit device which include this solder joint are provided. The solder alloy contains, by mass %, 1% to 4% of Ag, 0.5% to 1.0% of Cu, 1.5% to 5.5% of Bi, 1.0% to 5.3% of Sb (or greater than 5.5% and less than or equal to 7.0% of Bi and 2.0% to 5.3% of Sb), 0.01% to 0.2% of Ni, 0.0040% to 0.0250% of As, and a balance of Sn.

Abstract: One aspect of the present invention is a prepreg including a resin composition or a semi-cured product of the resin composition and a fibrous base material, in which the resin composition contains a modified polyphenylene ether compound terminally modified with a substituent having an unsaturated carbon-carbon double bond, and a crosslinkable curing agent having an unsaturated carbon-carbon double bond in a molecule, the fibrous base material is quartz glass cloth, the prepreg contains a silane coupling agent having an unsaturated carbon-carbon double bond in a molecule, in an amount of 0.01% by mass or more and less than 3% by mass with respect to the prepreg, and a cured product of the prepreg has a dielectric loss tangent of 0.002 or less at 10 GHz.

Abstract: An electronic device such as a head-mounted device may have a display that displays computer-generated content for a user. The head-mounted device may have an optical system that directs the computer-generated content towards eye boxes for viewing by a user. The optical system may include a spatially addressable adjustable optical component. The adjustable optical component may have first and second electrodes and an electrically adjustable material between the first and second electrodes. The electrically adjustable material may include a transparent conductive material such as indium tin oxide that includes a pattern of segmented trenches configured to provide the transparent conductive material with electrical anisotropy. Contacts may be coupled to the transparent conductive material. Control circuitry can adjust the electrically adjustable material to form a spatially addressable light modulator or adjustable lens.

Abstract: A Chip on Film (COF) package and a display device including the same are provided. The COF package includes: a film substrate; a chip arranged within a chip region on the film substrate; outer leads; and inner leads. The outer leads are arranged on the same side of the chip region and arranged as at least two rows of outer leads. The inner leads are arranged on a first side and a second side of the chip and connected with the chip. The at least two rows of outer leads include a first row and a second row of outer leads, the first row of outer leads are between the second row of outer leads and the chip, and wirings between at least part of leads among the second row of outer leads and the inner leads on the second side of the chip adopt a closed-loop like connection mode.

Abstract: A semiconductor device includes a substrate and at least one capacitor element on each of opposite surfaces of the substrate. The at least one capacitor element includes a first electrode with a first pad and first terminals connected to the first pad, wherein the first terminals extend away from the substrate, and a second electrode with a second pad and second terminals connected to the second pad, wherein the second terminals extend toward the substrate, wherein the first terminals and the second terminals are staggered and separated by an interlayer dielectric layer.

Abstract: An adapting cable structure includes a cable, a first circuit board and a second circuit board. The cable is used to transfer a power signal or a control signal. The first circuit board includes a plurality of contacting parts and a plurality of first welding parts. Another end of the cable is on the second circuit board and the plurality of the contacting parts are located at two sides of the first circuit board. The plurality of welding parts are connected to one end of the cable. Furthermore, a pattern of a text or a specific design is placed on the cable. The pattern is used to improve the appearance or the identification of the cable.

Abstract: A semiconductor device package includes a first conductive base, a first insulation layer and a second insulation layer. The first conductive base has a first surface, a second surface opposite to the first surface and a lateral surface extended between the first surface and the second surface. The lateral surface includes a first portion adjacent to the first surface and a second portion adjacent to the second surface. The first insulation layer comprises a first insulation material. The first insulation layer has a first surface and a second surface opposite to the first surface. The first insulation layer covers the first portion of the lateral surface of the first conductive base. The second insulation layer comprises a second insulation material and covers the second portion of the lateral surface of the first conductive base. The first insulation material is different from the second insulation material.

Abstract: A lead-free solder alloy includes 2.0% by mass or more and 4.0% by mass or less of Ag, 0.3% by mass or more and 0.7% by mass or less of Cu, 1.2% by mass or more and 2.0% by mass or less of Bi, 0.5% by mass or more and 2.1% by mass or less of In, 3.0% by mass or more and 4.0% by mass or less of Sb, 0.001% by mass or more and 0.05% by mass or less of Ni, 0.001% by mass or more and 0.01% by mass or less of Co, and the balance being Sn.

Abstract: A lead-free solder alloy includes 2.0% by mass or more and 4.0% by mass or less of Ag, 0.3% by mass or more and 0.7% by mass or less of Cu, 1.2% by mass or more and 2.0% by mass or less of Bi, 0.5% by mass or more and 2.1% by mass or less of In, 3.0% by mass or more and 4.0% by mass or less of Sb, 0.001% by mass or more and 0.05% by mass or less of Ni, 0.001% by mass or more and 0.01% by mass or less of Co, and the balance being Sn.

Abstract: Disclosed herein is a semiconductor IC-embedded substrate that includes insulating layers, conductor layers, and a semiconductor IC embedded in the insulating layers. The insulating layers includes first and second insulating layers. The conductor layers includes a first conductor layer having a first wiring pattern and a second conductor layer having a second wiring pattern. The semiconductor IC includes a rewiring pattern connected in common to power supply pads. The rewiring pattern is connected to the first wiring pattern via a first opening of the first insulating layer. The first wiring pattern is connected to the second wiring pattern via second openings of the second insulating layer. The first opening is greater in area than each of the second openings.

Abstract: A lead-free solder contains 93.0 mass % or more and 98.95 mass % or less of indium, 1.0 mass % or more and 4.0 mass % or less of tin, and an addition metal. The addition metal contains at least one of silver, antimony, copper, or nickel. The addition metal is neither indium nor tin. The total of mass percentage of the addition metal is 0.05 mass % or more and 6.0 mass % or less. The sum of the total mass percentage of the addition metal, the mass percentage of indium, and the mass percentage of tin is 100 mass % or less.

Abstract: A method for manufacturing a wiring board is capable of forming a metal layer included in a wiring layer to have an even thickness. The method includes preparing a conductive first underlayer on a surface of a substrate; a conductive second underlayer on a surface of the first underlayer; and a seed layer on a surface of the second underlayer and containing metal. The method disposes a solid electrolyte membrane between an anode and the seed layer as a cathode; applies voltage between the anode and the first underlayer to form a metal layer on the surface of the seed layer; removes an exposed portion of the second underlayer without the seed layer from the substrate; and removes an exposed portion of the first underlayer without the seed layer from the substrate. The first underlayer is a material having a higher electrical conductivity than that of the second underlayer.

Abstract: A stretchable mounting board that includes a stretchable substrate having a main surface, a stretchable wiring disposed on the main surface of the stretchable substrate, a mounting electrode section electrically connected to the stretchable wiring, solder electrically connected to the mounting electrode section and including bismuth and tin, and an electronic component electrically connected to the mounting electrode section with the solder interposed therebetween. The mounting electrode section has a first electrode layer on a side thereof facing the stretchable wiring and which includes bismuth and tin, and a second electrode layer on a side thereof facing the solder and which includes bismuth and tin. A concentration of the bismuth in the first electrode layer is lower than a concentration of the bismuth in the second electrode layer.

Abstract: A bonded assembly includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes first metallic bonding pads embedded in first dielectric material layers, the second semiconductor die includes second metallic bonding pads embedded in second dielectric material layers, the first metallic bonding pads are bonded to a respective one of the second metallic bonding pads; and each of the first metallic bonding pads includes a corrosion barrier layer containing an alloy of a primary bonding metal and at least one corrosion-suppressing element that is different from the primary bonding metal.

Abstract: A touch element, a touch substrate, a display device, and a method of manufacturing the touch substrate are disclosed. The touch element includes a first conductive pattern layer. The first conductive pattern layer includes a first conductive pattern. The first conductive pattern includes a first basic pattern and a first incremental pattern. The touch element further includes a second conductive pattern layer. The second conductive pattern layer is stacked with and insulated from the first conductive pattern layer. An orthographic projection of the first incremental pattern on the second conductive pattern layer coincides with a pattern of the second conductive pattern layer.

Abstract: A substrate embedded electronic component package includes a core member having a cavity in which a metal layer is disposed on a bottom surface thereof, an electronic component disposed in the cavity, an encapsulant filling at least a portion of the cavity and covering at least a portion of each of the core member and the electronic component, and a connection structure disposed on the encapsulant and including a first wiring layer connected to the electronic component. A wall surface of the cavity has at least one groove portion protruding outwardly from a center of the cavity, and the groove portion extends to a same depth in the core member as a depth of the cavity.

Abstract: A printed wiring board includes a first resin insulating layer, a conductor layer on the first resin insulating layer, and a second resin insulating layer formed on the first resin insulating layer such that the second resin insulating layer is covering the conductor layer. The conductor layer includes a first circuit having a width of 15 ?m or less and a rectangular cross-sectional shape, a second circuit having a trapezoidal cross-sectional shape, a third circuit, a fourth circuit, a fifth circuit, and a sixth circuit, a space between the first and third circuits has a width of 14 ?m or less, a space between the first and fourth circuits has a width of 14 ?m or less, a space between the second and fifth circuits has a width of 20 ?m or more, and a space between the second and sixth circuits has a width of 20 ?m or more.

Abstract: A wiring board of the present disclosure comprises an insulating layer, a first conductor layer located on the surface of the insulating layer and containing any one of nickel and chromium, a metal belonging to group of the periodic table; or a metal belonging to group of the periodic table, a second conductor layer located inside the outer circumferential edge on the first conductor layer and containing copper, a third conductor layer located on the surface of the insulating layer in a state of covering the first conductor layer and the second conductor layer and containing nickel, and a fourth conductor layer located in a state of covering the third conductor layer and containing gold. The third conductor layer has an overhanging part extending outward from the outer circumferential edge of the first conductor layer, and the fourth conductor layer is located between the overhanging part and the insulating layer.

Abstract: Provided is an ink for use in electronic component production making use of screen printing, which is suitable for actually allowing fine lines with high precision to be drawn in screen printing, and for actually allowing successive screen printing operations to be performed. The ink for screen printing of the present invention includes surface-modified silver nanoparticles (A) and a solvent (B), and has a viscosity at a shear rate of 10 (1/s) and 25° C. of 60 Pa·s or more. The surface-modified silver nanoparticles (A) each include a silver nanoparticle and an amine-containing protective agent coating the silver nanoparticle. The solvent (B) includes at least a terpene solvent. In solvent (B), a content of solvents having a boiling point of less than 130° C. is 20 wt % or less based on the total amount of solvents.

Abstract: A semiconductor substrate includes a dielectric insulation layer and a structured metallization layer having at least five separate sections attached to the dielectric insulation layer, a first switching element having first emitter and collector terminals, a second switching element having second emitter and collector terminals, a first diode element having first anode and cathode terminals, and a second diode element having second anode and cathode terminals. The switching and diode elements are arranged on a first section of the metallization layer, with the collector and cathode terminals electrically coupled to the first section. The first anode and emitter terminals are electrically coupled to second and third sections. The second anode and emitter terminals are electrically coupled to fourth and fifth sections. The first section separates the second and fourth adjacent sections from the third and fifth adjacent sections.

Abstract: The present invention relates to a cleaner. A cleaner according to an aspect may include a battery housing and a battery separably coupled to the battery housing. The battery may include a frame, a plurality of battery cells received in the frame, a battery holder surrounding the plurality of battery cells and including a separation wall to divide the plurality of battery cells in a plurality of rows.

Abstract: An electricity storage device member is provided. The electricity storage device member includes a base material mainly composed of a metal and a resin layer stacked on the base material, in which the resin layer contains a crosslinked fluororesin.

Abstract: A semiconductor device includes a substrate and at least one capacitor element. The capacitor element is on the substrate. The capacitor element includes a first electrode with a first pad and first terminals connected to the first pad, wherein the first terminals extend away from the substrate; and a second electrode with a second pad and second terminals connected to the second pad, wherein the second terminals extend toward the substrate, wherein the first terminals and the second terminals are staggered and separated by an interlayer dielectric layer.

Abstract: In a sensor arrangement for measurement of the temperature of a disk, it is provided that the sensor arrangement comprises a circuit carrier with a temperature sensor arranged thereon, wherein the circuit carrier and the temperature sensor are arranged in a housing and an electrical connection and a heat-conducting element are guided out from the housing, the heat-conducting element is configured as a rigid pin, the rigid pin has a thermal connection and a mechanical connection to the circuit carrier, the rigid pin is provided and configured to make a thermal contact with the disk.

Abstract: A display device including a flexible module including a display panel; an adhesive film disposed on one surface of the flexible module; support plates disposed on the adhesive film; a first anti-adhesive film pattern disposed between each of the support plates and the adhesive film; and a second anti-adhesive film pattern disposed between each of the support plates and the adhesive film and spaced apart from the first anti-adhesive film pattern. Each of the first anti-adhesive film pattern and the second anti-adhesive film pattern includes a metal material, and each of the first anti-adhesive film pattern and the second anti-adhesive film pattern has a thickness in a range of 100 nm to 1000 nm.

Abstract: A multiple layer printed circuit board (PCB) in which the cores (or core layers) are removed and replaced with prepreg layers, which provide structure integrity for the PCB. Such a multi-layer PCB may include a plurality of layers that include a plurality of signal layers, a plurality of ground plane layers, a plurality of inner signal layers, and a single core substrate layer. Each layer in the plurality of layers may be separated from every other layer in the plurality of layers by at least one prepreg substrate layer.

Abstract: In the second area, the lower base surface of the wirings is in contact with the first inorganic insulating film including a stepped portion including upper surfaces having mutually different heights and being adjacent to each other in the second direction, and a stepped surface rising from the upper surfaces except the uppermost surface. The first inorganic insulating film constitutes at least the upper surfaces except the lowest surface, and the stepped surface. The adjacent wirings include a pair of convex portions protruding toward a direction facing each other. One and the other of the pair of convex portions are separated to face each other at a position where the stepped portion does not exist in the second area in the first inorganic insulating film.

Abstract: A multilayer board includes a first substrate made of a thermoplastic resin, a first conductor pattern provided on the first substrate, a second substrate made of the thermoplastic resin, and a second conductor pattern provided on the second substrate. An insulation coating which covers the first conductor pattern is partially disposed between the first substrate and the second substrate. The insulation coating is made of a material having lower fluidity at a predetermined press temperature than fluidities of the first substrate and the second substrate, and a plurality of substrates including the first substrate and the second substrate are laminated and thermally compressed and bonded at the press temperature.

Abstract: A package substrate is disclosed. The package substrate includes a substrate core, a cavity below the substrate core that extends from a surface of a first resist layer to a bottom surface of the package substrate, and a first terminal and a second terminal in the first resist layer. The package substrate also includes one or more passive components that are coupled inside the cavity to the first terminal and the second terminal.

Abstract: A semiconductor package includes a bottom package and an upper redistribution layer disposed on the bottom package. The bottom package includes a substrate and a semiconductor chip disposed on the substrate. A conductive pillar extends upwardly from the substrate and is spaced apart from the semiconductor chip. A mold layer is disposed on the substrate and encloses the semiconductor chip and lateral side surfaces of the conductive pillar. The conductive pillar includes a connection pillar configured to electrically connect the substrate to the upper redistribution layer and an alignment pillar that is spaced apart from the connection pillar. The upper redistribution layer includes a redistribution metal pattern configured to be electrically connected to the connection pillar. A first insulating layer is in direct contact with a top surface of the redistribution metal pattern. A top surface of the alignment pillar is in direct contact with the first insulating layer.

Abstract: To provide a copper-clad laminate which maintains adhesion between a resin film and a conductor layer and which suppresses the occurrence of wrinkles. A copper-clad laminate has a base film containing a thermoplastic resin, an underlying metal layer film-formed on a surface of the base film by a dry plating method, and a copper layer film-formed on a surface of the underlying metal layer. The underlying metal layer has a mean thickness of 0.3 to 1.9 nm. Since the underlying metal layer has a mean thickness of 0.3 nm or more, it is possible to maintain adhesion between the base film and a conductor layer. Since the underlying metal layer has a mean thickness of 1.9 nm or less, it is possible to suppress an increase in the temperature of a film during film-forming of the underlying metal layer, and it is possible to suppress the occurrence of wrinkles.

Abstract: The present disclosure relates to a piezoresistive ink composition for sensors production. This ink, change linearly their electrical resistivity with an applied deformation and can easily recover when the external applied stress is released. The composition comprises flexible polymers as thermoplastic elastomers from the styrene-butadiene-styrene family (SBS, SEBS or others), nanostructures of carbon or metal, polar solvents and dispersive agents. With this ink, the user can print the sensor with any desired geometry and use different printing techniques, including drop casting, spray, screen and inkjet printing.