Conducting (e.g., Ink) Patents (Class 174/257)
  • Patent number: 10804004
    Abstract: A conducting film of the present invention includes (A) graphene and/or graphene oxide, and/or derivatives thereof, and (B) a compound having a sulfonic acid group, and/or derivatives thereof, and has a volume resistivity of 1×104 ?·cm or less. A method for producing the conducting film of the present invention includes preparing a dispersion by dispersing a component including (A) graphene and/or graphene oxide, and/or derivatives thereof, and (B) a compound having a sulfonic acid group, and/or derivatives thereof in a dispersion medium, applying the dispersion on a substrate and drying it, and performing heat treatment at a temperature of 100° C. or more. Thereby, the present invention provides a conducting film that has high conductivity and can be applied to a wide range of composites including graphenes, and a method for producing the same.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: October 13, 2020
    Assignees: NATIONAL UNIVERSITY CORPORATION NAGOYA UNIVERSITY, FUJI POLYMER INDUSTRIES CO., LTD.
    Inventors: Shigeji Konagaya, Toshio Saruyama, Hitoshi Shibuya
  • Patent number: 10796928
    Abstract: A wiring structure includes a first unit, a second unit, a first insulation wall, a first redistribution layer and a third unit. The first unit is disposed at a first elevation and having a first circuit layer and a first dielectric layer surrounding the first circuit layer. The second unit is disposed at the first elevation and having a second circuit layer and a second dielectric layer surrounding the second circuit layer. The first insulation wall is disposed between the first unit and the second unit. The first redistribution layer is disposed on the first unit and the second unit, and electrically connected between the first unit and the second unit. The third unit is disposed on the first redistribution layer and having a third circuit layer and a third dielectric layer surrounding the third circuit layer.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: October 6, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Patent number: 10792489
    Abstract: The present invention provides a bio-electrode composition capable of forming a living body contact layer for a bio-electrode that is excellent in conductivity and biocompatibility, is light-weight, can be manufactured at low cost, and can control significant reduction in conductivity even though the bio-electrode is soaked in water or dried. The present invention is accomplished by a bio-electrode composition including an ionic material and a resin, in which the ionic material is a lithium salt, a sodium salt, a potassium salt, a calcium salt, or an ammonium salt of sulphonamide represented by the following general formula (1).
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: October 6, 2020
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Jun Hatakeyama, Takayuki Fujiwara, Motoaki Iwabuchi, Yasuyoshi Kuroda
  • Patent number: 10791631
    Abstract: Disclosed is a surface treated copper foil in which the dropping of the roughening particles from the roughening treatment layer provided on the surface of the copper foil is favorably suppressed. Also disclosed is a surface treated copper foil, comprising a copper foil, a roughening treatment layer on one surface, and/or another roughening treatment layer the other surface of the copper foil, wherein a height of roughening particles of the roughening treatment layer is 5 to 1000 nm from the surface, a color difference ?E*ab according to JIS Z 8730 of a surface of a side of the roughening treatment layer is 65 or less, and a glossiness of the TD of the surface of the side of the roughening treatment layer is 70% or less.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: September 29, 2020
    Assignee: JX Nippon Mining & Metals Corporation
    Inventors: Yuki Ori, Hideta Arai, Atsushi Miki, Ryo Fukuchi
  • Patent number: 10784203
    Abstract: In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Hsiu-Jen Lin, Hao-Yi Tsai, Ming Hung Tseng, Tsung-Hsien Chiang, Tin-Hao Kuo, Yen-Liang Lin
  • Patent number: 10765003
    Abstract: A multi-layer circuit board is formed by positioning a top sub having traces on at least one side to one or more pairs of composite layers, each composite layer comprising an interposer layer and a sub layer. Each sub layer which is adjacent to an interposer layer having an interconnection aperture, the interconnection aperture positioned adjacent to interconnections having a plated through via or pad on each corresponding sub layer. Each interposer aperture is filled with a conductive paste, and the stack of top sub and one or more pairs of composite layers are placed into a lamination press, the enclosure evacuated, and an elevated temperature and laminated pressure is applied until the conductive paste has melted, connecting the adjacent interconnections, and the boards are laminated together into completed laminated multi-layer circuit board.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: September 1, 2020
    Assignee: CATLAM, LLC
    Inventors: Kenneth S. Bahl, Konstantine Karavakis
  • Patent number: 10763031
    Abstract: There are provided an inductor and a method of manufacturing the same. The inductor includes: a body including a plurality of coil layers and high-rigidity insulating layers disposed on and beneath the plurality of coil layers; and external electrodes disposed on external surfaces of the body and connected to the coil layers. Build-up insulating layers are disposed between the high-rigidity insulating layers to cover the coil layers, and the high-rigidity insulating layers have a Young's modulus greater than that of the build-up insulating layers.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: September 1, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jong Yoon Jang, Seok Hwan Ahn, Jeong Min Cho, Tae Hoon Kim, Jin Gul Hyun, Se Woong Paeng
  • Patent number: 10756037
    Abstract: A package structure including a semiconductor die, an insulating encapsulant, a redistribution layer and a plurality of conductive terminals is provided. The semiconductor die includes a semiconductor substrate, a plurality of conductive pads and a plurality of conductive strips. The conductive pads are disposed on and connected to the plurality of conductive pads, wherein each of the conductive strips is physically connected to at least two conductive pads. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the insulating encapsulant and the semiconductor die, wherein the redistribution layer is electrically connected to the plurality of conductive strips. The plurality of conductive terminals is disposed on the redistribution layer.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hsien Huang, An-Jhih Su, Der-Chyang Yeh, Hua-Wei Tseng, Yueh-Ting Lin, Ming-Shih Yeh
  • Patent number: 10734248
    Abstract: A printed circuit board according to an embodiment includes: an insulating layer; a first pad disposed on a first surface of the insulating layer; a first conductive layer disposed on the first pad and including gold (Au); a second pad disposed on a second surface of the insulating layer; and a second conductive layer disposed on the second pad and including gold (Au), wherein the first conductive layer is a conductive layer connected to a wire, the second conductive layer is a conductive layer connected to a solder, and the first conductive layer is thicker than the second conductive layer.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: August 4, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Sung Oh Cho, Yoon Tai Kim
  • Patent number: 10721822
    Abstract: There is provided an electric connection member having a substrate, an insulating adhesive layer provided on the substrate, and a conductive interconnect, wherein the electric connection member is provided with a recess that opens at a side of the insulating adhesive layer, the conductive interconnect is disposed in the recess, a metal nano-ink is disposed on the conductive interconnect, and all of the metal nano-ink is contained inside the recess.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: July 21, 2020
    Assignee: JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITED
    Inventors: Junya Sato, Ryosuke Mitsui
  • Patent number: 10712453
    Abstract: A detection element can obtain a high-resolution radiation image having a high signal intensity and a high S/N ratio. A detection element including a substrate having a through hole, an insulating layer arranged inside of the through hole, a through electrode arranged further to the inner side of the through hole than the insulating layer, a resin layer having insulating properties and having an opening portion exposing the through electrode, a first electrode arranged above the through electrode and the resin layer, the first electrode being connected to the through electrode through the opening portion, and a second electrode arranged above the resin layer, the second electrode being separated from the first electrode.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: July 14, 2020
    Assignee: DAI NIPPON PRINTING Co., Ltd.
    Inventors: Kohei Ota, Tomohisa Motomura, Takamasa Takano, Koichi Nakayama
  • Patent number: 10658925
    Abstract: A printed circuit board (1) for converting an input phase to at least one output phase (U,V,W), which has an input phase surface area with at least one conductive DC+ layer (28) and one conductive DC? layer (29) for each conductive DC+ layer (28), for conducting the input phase. There is at least one high-side power semiconductor (6) for each output phase (U, V, W) and one low-side power semiconductor (7) for each high-side power semiconductor (6), for switching the input phase. The at least one DC+ layer (28) corresponding to a respective DC? layer (29) is formed in a cover surface area (2), which covers at least 75% of the input phase surface area.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 19, 2020
    Assignee: ZF FRIEDRICHSHAFEN AG
    Inventors: Wilfried Lassmann, Jörg Kűhnl
  • Patent number: 10653336
    Abstract: Methods of using subcutaneously implantable sensor devices and associated systems having a communication module that is controlled based upon the detection of a predetermined chemical agent.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Stanley Mo, Alexandra Zafiroglu, Giuseppe Raffa, Joshua Ratcliff, Jose Sia, Adam Jordan
  • Patent number: 10642429
    Abstract: The present disclosure provides a touch component, a method for manufacturing the touch component and a touch screen. The touch component includes a first metal mesh layer and a second metal mesh layer which are opposite to each other, the first metal mesh layer including a plurality of first touch channel areas, the first virtual wiring area including a plurality of first virtual wiring openings, the second metal mesh layer including a plurality of second touch channel areas and a plurality of second virtual wiring areas, the second virtual wiring area including a plurality of second virtual wiring openings. A projection of at least part of the first virtual wiring opening on the second metal mesh layer intersects with a grid line of the second metal mesh layer.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: May 5, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventors: Jiawei Xu, Qicheng Chen, Jun Li, Lei Zhang, Tsung Chieh Kuo
  • Patent number: 10639134
    Abstract: Methods and apparatuses for monitoring either or both the performance of an orthodontic appliance for repositioning a patient's teeth and/or the user compliance in wearing the appliance using a biosensor. The apparatuses described herein may include one or more sensors, including biosensors, electrical sensors, or both, configured to generate sensor data related to user compliance and/or repositioning of the patient's teeth by an orthodontic appliance.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: May 5, 2020
    Assignee: Align Technology, Inc.
    Inventors: Yaser Shanjani, Bruce Cam, John Y. Morton, Jun Sato
  • Patent number: 10619262
    Abstract: Electrodeposited copper foils having properties suitable for use as current collectors in lithium-ion secondary batteries are disclosed. The electrodeposited copper foils include a drum side and a deposited side. At least one of the deposited side or the drum side has a root mean square slope (R?q) in the range of about 0.03 to about 0.23. In this manner, the copper foil has good durability and workability, as well as good performance as current collectors in lithium-ion secondary batteries.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: April 14, 2020
    Assignee: CHANG CHUN PETROCHEMICAL CO., LTD.
    Inventors: Huei-Fang Huang, Yao-Sheng Lai, Jui-Chang Chou
  • Patent number: 10607848
    Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed on the substrate. A first passivation material layer is formed on sidewalls of the opening and on the substrate. A treatment process is performed to the first passivation material layer to form a second passivation material layer. A first surface of the second passivation material layer and a second surface (at an inner side) of the second passivation material layer are differ in a property, and the first surface is located at a side of the second passivation material layer relatively away from the material layer.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: March 31, 2020
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Yuan-Chieh Chiu, Shih-Ping Hong, Kuang-Chao Chen, Yen-Ju Chen
  • Patent number: 10609823
    Abstract: A method for manufacturing a multilayer wiring board includes a step (1) and a step (2). The step (1) disposes a hole for through-hole, a squirt of metal foils, and a lower space. The squirt of the metal foils on both the sides of the insulating layer is formed at an opening of the hole for through-hole. The lower space is formed between the squirt of the metal foils and an inner wall of the hole for through-hole. The step (2) plugs up the hole for through-hole by forming an electrolytic filled plating layer at an inside of the hole for through-hole and on the metal foils on both the sides of the insulating layer. The plugging of the hole for through-hole in the step (2) is performed by once decreasing a current density of an electrolytic filled plating in a middle of the electrolytic filled plating and then increasing the current density again.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: March 31, 2020
    Assignee: HITACHI CHEMICAL COMPANY, LTD.
    Inventor: Nobuyuki Yoshida
  • Patent number: 10597508
    Abstract: There is provided an electromagnetic wave shielding material excellent in moldability and developing a good electromagnetic wave shielding function. The electromagnetic wave shielding material 1 contains a synthetic resin 11, and an exfoliated graphite 12 being a layered body of graphene and having a number of graphene layers of 200 or smaller and an aspect ratio of 20 or higher.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: March 24, 2020
    Assignee: SEKISUI CHEMICAL CO., LTD.
    Inventors: Katsunori Takahashi, Kensuke Tsumura, Kazuhiro Sawa
  • Patent number: 10602621
    Abstract: A method of manufacturing a circuit board includes: providing a substrate including a bottom layer and a resin layer over the bottom layer, the resin layer including a first surface in contact with the bottom layer and a second surface opposite to the first surface; forming a plurality of vias through the resin layer; depositing a first metal layer in the vias, the first metal layer filling a portion of each of the vias; depositing a second metal layer over the first metal layer and in the vias; forming a patterned metal layer over the second metal layer and extending from each of the vias to a position over the second surface; separating the bottom layer and the resin layer; and removing a portion of the resin layer from the first surface, so that the first metal layer protrudes from the resin layer.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: March 24, 2020
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventor: Hsin-Chi Hu
  • Patent number: 10601158
    Abstract: There is a problem that an oxide film or high resistance abrasion powder is formed at the contact interface due to micro sliding abrasion in a high temperature environment or temperature cycle to increase the contact resistance at the contact portion of a non-noble metal connection terminal. Provided is an in-vehicle electronic module, a connector, and a connection structure thereof, which have the same connection reliability as noble metals even when exposed to a harsh environment and can reduce cost of members.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: March 24, 2020
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Ryouichi Kajiwara, Toshiaki Ishii, Masaru Kamoshida
  • Patent number: 10593438
    Abstract: A solar cell front side silver paste doped with modified graphene and its preparation method are disclosed. The solar cell front side silver paste doped with modified graphene comprises by weight 0.1-5 parts of modified graphene, 88-91 parts of silver powder, 5-15 parts of organic binder, 1-5 parts of organic solvent, 1-3 parts of glass powder, wherein the modified graphene is a surface modified graphene. A solar cell front side silver paste is developed, which is screen printed on a crystalline silicon wafer, sintered at a high temperature, penetrates the SiNx passivation layer in the crystalline silicon wafer, and thus forms a good ohmic contact.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: March 17, 2020
    Assignee: Nantong T-Sun New Energy Co., Ltd.
    Inventor: Peng Zhu
  • Patent number: 10590296
    Abstract: The present disclosure relates to a piezoresistive ink composition for sensors production. This ink, change linearly their electrical resistivity with an applied deformation and can easily recover when the external applied stress is released. The composition comprises flexible polymers as thermoplastic elastomers from the styrene-butadiene-styrene family (SBS, SEBS or others), nanostructures of carbon or metal, polar solvents and dispersive agents. With this ink, the user can print the sensor with any desired geometry and use different printing techniques, including drop casting, spray, screen and inkjet printing.
    Type: Grant
    Filed: January 2, 2017
    Date of Patent: March 17, 2020
    Assignees: UNIVERSIDAD DO MINHO, DYNASOL ELASTOMEROS S.A.
    Inventors: Senen Lanceros Mendez, Pedro Filipe Ribeiro Da Costa, Juliana Alice Ferreira Oliveira, Bruna Ferreira Gonçalves, Sergio Corona Galvàn
  • Patent number: 10590310
    Abstract: The present invention relates to a method for reversibly bonding a first and a second substrate, wherein at least the first substrate is an electrically non-conductive substrate, the method comprising: coating the surface of the electrically non-conductive substrate(s) with a conductive ink; applying an electrically debondable hot melt adhesive composition to the conductive ink-coated surface of the first substrate and/or the second substrate; contacting the first and the second substrates such that the electrically debondable hot melt adhesive composition is interposed between the two substrates; allowing formation of an adhesive bond between the two substrates to provide bonded substrates; and optionally applying a voltage to the bonded substrates whereby adhesion at least one interface between the electrically debondable hot melt adhesive composition and a substrate surface is substantially weakened. Furthermore, the present invention relates to the bonded substrates thus obtained.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: March 17, 2020
    Assignee: Henkel AG & Co. KGaA
    Inventors: Reimar Heucher, Thomas Moeller, Siegfried Kopannia, Alasdair Crawford
  • Patent number: 10585541
    Abstract: A display may include a substrate, an array of thin film transistors, an array of micro-light-emitting diode elements supported by the substrate and an array of sensing elements supported by the substrate. Each sensing element may include a continuous conductive layer functioning as part of the sensing element and extending along the substrate as an electrically conductive trace connected to one of the thin film transistors.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: March 10, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ning Ge, Ya-Ling Chang, Helen A. Holder
  • Patent number: 10586661
    Abstract: A process for producing a thin film graphene oxide-bonded metal foil current collector for a battery or supercapacitor, comprising: (a) preparing a graphene oxide gel having graphene oxide (GO) molecules dissolved in a fluid medium; (b) depositing a layer of GO gel onto at least one of two primary surfaces of a metal foil to form a layer of wet graphene oxide gel, wherein the depositing procedure includes shear-induced thinning of the GO gel; (c) partially or completely removing said fluid medium from the deposited wet layer to form a dry film of GO having an inter-plane spacing d002 of 0.4 nm to 1.2 nm as determined by X-ray diffraction; and (d) heat treating the dry film of graphene oxide to form the thin film graphene oxide-bonded metal foil current collector at a heat treatment temperature from 80° C. to 2,500° C.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: March 10, 2020
    Assignee: Global Graphene Group, Inc.
    Inventors: Aruna Zhamu, Yi-Jun Lin, Bor Z. Jang
  • Patent number: 10569085
    Abstract: The invention is an implantable electrode configuration having a carrier substrate of a biocompatible polymer in at least some areas and a freely accessible electrode surface applied to the carrier substrate or integrated into the carrier substrate on the carrier substrate surface in at least some areas is described and a method for producing the implantable electrode configuration. The electrode has a metallic base plate having a planar top side and bottom side, including at least one structural element protruding orthogonally from the top side. The planar surface of the metallic base plate is oriented parallel to the carrier substrate surface and the metallic base plate is enclosed by the biocompatible polymer, except for a first surface area of the at least one structural element which faces the carrier substrate surface and is the freely accessible electrode surface.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: February 25, 2020
    Assignee: Neuroloop GmbH
    Inventors: Dennis Plachta, Mortimer Giehrtmuehlen, Thomas Stieglitz, Josef Zentner
  • Patent number: 10537017
    Abstract: A printed circuit board according to an embodiment of the present invention includes a base film containing, as a main component, a polyimide and a conductive pattern disposed on at least one surface of the base film. The conductive pattern includes a copper particle bond layer which is fixed to the base film. An external transmittance for a wavelength of 500 nm in a conductive pattern non-formed region of the base film is 70% or less of an internal transmittance for a wavelength of 500 nm in a middle layer portion of the base film.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: January 14, 2020
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Kohei Okamoto, Kousuke Miura, Hiroshi Ueda, Takashi Kasuga, Kazuhiro Miyata
  • Patent number: 10537021
    Abstract: A three-dimensional wiring board production method is provided that includes: a preparation step of preparing a resin film (1) having a breaking elongation of 50% or more; a first metal film formation step of forming a first metal film (3) on a surface of the resin film; a pattern formation step of performing patterning on the first metal film to form a desired pattern; a three-dimensional molding step of performing three-dimensional molding by heating and pressurizing the resin film; and a second metal film formation step of forming a second metal film (21) on the first metal film having a pattern formed thereon. In the first metal film formation step, metal is deposited in a particle state to form the first metal film in a porous state.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 14, 2020
    Assignee: MEIKO ELECTRONICS CO., LTD.
    Inventor: Shigeru Michiwaki
  • Patent number: 10535592
    Abstract: A barrier layer is formed over electrically conductive contact pads on a substrate such as a wafer. A photoresist layer is applied over the barrier layer, and openings in the photoresist layer are filled with solder to form solder bumps. The barrier layer may be removed from within the openings prior to filling the openings with solder. The process is applicable to fine pitch architectures and chip size packaging substrates. The photoresist layer and portions of the barrier layer outside of the openings are removed following solder fill.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: January 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Eric P. Lewandowski, Jae-Woong Nah, Peter J. Sorce
  • Patent number: 10522289
    Abstract: An electronic component includes a component main body including an embedded internal conductor and an outer electrode. The component main body includes an end surface on which the internal conductor is exposed, and a main surface that is continuous with the end surface and intersects with the end surface. The outer electrode includes an end surface covering portion connected to the internal conductor by covering at least a portion of the internal conductor exposed on the end surface, and a main surface covering portion that covers at least a portion of the main surface. At least a portion of an exposed surface of the main surface covering portion includes a Sn plating layer, and at least a portion of an exposed surface of the end surface covering portion includes a Sn—Ni layer.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: December 31, 2019
    Assignee: MURATA & MANUFACTURING CO., LTD.
    Inventors: Shinichiro Kuroiwa, Kazuo Hattori, Isamu Fujimoto, Yasuyuki Sekimoto
  • Patent number: 10518503
    Abstract: A laminated substrate including a halogen-free epoxy resin composition. The halogen-free epoxy resin composition includes 100 parts by weight of a halogen-free naphthalene type epoxy resin, 10 to 25 parts by weight of a DOPO modified curing agent, 25 to 45 parts by weight of a cyanate resin, 35 to 60 parts by weight of bismaleimide, 45 to 65 parts by weight of a non-DOPO flame retardant, and 0.5 to 15 parts by weight of a curing accelerator. The laminated substrate of the present disclosure includes a halogen-free epoxy resin composition which has the characteristic of high transition temperature, so that the halogen-free epoxy resin composition has low dielectric constant, low dissipation factor, high heat resistance and high storage modulus.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: December 31, 2019
    Assignee: ITEQ CORPORATION
    Inventors: Ta-Yuan Yu, Kai-Yang Chen, Yen-Hsing Wu
  • Patent number: 10490421
    Abstract: A printed circuit board according to an embodiment includes: an insulating layer; a first pad disposed on a first surface of the insulating layer; a first conductive layer disposed on the first pad and including gold (Au); a second pad disposed on a second surface of the insulating layer; and a second conductive layer disposed on the second pad and including gold (Au), wherein the first conductive layer is a conductive layer connected to a wire, the second conductive layer is a conductive layer connected to a solder, and the first conductive layer is thicker than the second conductive layer.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: November 26, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Sung Oh Cho, Yoon Tai Kim
  • Patent number: 10468342
    Abstract: A method to produce a substrate suitable for diffusion bonding is described. A flexible dielectric substrate is provided. An alkaline modification is applied to the dielectric substrate to form a polyamic acid (PAA) anchoring layer on a surface of the dielectric substrate. A Ni—P seed layer is electrolessly plated on the PAA layer. Copper traces are plated within a photoresist pattern on the Ni—P seed layer. A surface finishing layer is electrolytically plated on the copper traces. The photoresist pattern and Ni—P seed layer not covered by the copper traces are removed to complete the substrate suitable for diffusion bonding.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: November 5, 2019
    Assignee: Compass Technology Company, Ltd.
    Inventors: Kelvin Po Leung Pun, Chee Wah Cheung
  • Patent number: 10433429
    Abstract: A method is presented that improves reliability for the mechanical electrical connection formed between a grid array device, such as a pin grid array device (PGA) or a column grid array device (CGA), and a substrate such as a printed circuit board (PCB). Between adjacent PCB pads, the method increases a spacing pattern toward the periphery of the CGA, creating a misalignment between pads and columns. As part of the method, columns align with the pads, resulting in column tilt that increases from the center to the periphery of the CGA. An advantage of the method is that the column tilt reduces the amount of contractions and expansions of columns during thermal cycling, thereby increasing the projected life of CGA. Another advantage of the method is that it reduces shear stress, further increasing the projected life of the CGA.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: October 1, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: James H. Kelly, Dmitry Tolpin, Roger M. Maurais
  • Patent number: 10412837
    Abstract: An anisotropic conductive film including conductive particles arranged uniformly in a single layer and capable of supporting fine-pitch connection is produced by: drying a coating film of a particle dispersion in which conductive particles are dispersed in a dilute solution of a thermoplastic resin that forms a coating after drying, whereby a conductive particle-containing layer is formed in which the coated conductive particles coated with the dried coating of the dilute solution of the thermoplastic resin and arranged in a single layer stick to the dried coating film; and laminating an insulating resin layer onto the conductive particle-containing layer.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: September 10, 2019
    Assignee: DEXERIALS CORPORATION
    Inventor: Kouichi Sato
  • Patent number: 10386957
    Abstract: The conductive film is configured such that in a case in which a parameter Ca of a first-overlapped-portion in which a thin metal wire constituting a first-electrode and a thin metal wire constituting a second-electrode are superimposed in plan view is represented by Equation (1) of Ca=(A?wa*wb)/d, while setting an area of the first-overlapped-portion to A (?m2), line widths of the respective thin metal wires constituting the first-electrode and the second-electrode to wa and wb (?m), and a distance between the first-electrode and the second-electrode in a thickness direction of a substrate to d (?m), in a 5 mm×5 mm quadrangular region that is set to include a crossing region in which the first-electrode and the second-electrode cross each other in a conductive region, the parameter Ca of 90% or more of the first-overlapped-portions included in the region is 1.0 or less.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: August 20, 2019
    Assignee: FUJIFILM Corporation
    Inventor: Hiroshige Nakamura
  • Patent number: 10373903
    Abstract: A laminate is provided comprising a support, a resin layer, a metal layer, an insulating layer, and a redistribution layer. The resin layer comprises a photo-decomposable resin having light-shielding properties and has a transmittance of up to 20% with respect to light of wavelength 355 nm. The laminate is easy to fabricate and has thermal process resistance, the support is easily separated, and a semiconductor package is efficiently produced.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: August 6, 2019
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Hiroyuki Yasuda, Michihiro Sugo, Hideto Kato, Kazunori Kondo
  • Patent number: 10368449
    Abstract: An anisotropic conductive film including conductive particles arranged uniformly in a single layer and capable of supporting fine-pitch connection is produced by: drying a coating film of a particle dispersion in which conductive particles are dispersed in a dilute solution of a thermoplastic resin that forms a coating after drying, whereby a conductive particle-containing layer is formed in which the coated conductive particles coated with the dried coating of the dilute solution of the thermoplastic resin and arranged in a single layer stick to the dried coating film; and laminating an insulating resin layer onto the conductive particle-containing layer.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: July 30, 2019
    Assignee: DEXERIALS CORPORATION
    Inventor: Kouichi Sato
  • Patent number: 10361176
    Abstract: An apparatus includes a substrate and a circuit trace having a predetermined pattern disposed on the substrate. A plurality of LEDs are connected to the substrate via the circuit trace. The predetermined pattern is arranged as an array of lines along a surface of the substrate, and the plurality of LEDs are distributed along the lines of the array.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: July 23, 2019
    Assignee: Rohinni, LLC
    Inventors: Cody Peterson, Andrew Huska
  • Patent number: 10361265
    Abstract: A semiconductor structure that includes a resistor that is located within an interconnect dielectric material layer of an interconnect level is provided. The resistor includes a diffusion barrier material that is present at a bottom of a feature that is located in the interconnect dielectric material layer. In some embodiments, the resistor has a topmost surface that is located entirely beneath a topmost surface of the interconnect dielectric material layer. In such an embodiment, the resistor is provided by removing sidewall portions of a diffusion barrier liner that surrounds a metal-containing structure. The removal of the sidewall portions of the diffusion barrier liner reduces the parasitic noise that is contributed to the sidewall portions of a resistor that includes such a diffusion barrier liner. Improved precision can also be obtained since sidewall portions may have a high thickness variation which may adversely affect the resistor's precision.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Baozhen Li, Kirk Peterson, John Sheets, Lawrence A. Clevenger, Junli Wang, Chih-Chao Yang
  • Patent number: 10350872
    Abstract: The present invention is to provide an anisotropic conductive film that excels in dispersing conductive particles and trapping the particles, and maintains conduction reliability even between narrow-pitched terminals. By a method for manufacturing an anisotropic conductive film containing conductive particles, the conductive particles are buried in grooves in a sheet having the grooves regularly formed in the same direction, the conductive particles are arranged, a first resin film having a thermo-setting resin layer formed on a stretchable base film is laminated on the surface of the sheet on the side of the grooves to transfer and attach the conductive particles to the first resin film, the first resin film is uniaxially stretched in a direction other than the direction perpendicular to the array direction of the conductive particles, and a second resin film is laminated.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: July 16, 2019
    Assignee: DEXERIALS CORPORATION
    Inventor: Tomoyuki Ishimatsu
  • Patent number: 10356898
    Abstract: Provided herein is a carrier-attached copper foil having desirable fine circuit formability. The carrier-attached copper foil includes a carrier, an interlayer, and an ultrathin copper layer in this order. The maximum ridge height Sp as measured with a laser microscope according to ISO 25178 on the surface of the carrier-attached copper foil on the side of the ultrathin copper layer is 0.193 to 3.082 ?m.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: July 16, 2019
    Assignee: JX Nippon Mining & Metals Corporation
    Inventor: Nobuaki Miyamoto
  • Patent number: 10356900
    Abstract: A circuit board, a display device including the same, and a method of manufacturing a circuit board are provided. A circuit board includes a base substrate, a wiring line provided on the base substrate, a passivation layer provided on the wiring line, an elastic bump provided on the passivation layer, and a conductive layer provided on the elastic bump. The passivation layer includes a first opening and a second opening that expose a partial region of the wiring line, and the second opening is arranged in a region adjacent to the first opening.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: July 16, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jung Yun Jo, Jeong Do Yang
  • Patent number: 10346561
    Abstract: A computer-implemented method for determining a system layout of a photovoltaic (PV) system is implemented by a design automation computer system in communication with a memory. The method includes receiving a first selection of a system table, receiving a layout mode designation, identifying a system orientation, identifying a system spacing, receiving a layout detail designation, and applying a layout algorithm based on the first selection of a system table, the layout mode designation, the layout mode designation, the system orientation, the system spacing and the layout detail designation.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: July 9, 2019
    Assignee: FTC Solar, Inc.
    Inventors: Andrew Joseph Morse, Nagendra Srinivas Cherukupalli, Ravi Ranganathan, Krishnan Ramagopal
  • Patent number: 10349520
    Abstract: A multi-layer circuit board is formed by positioning a top sub having traces on at least one side to one or more pairs of composite layers, each composite layer comprising an interposer layer and a sub layer. Each sub layer which is adjacent to an interposer layer having an interconnection aperture, the interconnection aperture positioned adjacent to interconnections having a plated through via or pad on each corresponding sub layer. Each interposer aperture is filled with a conductive paste, and the stack of top sub and one or more pairs of composite layers are placed into a lamination press, the enclosure evacuated, and an elevated temperature and laminated pressure is applied until the conductive paste has melted, connecting the adjacent interconnections, and the boards are laminated together into completed laminated multi-layer circuit board.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: July 9, 2019
    Assignee: CATLAM, LLC
    Inventors: Konstantine Karavakis, Kenneth S. Bahl
  • Patent number: 10349518
    Abstract: A method of manufacturing an embedded circuit board includes: a first adhesive coated copper is provided, which includes a first copper layer pre-formed with at least two first positioning holes and a first adhesive layer formed on a surface of the first copper layer; at least one first electronic element are adhered to the first adhesive layer, electrodes of the first electronic element face their corresponding first positioning hole; a second adhesive coated copper and a semi-cured film are provided, the first adhesive coated copper and the second adhesive coated copper are pressed on opposite surfaces of the semi-cured film, thereby embedding the first electronic elements in the semi-cured film; the first adhesive layer is partially removed to define first holes for exposing electrodes of the first electronic element; the electrodes are electrically connected with the first copper layer. A circuit board made by the method is also provided.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 9, 2019
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventors: Han-Pei Huang, Yong-Chao Wei
  • Patent number: 10347628
    Abstract: Forming a semiconductor layer on a semiconductor substrate, a top surface of the semiconductor layer above a fin in a second region is higher than a top surface of the semiconductor layer in a first region, etching the semiconductor layer and a mask in the first region to expose a top surface of the semiconductor substrate to form a first stack, and etching the semiconductor layer and the mask in the second region to expose a top surface of the fin to form a second stack, epitaxially growing a semiconductor material on a top surface of the fin not covered by the second stack, recessing the first and second stack to expose a top surface of the semiconductor layer, a portion of the mask remains above the semiconductor layer in the first stack, top surfaces of each of the first and second stacks each are substantially flush with one another.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Charan V. V. S. Surisetty
  • Patent number: 10342135
    Abstract: Disclosed herein are a printed circuit board, a manufacturing method thereof, and a semiconductor package including the printed circuit board. The printed circuit board includes a base substrate including a plurality of circuit patterns, a cavity formed above the base substrate, a pad embedded in the base substrate and being exposed through the substrate bottom surface of the cavity, and an electronic component mounted in the cavity and electrically connected to the pad. According to the present invention, a cavity having a predetermined depth is formed in a base substrate of a printed circuit board so as to mount an electronic component therein, such that a gap between an upper semiconductor package and a lower semiconductor package may be obtained even if pitches between the balls are decreased for high density and high performance of the upper semiconductor package in the manufacturing of a semiconductor package having a PoP structure.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: July 2, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seong Ryul Choi, Suk Chang Hong, Sang Kab Park, Kwang Seop Youm
  • Patent number: 10325843
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: June 18, 2019
    Assignee: INTEL CORPORATION
    Inventors: Qinglei Zhang, Stefanie M. Lotz