Abstract: Methods of using subcutaneously implantable sensor devices and associated systems having a communication module that is controlled based upon the detection of a predetermined chemical agent.

Abstract: A printed circuit board (1) for converting an input phase to at least one output phase (U,V,W), which has an input phase surface area with at least one conductive DC+ layer (28) and one conductive DC? layer (29) for each conductive DC+ layer (28), for conducting the input phase. There is at least one high-side power semiconductor (6) for each output phase (U, V, W) and one low-side power semiconductor (7) for each high-side power semiconductor (6), for switching the input phase. The at least one DC+ layer (28) corresponding to a respective DC? layer (29) is formed in a cover surface area (2), which covers at least 75% of the input phase surface area.

Abstract: Methods and apparatuses for monitoring either or both the performance of an orthodontic appliance for repositioning a patient's teeth and/or the user compliance in wearing the appliance using a biosensor. The apparatuses described herein may include one or more sensors, including biosensors, electrical sensors, or both, configured to generate sensor data related to user compliance and/or repositioning of the patient's teeth by an orthodontic appliance.

Abstract: The present disclosure provides a touch component, a method for manufacturing the touch component and a touch screen. The touch component includes a first metal mesh layer and a second metal mesh layer which are opposite to each other, the first metal mesh layer including a plurality of first touch channel areas, the first virtual wiring area including a plurality of first virtual wiring openings, the second metal mesh layer including a plurality of second touch channel areas and a plurality of second virtual wiring areas, the second virtual wiring area including a plurality of second virtual wiring openings. A projection of at least part of the first virtual wiring opening on the second metal mesh layer intersects with a grid line of the second metal mesh layer.

Abstract: Electrodeposited copper foils having properties suitable for use as current collectors in lithium-ion secondary batteries are disclosed. The electrodeposited copper foils include a drum side and a deposited side. At least one of the deposited side or the drum side has a root mean square slope (R?q) in the range of about 0.03 to about 0.23. In this manner, the copper foil has good durability and workability, as well as good performance as current collectors in lithium-ion secondary batteries.

Abstract: A method for manufacturing a multilayer wiring board includes a step (1) and a step (2). The step (1) disposes a hole for through-hole, a squirt of metal foils, and a lower space. The squirt of the metal foils on both the sides of the insulating layer is formed at an opening of the hole for through-hole. The lower space is formed between the squirt of the metal foils and an inner wall of the hole for through-hole. The step (2) plugs up the hole for through-hole by forming an electrolytic filled plating layer at an inside of the hole for through-hole and on the metal foils on both the sides of the insulating layer. The plugging of the hole for through-hole in the step (2) is performed by once decreasing a current density of an electrolytic filled plating in a middle of the electrolytic filled plating and then increasing the current density again.

Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed on the substrate. A first passivation material layer is formed on sidewalls of the opening and on the substrate. A treatment process is performed to the first passivation material layer to form a second passivation material layer. A first surface of the second passivation material layer and a second surface (at an inner side) of the second passivation material layer are differ in a property, and the first surface is located at a side of the second passivation material layer relatively away from the material layer.

Abstract: There is provided an electromagnetic wave shielding material excellent in moldability and developing a good electromagnetic wave shielding function. The electromagnetic wave shielding material 1 contains a synthetic resin 11, and an exfoliated graphite 12 being a layered body of graphene and having a number of graphene layers of 200 or smaller and an aspect ratio of 20 or higher.

Abstract: A method of manufacturing a circuit board includes: providing a substrate including a bottom layer and a resin layer over the bottom layer, the resin layer including a first surface in contact with the bottom layer and a second surface opposite to the first surface; forming a plurality of vias through the resin layer; depositing a first metal layer in the vias, the first metal layer filling a portion of each of the vias; depositing a second metal layer over the first metal layer and in the vias; forming a patterned metal layer over the second metal layer and extending from each of the vias to a position over the second surface; separating the bottom layer and the resin layer; and removing a portion of the resin layer from the first surface, so that the first metal layer protrudes from the resin layer.

Abstract: There is a problem that an oxide film or high resistance abrasion powder is formed at the contact interface due to micro sliding abrasion in a high temperature environment or temperature cycle to increase the contact resistance at the contact portion of a non-noble metal connection terminal. Provided is an in-vehicle electronic module, a connector, and a connection structure thereof, which have the same connection reliability as noble metals even when exposed to a harsh environment and can reduce cost of members.

Abstract: The present disclosure relates to a piezoresistive ink composition for sensors production. This ink, change linearly their electrical resistivity with an applied deformation and can easily recover when the external applied stress is released. The composition comprises flexible polymers as thermoplastic elastomers from the styrene-butadiene-styrene family (SBS, SEBS or others), nanostructures of carbon or metal, polar solvents and dispersive agents. With this ink, the user can print the sensor with any desired geometry and use different printing techniques, including drop casting, spray, screen and inkjet printing.

Abstract: A solar cell front side silver paste doped with modified graphene and its preparation method are disclosed. The solar cell front side silver paste doped with modified graphene comprises by weight 0.1-5 parts of modified graphene, 88-91 parts of silver powder, 5-15 parts of organic binder, 1-5 parts of organic solvent, 1-3 parts of glass powder, wherein the modified graphene is a surface modified graphene. A solar cell front side silver paste is developed, which is screen printed on a crystalline silicon wafer, sintered at a high temperature, penetrates the SiNx passivation layer in the crystalline silicon wafer, and thus forms a good ohmic contact.

Abstract: The present invention relates to a method for reversibly bonding a first and a second substrate, wherein at least the first substrate is an electrically non-conductive substrate, the method comprising: coating the surface of the electrically non-conductive substrate(s) with a conductive ink; applying an electrically debondable hot melt adhesive composition to the conductive ink-coated surface of the first substrate and/or the second substrate; contacting the first and the second substrates such that the electrically debondable hot melt adhesive composition is interposed between the two substrates; allowing formation of an adhesive bond between the two substrates to provide bonded substrates; and optionally applying a voltage to the bonded substrates whereby adhesion at least one interface between the electrically debondable hot melt adhesive composition and a substrate surface is substantially weakened. Furthermore, the present invention relates to the bonded substrates thus obtained.

Abstract: A display may include a substrate, an array of thin film transistors, an array of micro-light-emitting diode elements supported by the substrate and an array of sensing elements supported by the substrate. Each sensing element may include a continuous conductive layer functioning as part of the sensing element and extending along the substrate as an electrically conductive trace connected to one of the thin film transistors.

Abstract: A process for producing a thin film graphene oxide-bonded metal foil current collector for a battery or supercapacitor, comprising: (a) preparing a graphene oxide gel having graphene oxide (GO) molecules dissolved in a fluid medium; (b) depositing a layer of GO gel onto at least one of two primary surfaces of a metal foil to form a layer of wet graphene oxide gel, wherein the depositing procedure includes shear-induced thinning of the GO gel; (c) partially or completely removing said fluid medium from the deposited wet layer to form a dry film of GO having an inter-plane spacing d002 of 0.4 nm to 1.2 nm as determined by X-ray diffraction; and (d) heat treating the dry film of graphene oxide to form the thin film graphene oxide-bonded metal foil current collector at a heat treatment temperature from 80° C. to 2,500° C.

Abstract: The invention is an implantable electrode configuration having a carrier substrate of a biocompatible polymer in at least some areas and a freely accessible electrode surface applied to the carrier substrate or integrated into the carrier substrate on the carrier substrate surface in at least some areas is described and a method for producing the implantable electrode configuration. The electrode has a metallic base plate having a planar top side and bottom side, including at least one structural element protruding orthogonally from the top side. The planar surface of the metallic base plate is oriented parallel to the carrier substrate surface and the metallic base plate is enclosed by the biocompatible polymer, except for a first surface area of the at least one structural element which faces the carrier substrate surface and is the freely accessible electrode surface.

Abstract: A printed circuit board according to an embodiment of the present invention includes a base film containing, as a main component, a polyimide and a conductive pattern disposed on at least one surface of the base film. The conductive pattern includes a copper particle bond layer which is fixed to the base film. An external transmittance for a wavelength of 500 nm in a conductive pattern non-formed region of the base film is 70% or less of an internal transmittance for a wavelength of 500 nm in a middle layer portion of the base film.

Abstract: A three-dimensional wiring board production method is provided that includes: a preparation step of preparing a resin film (1) having a breaking elongation of 50% or more; a first metal film formation step of forming a first metal film (3) on a surface of the resin film; a pattern formation step of performing patterning on the first metal film to form a desired pattern; a three-dimensional molding step of performing three-dimensional molding by heating and pressurizing the resin film; and a second metal film formation step of forming a second metal film (21) on the first metal film having a pattern formed thereon. In the first metal film formation step, metal is deposited in a particle state to form the first metal film in a porous state.

Abstract: A barrier layer is formed over electrically conductive contact pads on a substrate such as a wafer. A photoresist layer is applied over the barrier layer, and openings in the photoresist layer are filled with solder to form solder bumps. The barrier layer may be removed from within the openings prior to filling the openings with solder. The process is applicable to fine pitch architectures and chip size packaging substrates. The photoresist layer and portions of the barrier layer outside of the openings are removed following solder fill.

Abstract: A laminated substrate including a halogen-free epoxy resin composition. The halogen-free epoxy resin composition includes 100 parts by weight of a halogen-free naphthalene type epoxy resin, 10 to 25 parts by weight of a DOPO modified curing agent, 25 to 45 parts by weight of a cyanate resin, 35 to 60 parts by weight of bismaleimide, 45 to 65 parts by weight of a non-DOPO flame retardant, and 0.5 to 15 parts by weight of a curing accelerator. The laminated substrate of the present disclosure includes a halogen-free epoxy resin composition which has the characteristic of high transition temperature, so that the halogen-free epoxy resin composition has low dielectric constant, low dissipation factor, high heat resistance and high storage modulus.

Abstract: An electronic component includes a component main body including an embedded internal conductor and an outer electrode. The component main body includes an end surface on which the internal conductor is exposed, and a main surface that is continuous with the end surface and intersects with the end surface. The outer electrode includes an end surface covering portion connected to the internal conductor by covering at least a portion of the internal conductor exposed on the end surface, and a main surface covering portion that covers at least a portion of the main surface. At least a portion of an exposed surface of the main surface covering portion includes a Sn plating layer, and at least a portion of an exposed surface of the end surface covering portion includes a Sn—Ni layer.

Abstract: A printed circuit board according to an embodiment includes: an insulating layer; a first pad disposed on a first surface of the insulating layer; a first conductive layer disposed on the first pad and including gold (Au); a second pad disposed on a second surface of the insulating layer; and a second conductive layer disposed on the second pad and including gold (Au), wherein the first conductive layer is a conductive layer connected to a wire, the second conductive layer is a conductive layer connected to a solder, and the first conductive layer is thicker than the second conductive layer.

Abstract: A method to produce a substrate suitable for diffusion bonding is described. A flexible dielectric substrate is provided. An alkaline modification is applied to the dielectric substrate to form a polyamic acid (PAA) anchoring layer on a surface of the dielectric substrate. A Ni—P seed layer is electrolessly plated on the PAA layer. Copper traces are plated within a photoresist pattern on the Ni—P seed layer. A surface finishing layer is electrolytically plated on the copper traces. The photoresist pattern and Ni—P seed layer not covered by the copper traces are removed to complete the substrate suitable for diffusion bonding.

Abstract: A method is presented that improves reliability for the mechanical electrical connection formed between a grid array device, such as a pin grid array device (PGA) or a column grid array device (CGA), and a substrate such as a printed circuit board (PCB). Between adjacent PCB pads, the method increases a spacing pattern toward the periphery of the CGA, creating a misalignment between pads and columns. As part of the method, columns align with the pads, resulting in column tilt that increases from the center to the periphery of the CGA. An advantage of the method is that the column tilt reduces the amount of contractions and expansions of columns during thermal cycling, thereby increasing the projected life of CGA. Another advantage of the method is that it reduces shear stress, further increasing the projected life of the CGA.

Abstract: An anisotropic conductive film including conductive particles arranged uniformly in a single layer and capable of supporting fine-pitch connection is produced by: drying a coating film of a particle dispersion in which conductive particles are dispersed in a dilute solution of a thermoplastic resin that forms a coating after drying, whereby a conductive particle-containing layer is formed in which the coated conductive particles coated with the dried coating of the dilute solution of the thermoplastic resin and arranged in a single layer stick to the dried coating film; and laminating an insulating resin layer onto the conductive particle-containing layer.

Abstract: The conductive film is configured such that in a case in which a parameter Ca of a first-overlapped-portion in which a thin metal wire constituting a first-electrode and a thin metal wire constituting a second-electrode are superimposed in plan view is represented by Equation (1) of Ca=(A?wa*wb)/d, while setting an area of the first-overlapped-portion to A (?m2), line widths of the respective thin metal wires constituting the first-electrode and the second-electrode to wa and wb (?m), and a distance between the first-electrode and the second-electrode in a thickness direction of a substrate to d (?m), in a 5 mm×5 mm quadrangular region that is set to include a crossing region in which the first-electrode and the second-electrode cross each other in a conductive region, the parameter Ca of 90% or more of the first-overlapped-portions included in the region is 1.0 or less.

Abstract: A laminate is provided comprising a support, a resin layer, a metal layer, an insulating layer, and a redistribution layer. The resin layer comprises a photo-decomposable resin having light-shielding properties and has a transmittance of up to 20% with respect to light of wavelength 355 nm. The laminate is easy to fabricate and has thermal process resistance, the support is easily separated, and a semiconductor package is efficiently produced.

Abstract: An anisotropic conductive film including conductive particles arranged uniformly in a single layer and capable of supporting fine-pitch connection is produced by: drying a coating film of a particle dispersion in which conductive particles are dispersed in a dilute solution of a thermoplastic resin that forms a coating after drying, whereby a conductive particle-containing layer is formed in which the coated conductive particles coated with the dried coating of the dilute solution of the thermoplastic resin and arranged in a single layer stick to the dried coating film; and laminating an insulating resin layer onto the conductive particle-containing layer.

Abstract: An apparatus includes a substrate and a circuit trace having a predetermined pattern disposed on the substrate. A plurality of LEDs are connected to the substrate via the circuit trace. The predetermined pattern is arranged as an array of lines along a surface of the substrate, and the plurality of LEDs are distributed along the lines of the array.

Abstract: A semiconductor structure that includes a resistor that is located within an interconnect dielectric material layer of an interconnect level is provided. The resistor includes a diffusion barrier material that is present at a bottom of a feature that is located in the interconnect dielectric material layer. In some embodiments, the resistor has a topmost surface that is located entirely beneath a topmost surface of the interconnect dielectric material layer. In such an embodiment, the resistor is provided by removing sidewall portions of a diffusion barrier liner that surrounds a metal-containing structure. The removal of the sidewall portions of the diffusion barrier liner reduces the parasitic noise that is contributed to the sidewall portions of a resistor that includes such a diffusion barrier liner. Improved precision can also be obtained since sidewall portions may have a high thickness variation which may adversely affect the resistor's precision.

Abstract: A circuit board, a display device including the same, and a method of manufacturing a circuit board are provided. A circuit board includes a base substrate, a wiring line provided on the base substrate, a passivation layer provided on the wiring line, an elastic bump provided on the passivation layer, and a conductive layer provided on the elastic bump. The passivation layer includes a first opening and a second opening that expose a partial region of the wiring line, and the second opening is arranged in a region adjacent to the first opening.

Abstract: Provided herein is a carrier-attached copper foil having desirable fine circuit formability. The carrier-attached copper foil includes a carrier, an interlayer, and an ultrathin copper layer in this order. The maximum ridge height Sp as measured with a laser microscope according to ISO 25178 on the surface of the carrier-attached copper foil on the side of the ultrathin copper layer is 0.193 to 3.082 ?m.

Abstract: The present invention is to provide an anisotropic conductive film that excels in dispersing conductive particles and trapping the particles, and maintains conduction reliability even between narrow-pitched terminals. By a method for manufacturing an anisotropic conductive film containing conductive particles, the conductive particles are buried in grooves in a sheet having the grooves regularly formed in the same direction, the conductive particles are arranged, a first resin film having a thermo-setting resin layer formed on a stretchable base film is laminated on the surface of the sheet on the side of the grooves to transfer and attach the conductive particles to the first resin film, the first resin film is uniaxially stretched in a direction other than the direction perpendicular to the array direction of the conductive particles, and a second resin film is laminated.

Abstract: A multi-layer circuit board is formed by positioning a top sub having traces on at least one side to one or more pairs of composite layers, each composite layer comprising an interposer layer and a sub layer. Each sub layer which is adjacent to an interposer layer having an interconnection aperture, the interconnection aperture positioned adjacent to interconnections having a plated through via or pad on each corresponding sub layer. Each interposer aperture is filled with a conductive paste, and the stack of top sub and one or more pairs of composite layers are placed into a lamination press, the enclosure evacuated, and an elevated temperature and laminated pressure is applied until the conductive paste has melted, connecting the adjacent interconnections, and the boards are laminated together into completed laminated multi-layer circuit board.

Abstract: A computer-implemented method for determining a system layout of a photovoltaic (PV) system is implemented by a design automation computer system in communication with a memory. The method includes receiving a first selection of a system table, receiving a layout mode designation, identifying a system orientation, identifying a system spacing, receiving a layout detail designation, and applying a layout algorithm based on the first selection of a system table, the layout mode designation, the layout mode designation, the system orientation, the system spacing and the layout detail designation.

Abstract: Forming a semiconductor layer on a semiconductor substrate, a top surface of the semiconductor layer above a fin in a second region is higher than a top surface of the semiconductor layer in a first region, etching the semiconductor layer and a mask in the first region to expose a top surface of the semiconductor substrate to form a first stack, and etching the semiconductor layer and the mask in the second region to expose a top surface of the fin to form a second stack, epitaxially growing a semiconductor material on a top surface of the fin not covered by the second stack, recessing the first and second stack to expose a top surface of the semiconductor layer, a portion of the mask remains above the semiconductor layer in the first stack, top surfaces of each of the first and second stacks each are substantially flush with one another.

Abstract: A method of manufacturing an embedded circuit board includes: a first adhesive coated copper is provided, which includes a first copper layer pre-formed with at least two first positioning holes and a first adhesive layer formed on a surface of the first copper layer; at least one first electronic element are adhered to the first adhesive layer, electrodes of the first electronic element face their corresponding first positioning hole; a second adhesive coated copper and a semi-cured film are provided, the first adhesive coated copper and the second adhesive coated copper are pressed on opposite surfaces of the semi-cured film, thereby embedding the first electronic elements in the semi-cured film; the first adhesive layer is partially removed to define first holes for exposing electrodes of the first electronic element; the electrodes are electrically connected with the first copper layer. A circuit board made by the method is also provided.

Abstract: Disclosed herein are a printed circuit board, a manufacturing method thereof, and a semiconductor package including the printed circuit board. The printed circuit board includes a base substrate including a plurality of circuit patterns, a cavity formed above the base substrate, a pad embedded in the base substrate and being exposed through the substrate bottom surface of the cavity, and an electronic component mounted in the cavity and electrically connected to the pad. According to the present invention, a cavity having a predetermined depth is formed in a base substrate of a printed circuit board so as to mount an electronic component therein, such that a gap between an upper semiconductor package and a lower semiconductor package may be obtained even if pitches between the balls are decreased for high density and high performance of the upper semiconductor package in the manufacturing of a semiconductor package having a PoP structure.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed.

Abstract: The present disclosure provides a shorting bar structure and a method for manufacturing the same, and a Thin Film Transistor (TFT) substrate. The shorting bar structure comprises: a test wire; a test probe contact part connected to the test wire and configured to be able to contact with a test probe; and at least one PN junction structure located between the test wire and at least one wire under test, and configured to allow a test signal to be unidirectionally transmittable in a direction from the test wire to the wire under test.

Abstract: According to certain embodiments, a method by a wireless device is provided for transmitting uplink control information (UCI) on a serving cell on the unlicensed spectrum. The method includes formatting the UCI as a shortened control signalling transmission and transmitting the UCI formatted as the shortened control signalling transmission to a network node. The shortened control signalling transmission is transmitted during a transmission opportunity on the serving cell on the unlicensed spectrum without performing channel sensing.

Abstract: An anisotropic conductive film including conductive particles arranged uniformly in a single layer and capable of supporting fine-pitch connection is produced by: drying a coating film of a particle dispersion in which conductive particles are dispersed in a dilute solution of a thermoplastic resin that forms a coating after drying, whereby a conductive particle-containing layer is formed in which the coated conductive particles coated with the dried coating of the dilute solution of the thermoplastic resin and arranged in a single layer stick to the dried coating film; and laminating an insulating resin layer onto the conductive particle-containing layer.

Abstract: Composite material, where the matrix material and the additive are held together by covalently or non-covalently bound ligands. The linker unit between matrix and additive has the structure Ligand1-LinkerL-Ligand 2, wherein Ligand1 and Ligand2 are a bond or a chemical entity that is capable of binding covalently or non-covalently to a structural entity, such as a polymer matrix or the additive (ex. CNT, graphene, carbon nanofiber, etc), and LinkerL is a chemical bond or entity that links Ligand1 and Ligand2.

Abstract: A circuit substrate is provided with a base formed of ceramics. It includes a first face a second face; and a through hole penetrating from the first face to the second face; a through conductor: containing silver and copper as main components; disposed inside the through hole; and including a plurality of surfaces; and a metal layer in contact with at least one of the plurality of surfaces. The through conductor includes a eutectic region of silver and copper, disposed in a metal layer side of a diametrically center region of the through conductor; and a non-eutectic region of silver and copper, disposed in a central region of the diametrically center region of the through conductor.

Abstract: A semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader.

Abstract: A resin substrate includes a first portion including a plurality of resin sheets provided at one end in a stacking direction and a second portion including a plurality of resin sheets provided at the other end in the stacking direction. The thickness of the plurality of resin sheets is the same or substantially the same as the thickness of the first portion and the second portion. The density of planar conductor patterns of the first portion with respect to the volume of the first portion is lower than the density of planar conductor patterns of the second portion with respect to the volume of the second portion. The average of the diameters of the first interlayer connection conductor provided in the first portion is greater than the average of the diameters of the second interlayer connection conductor provided in the second portion.

Abstract: A membrane circuit structure with function expandability is provided. The membrane circuit structure includes a substrate, a lower circuit layer and a covering layer. The substrate includes a first region and at least one second region. The at least one second region is arranged near the first region. The lower circuit layer is printed on the first region. The lower circuit layer is made of a first conductive material. The covering layer is electroplated on a portion of a surface of the lower circuit layer. The covering layer is made of a second conductive material. At least one expansion line is welded on the corresponding second region, and electrically connected with the covering layer and a corresponding function-expanding unit.

Abstract: A stacked mounting structure and a method of manufacturing stacked mounting structure are provided. The stacked mounting structure includes a plurality of members provided with a mounting area which is necessary for installing and operating components to be mounted on at least one principal surface, and an area for connections for signal transfer for operating the components to be mounted, and an electroconductive member which is disposed on the area for connections between the mutually facing members, and a cross section of the electroconductive member is same as or smaller than the area for connections, and an end portion of the electroconductive member is extended from a principal surface of one member up to a principal surface of the other member, and a height of the electroconductive member regulates a distance of the mounting area.

Abstract: A composition for a bond ply, and a circuit subassembly that comprises such bond ply, are disclosed. The circuit subassembly can have a UL-94 rating of V-0. The composition of the bond ply layer comprises 25 to 45 volume percent of liquid resin; 10 to 40 weight percent of a bromine-containing or phosphorus-containing aromatic compound having a peak melting point of at least about 260° C.; and 5 to 35 volume percent inorganic filler.

Abstract: A radio frequency transmission structure couples a RF signal between a first and a second radiating elements arranged at a first and a second sides of a first dielectric substrate, respectively. The RF coupling structure comprises first and second coupling structures. Each coupling structure has a hole arranged through the first dielectric substrate, a first electrically conductive layer arranged on a first wall of the hole to electrically connect a first and a second signal terminals, a second electrically conductive layer arranged on a second wall of the hole opposite to the first wall to electrically connect a first and a second reference terminals. The first electrically conductive layer is separated from the second electrically conductive layer. The first and second coupling structures are symmetrically arranged with the first electrically conductive layers closer to each other than the second electrically conductive layers are to each other.