With Particular Material Patents (Class 174/256)
  • Patent number: 10412840
    Abstract: Systems and methods are provided to produce electromechanical interconnections within integrated circuits (ICs), printed circuit boards (PCBs) and between PCBs and other electronic components such as resistors, capacitors and integrated circuits. Elements include so-called “smart pins” or “neuro-pins” that facilitate electrical pathways in the dimension normal to the plane of a PCB. Smart pins or neuro-pins may be inserted using automated processes that do not require the high temperatures normally associated with soldering. Resultant circuits generally contain a large number of layers that are more compact and more readily constructed compared with conventional PCB-based circuitry.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: September 10, 2019
    Assignee: DOTSLAM, INC.
    Inventors: Lewis James Marggraff, Nelson G. Publicover, Blake Marggraff, Edward D. Krent, Marc M. Thomas
  • Patent number: 10410991
    Abstract: A method of and system for adhesive bonding. The method and system a) treat a surface of an element to be bonded to provide an adherent structure including one or more rubber compounds on the surface; b) place a polymerizable adhesive composition, including at least one photoinitiator and at least one energy converting material, in contact with the adherent structure and two or more components to be bonded to form an assembly, c) irradiated the assembly with radiation at a first wavelength, capable of conversion by the at least one energy converting material, to a second wavelength capable of activating the at least one photoinitiator to produce from the polymerizable adhesive composition a cured adhesive composition; and d) adhesively join the two or more components by way of the adherent structure and the cured adhesive composition.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: September 10, 2019
    Assignee: IMMUNOLIGHT, LLC
    Inventors: Zakaryae Fathi, Frederic A. Bourke, Jr., Harold Walder
  • Patent number: 10363602
    Abstract: Metal nanoparticles according to the present invention have at least a bimodal size distribution in which the ratio obtained by dividing the area of a first peak, which has the smallest median size on the basis of the median size of peaks in the size distribution of the metal nanoparticles, by the total area of all peaks constituting the size distribution meets 0.4-0.8, and are capped with a capping layer containing an organic acid.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: July 30, 2019
    Assignee: KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGY
    Inventors: Young Min Choi, Eun Jung Lee, Sun Ho Jeong, Yeong Hui Seo, Beyong Hwan Ryu, Su Yeon Lee
  • Patent number: 10356916
    Abstract: A printed circuit board and a method of manufacturing the same are provided. The printed circuit board includes an inner layer including at least one insulating layer and wiring parts, and outer layers disposed on opposing sides of the inner layer, the outer layers including reinforcing layers and wiring parts, the reinforcing layers having a greater degree of rigidity than the insulating layer.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: July 16, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Han Kim, Sang Yul Ha, Sung Han Kim, Kyung Ho Lee, Seok Hwan Ahn, Myung Sam Kang
  • Patent number: 10342129
    Abstract: A substrate includes an insulation layer including a glass cloth impregnated with a resin, and a through hole having a hole included in the insulation layer and plating formed in an inner surface of the hole, where a location, intersecting with the glass cloth, of an outer circumferential portion of the through hole has a recessed portion recessed toward an outside of the hole.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: July 2, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Shigeo Iriguchi, Takahiro Kitagawa, Mitsunori Abe, Shigeru Sugino, Nobuo Taketomi, Kiyoyuki Hatanaka, Ryo Kanai
  • Patent number: 10300700
    Abstract: An inkjet printhead includes: a rigid elongate carrier having an ink supply channel and a lower surface having a plurality of printhead chips mounted thereon; a rigid PCB attached to the lower surface of the carrier, the PCB extending a length of the carrier and projecting laterally beyond a sidewall of the carrier; a lead retainer attached to the sidewall of the carrier; and a plurality of leads extending upwardly from contact pads positioned along a longitudinal edge portion of the PCB, each lead being secured to the sidewall of the carrier via the lead retainer. The PCB supplies power and data to the printhead chips via electrical connections between the PCB and the printhead chips.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: May 28, 2019
    Assignee: Memjet Technology Limited
    Inventors: Jason Thelander, David Burke, Andrew Thomas
  • Patent number: 10297937
    Abstract: A composite flexible printed wiring board includes a first flexible printed wiring board having an insulating layer, conductor layers and a first metal block fitted in a hole penetrating through the conductor layers and insulating layer, and a second flexible printed wiring board having an insulating layer, conductor layers and a second metal block fitted in a hole penetrating through the conductor layers and insulating layer. The first flexible printed wiring board and the second flexible printed wiring board have a welded portion formed by welding the first metal block and the second metal block and joining the first metal block and the second metal block such that the welded portion is joining the first flexible printed wiring board and the second flexible printed wiring board.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: May 21, 2019
    Assignee: IBIDEN CO., LTD.
    Inventors: Takahisa Hirasawa, Takayuki Furuno
  • Patent number: 10297564
    Abstract: A semiconductor package includes a semiconductor die, a substrate for supporting the semiconductor die, an encapsulant covering the semiconductor die and at least part of the substrate, and a die attach material attaching the semiconductor die to the substrate. The die attach material includes molecules having a first functional group with at least one free electron pair and a second functional group chemically reacted or reactable with the encapsulant in a way that promotes adhesion with the encapsulant. A corresponding method of manufacturing the semiconductor package is also described.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: May 21, 2019
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Georg Meyer-Berg
  • Patent number: 10279055
    Abstract: Power supply unit, in particular for a sterilization device, comprising at least one electric component, wherein, at least one of the electric components is at least partly covered with a solid insulation layer, wherein the solid insulation layer is adapted to provide an electric insulation.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: May 7, 2019
    Assignee: TETRA LAVAL HOLDINGS & FINANCE S.A.
    Inventor: Iosif Izrailit
  • Patent number: 10278289
    Abstract: A resin circuit board includes a multilayer body, mounting land conductors, and second components. The multilayer body includes thermoplastic resin layers laminated together. The mounting land conductors are provided on a front surface of the multilayer body, and terminal conductors of a first component are bonded to the mounting land conductors by a thermal bonding method. The second components are disposed in the multilayer body and each has a modulus of elasticity greater than that of the multilayer body. When the multilayer body is seen in plan view, the second components are arranged such that a straight line connecting the second components passes through the center of gravity of the first component and such that the second components are superposed with the mounting land conductors.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: April 30, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kuniaki Yosui, Shigeru Tago, Masaki Kawata
  • Patent number: 10264672
    Abstract: A glass substrate includes a plurality of through holes that penetrate from a first surface to a second surface of the glass substrate. Each through hole has an upper aperture with a first diameter on the first surface and a lower aperture with a second diameter on the second surface. For each of ten through holes selected from the plurality of through holes, a side wall length is obtained from the first and second diameters and the thickness of the glass substrate, and an R value is obtained by dividing the side wall length by the thickness of the glass substrate. The R values fall within a range of 1 to 1.1. A B value, obtained from dividing a difference between the greatest R value and the smallest R value by an average of the R values followed by multiplication with 100, is 5% or less.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: April 16, 2019
    Assignee: AGC Inc.
    Inventors: Shigetoshi Mori, Motoshi Ono, Mamoru Isobe, Kohei Horiuchi
  • Patent number: 10209619
    Abstract: A semiconductor device production composition comprises a product obtained by mixing a metal compound and a compound represented by Formula (1) in a first organic solvent, and a second organic solvent. R and R? each independently represent a hydrogen atom, a linear or cyclic alkyl group having a carbon number of 2 to 20, a linear or cyclic alkylcarbonyl group having a carbon number of 2 to 20, an aryl group having a carbon number of 6 to 20, or an aryloxy group having a carbon number of 6 to 20, and part of the hydrogen atoms in the cyclic alkyl, cyclic alkylcarbonyl, aryl, or aryloxy group are substituted or unsubstituted.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: February 19, 2019
    Assignee: JSR CORPORATION
    Inventors: Hisashi Nakagawa, Ryuichi Saitou, Shunsuke Kurita, Tatsuya Sakai
  • Patent number: 10194537
    Abstract: A printed circuit board and method of manufacturing same, the printed circuit board comprising a stack of layers. The stack of layers being comprised of alternating circuit layers and insulating layers that are laminated together. The stack of layers includes an area with resin cured to a degree. The area has a coefficient of thermal expansion that is dependent, at least in part, on the degree of curing of the resin.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: January 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bruce J. Chamberlin, Joseph Kuczynski, Paula M. Nixa
  • Patent number: 10188005
    Abstract: A control unit device for a motor vehicle includes a circuit board, on which a plurality of electronic components are disposed. The electronic components are electrically coupled to one another by conductor tracks on the circuit board. A substantially gas-impermeable cover is materially joined or bonded to the circuit board in such a way that the cover, together with the circuit board, forms a closed cavity in which the electronic components and the associated conductor tracks are located. A method for producing the control unit device is also provided.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: January 22, 2019
    Assignee: Conti Temic microelectronic GmbH
    Inventors: Andreas Albert, Gerhard Bauer, Juergen Henniger, Matthias Keuten, Michael Novak, Bernhard Schuch, Matthias Wieczorek
  • Patent number: 10176776
    Abstract: Provided is a display device, including: a driving circuit including a first output terminal group including at least one gate signal output terminal, and a second output terminal group including at least one source signal output terminal; and a plurality of gate lead-out lines configured to transmit a gate signal to a plurality of gate lines, in which each of the plurality of gate lines is electrically connected to at least one of the gate lead-out lines, and the first output terminal group is arranged between two adjacent second output terminal groups.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: January 8, 2019
    Assignee: Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Tetsuya Kawamura, Hironori Yasukawa
  • Patent number: 10168436
    Abstract: Water soluble, low alpha particle emission, electrically conductive coatings and techniques for formation thereof are provided. In one aspect, a method for forming an electrically-conductive coating on a substrate includes the steps of: forming an aqueous solution of a water soluble polymer (e.g., a polyvinylpyrrolidinone polymer or copolymer); adding electrically conductive filler particles to the aqueous solution above a percolation threshold to form a mixture; and depositing the mixture onto the substrate to form a low alpha particle emitting, electrically-conductive coating on the substrate, wherein the coating blocks alpha particles from being emitted from the substrate. An article and an alpha particle detector having a surface(s) thereof covered with the coating are also provided.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Gaynes, Jeffrey D. Gelorme, Michael S. Gordon
  • Patent number: 10102468
    Abstract: The invention relates to a method for producing an intermediate device comprising an electronic module, said intermediate device being used to receive at least one film or portion of a film or covering layer, said device comprising: a supporting body; at least one area for the interconnection of an electric circuit, borne by the supporting body; and an electronic module connected to said interconnection area by an anisotropic connection material, said material being compressed between said area and the module. The method comprises the implementation of a means for maintaining the compressed state of said anisotropic material and/or a means for isolating said material from the outside of the supporting body.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: October 16, 2018
    Assignee: GEMALTO SA
    Inventors: Christophe Bousquet, Yves Cuny, Brigitte Lacaze, Antoine Bajolle, Sébastien Gaspari, Frédérick Seban
  • Patent number: 10070530
    Abstract: An electronic component includes a substrate including a first principal surface, a second principal surface positioned on a side opposite to the first principal surface, a first side surface that connects the first principal surface and the second principal surface and that extends along a first direction, a second side surface that connects the first principal surface and the second principal surface and that extends along a second direction intersecting the first direction, and a corner portion that connects the first side surface and the second side surface and that has a curved surface curved outwardly, and a chip arranged at the first principal surface of the substrate.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: September 4, 2018
    Assignee: ROHM CO., LTD.
    Inventors: Motohiro Toyonaga, Yasuhiro Fuwa, Mamoru Yamagami, Isamu Nishimura
  • Patent number: 10049898
    Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material around the integrated circuit die mounting region. An interconnect structure is over the molding material and the integrated circuit die mounting region. A protection pattern is in a perimeter region of the package around the interconnect structure. The protection pattern includes a first conductive feature that is vertical within the package near a second conductive feature. The first conductive feature has a first width, and the second conductive feature has a second width. The second width is greater than the first width.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hsien-Wei Chen, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Wei-Cheng Wu, Chien-Fu Tseng
  • Patent number: 10039180
    Abstract: A dielectric tape suitable for use in an electronic device is provided. A dielectric slip composition comprises an organic vehicle and a dielectric glass composition comprising at least about 20 wt % and no more than about 50 wt % silicon dioxide, based upon 100% total weight of the glass composition, at least about 10 wt % and no more than about 50 wt % alkali metal oxides, based upon 100% total weight of the glass composition, and at least about 1 wt % and no more than about 10 wt % of at least one transition metal oxide. A method of forming an electronic device is also provided. The method includes the steps of applying at least one dielectric tape to at least one non-planar surface of a substrate, and subjecting the at least one dielectric tape to one or more thermal treatment steps to form a dielectric layer.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: July 31, 2018
    Assignee: Heraeus Precious Metals North America Conshohocken LLC
    Inventors: Samson Shahbazi, Steven Grabey, Mark Challingsworth, Ryan Persons
  • Patent number: 10029438
    Abstract: The present invention relates to a thermosetting resin composition, which comprises: (A) cyanate ester compound and/or cyanate ester prepolymer; and (B) polyphosphonate ester and/or phosphonate-carbonate copolymer. The thermosetting resin composition provided by the present invention has low dielectric constant and dielectric loss tangent. The prepreg and copper clad laminate made from the above-mentioned thermosetting resin composition have excellent dielectric properties and wet-heat resistance, UL94 V-0 flame resistance, and good processability.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: July 24, 2018
    Assignee: SHENGYI TECHNOLOGY CO., LTD.
    Inventors: Xianping Zeng, Nana Ren
  • Patent number: 10005911
    Abstract: Provided is a curable composition for a printed wiring board, which composition exhibits high physical strength as a coating film in terms of solder heat resistance, pencil hardness and the like and in which the components contained therein are not likely to precipitate in long-term storage even when the composition is configured to have a low viscosity and thereby made applicable to ink-jet printing, spin-coating and the like. The curable composition for a printed wiring board is characterized by comprising (A) a filler having a specific gravity of 3 or less, (B) a hydroxyl group-containing (meth)acrylate compound and (C) a photopolymerization initiator. The (A) filler having a specific gravity of 3 or less is preferably an inorganic filler.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: June 26, 2018
    Assignee: TAIYO INK MFG. CO., LTD.
    Inventors: Masayuki Shimura, Yoshiyuki Furuta, Masao Yumoto
  • Patent number: 9992879
    Abstract: A packaging substrate includes a first dielectric layer, a first wiring layer, a first conductive pillar layer, a second dielectric layer, a second wiring layer, an electrical pad layer, and a third dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface, plural openings, and a wall surface that faces at least one of the openings. The first wiring layer is located on the first surface and the wall surface. A portion of the first wiring layer on an edge of the wall surface adjacent to the second surface extends in a direction away from the wall surface. The first conductive pillar layer is located on a portion of the first wiring layer. The second dielectric layer is located on the first surface, the first wiring layer, and in the openings.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: June 5, 2018
    Assignee: Phoenix Pioneer technology Co., Ltd.
    Inventors: Che-Wei Hsu, Shih-Ping Hsu, Pao-Hung Chou
  • Patent number: 9980384
    Abstract: The circuit board includes a ceramic sintered body and a metal wiring layer provided on at least one primary surface thereof with a glass layer interposed therebetween, and when the cross section of the circuit board perpendicular to the primary surface of the ceramic sintered body is viewed, the ratio of the length of an interface between the glass layer and the metal wiring layer to a length of the glass layer in a direction along the primary surface is 1.25 to 1.80.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: May 22, 2018
    Assignee: KYOCERA Corporation
    Inventors: Yoshio Ohashi, Kunihide Shikata
  • Patent number: 9951231
    Abstract: Disclosed herein are copper-containing (Cu-containing) conductive pastes, copper (Cu) electrodes formed by firing the Cu-containing conductive paste over a substrate, and articles comprising a structural element with such Cu electrodes, wherein, the Cu-containing conductive paste contains a powder of coated Cu particles and glass frit dispersed in an organic medium.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: April 24, 2018
    Assignee: E I DU PONT DE NEMOURS AND COMPANY
    Inventor: Minfang Mu
  • Patent number: 9954273
    Abstract: An electronic device may be provided with wireless circuitry that includes antennas. An antenna may be formed from metal traces on a dielectric antenna carrier. The antenna carrier may be formed by molding a layer of plastic onto the surface of a foam member. The foam member may have a low dielectric constant to enhance antenna performance and may be formed from a stiff closed cell plastic foam material. Heat and pressure may be used to attach the layer of plastic to the surface of the foam member without adhesive. A laser may be used to selectively expose portions of the plastic layer to laser light. The plastic layer may include additives that sensitize the plastic layer to light exposure. Electroplated metal traces for the antenna may be formed on the exposed portions of the plastic layer while leaving other portions of the plastic layer uncovered with metal.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: April 24, 2018
    Assignee: Apple Inc.
    Inventors: Boon W. Shiu, Chun-Lung Chen, Erdinc Irci
  • Patent number: 9917025
    Abstract: A printed wiring board includes a first circuit board having a first surface and a second surface, and a second circuit board having a third surface and a fourth surface and having a mounting area on the third surface of the second circuit board. The first circuit board is laminated on the third surface of the second circuit board such that the first surface of the first circuit board is in contact with the third surface of the second circuit board, the first circuit board includes reinforcing material and has an opening portion exposing the mounting area of the second circuit board, and the first circuit board and the second circuit board are formed such that a ratio H1/h1 is in a range that is greater than 0.75 and smaller than 2.4, where H1 represents a thickness of the first circuit board and h1 represents a thickness of the second circuit board.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: March 13, 2018
    Assignee: IBIDEN CO., LTD.
    Inventors: Kota Noda, Takeshi Furusawa
  • Patent number: 9905339
    Abstract: In a conductive film forming method using photo sintering, a conductive film having low electric resistance is easily formed. Disclosed is a conductive film forming method in which a conductive film is formed using a photo sintering, which includes the steps of: forming a liquid film made of a copper particulate dispersion on a substrate, drying the liquid film to form a copper particulate layer, subjecting the copper particulate layer to photo sintering to form a conductive film, attaching a sintering promoter to the conductive film, and further subjecting the conductive film having the sintering promoter attached to photo sintering. The sintering promoter is a compound which removes copper oxide from metallic copper. Thereby, the sintering promoter removes a surface oxide film of copper particulates in the conductive film.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: February 27, 2018
    Assignee: ISHIHARA CHEMICAL CO., LTD.
    Inventors: Yuichi Kawato, Kazushige Miyamoto, Yusuke Maeda, Tomio Kudo
  • Patent number: 9907166
    Abstract: The object is to provide a resin composition for a printed circuit board capable of realizing a printed circuit board that not only has heat resistance and flame retardancy but also is excellent in heat resistance after moisture absorption. The resin composition is a resin composition for a printed circuit board containing a cyanate ester compound (A) obtained by cyanation of a naphthol-dihydroxynaphthalene aralkyl resin or a dihydroxynaphthalene aralkyl resin, and an epoxy resin (B).
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: February 27, 2018
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Takashi Kobayashi, Kentaro Takano
  • Patent number: 9889471
    Abstract: A process for application of metal on a substrate surface comprises applying a mixture of a solvent, a polymerizable monomer, and a photoinitiator on a substrate surface, wherein the photoinitiator does not form two phases together with the monomer and the solvent, i.e. it forms an amorphous mixture without any crystals. The monomer is able to polymerize to a polymer comprising at least one carboxylic group. Thereafter the solvent is evaporated. Polymerization is induced by irradiating the applied dried mixture. Ions are applied and reduced to metal and thereafter further metal can be deposited. The method can be used in industrial processes, both 2D and 3D surfaces can be coated with metal. Materials sensitive to standard grafting chemicals and/or polymers containing halogen atoms can be coated.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: February 13, 2018
    Assignee: Cuptronic Technology Ltd.
    Inventors: Sven Göthe, Björn Atthoff
  • Patent number: 9883595
    Abstract: A power electronic substrate includes a metallic baseplate having a first and second surface opposing each other. An electrically insulative layer also has first and second surfaces opposing each other, its first surface coupled to the second surface of the metallic baseplate. A plurality of metallic traces each include first and second surfaces opposing each other, their first surfaces coupled to the second surface of the electrically insulative layer. At least one of the metallic traces has a thickness measured along a direction perpendicular to the second surface of the metallic baseplate that is greater than a thickness of another one of the metallic traces also measured along a direction perpendicular to the second surface of the metallic baseplate. In implementations the electrically insulative layer is an epoxy or a ceramic material. In implementations the metallic traces are copper and are plated with a nickel layer at their second surfaces.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: January 30, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng Lin, Sadamichi Takakusaki
  • Patent number: 9875890
    Abstract: A system and method for depositing a metal dielectric film includes arranging a substrate in a plasma enhanced chemical vapor deposition (PECVD) processing chamber; supplying a carrier gas to the PECVD processing chamber; supplying a dielectric precursor gas to the PECVD processing chamber; supplying a metal precursor gas to the PECVD processing chamber; creating plasma in the PECVD processing chamber; and depositing a metal dielectric film on the substrate at a process temperature that is less than 500° C.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: January 23, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Fayaz Shaikh, Sirish Reddy
  • Patent number: 9875957
    Abstract: A wiring substrate includes a first wiring structure and a second wiring structure. The first wiring structure includes a first insulating layer, which covers a first wiring layer, and a via wiring. A first through hole of the first insulating layer is filled with the via wiring. The second wiring structure includes a second wiring layer and a second insulating layer. The second wiring layer is formed on an upper surface of the first insulating layer and an upper end surface of the via wiring. The second wiring layer partially includes a roughened surface. The second insulating layer is stacked on the upper surface of the first insulating layer and covers the second wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The roughened surface of the second wiring layer has a smaller surface roughness than the first wiring layer.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: January 23, 2018
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Noriyoshi Shimizu, Yusuke Gozu, Jun Furuichi, Akio Rokugawa, Takashi Ito
  • Patent number: 9842977
    Abstract: An electrical circuit board assembly (ECBA) preferably having at least one LED component and having a substrate that includes a plurality of raised pads formed such that open channels are formed therebetween, and such that the upper surfaces of the pads are preferably substantially coplanar. Such intra-pad channels facilitate heat transfer and cooling of the substrate and the ECBA. Further, such raised pads provide for alternate methods of electrically conductive track manufacturing so as to avoid the necessity of chemical etching which requires the use of hazardous toxic chemicals. Such alternate methods of electrically conductive track construction include adhesive conductive sheet application, conductive ink screen printing, and conductive ink painting.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: December 12, 2017
    Inventor: Raul A. Klein
  • Patent number: 9832867
    Abstract: A device having embedded metallic structures in a glass is provided. The device includes a first wafer, at least one conductive trace, a planarized insulation layer and a second wafer. The first wafer has at least one first wafer via that is filled with conductive material. The at least one conductive trace is formed on the first wafer. The at least one conductive trace is in contact with the at least one first wafer via that is filled with the conductive material. The planarized insulation layer is formed over the first wafer and at least one conductive trace. The planarized insulation layer further has at least one insulation layer via that provides a path to a portion of the at least one conductive trace. The second wafer is bonded to the planarized insulation layer.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: November 28, 2017
    Assignee: Medtronic, Inc.
    Inventors: John K. Day, David A. Ruben, Michael S. Sandlin
  • Patent number: 9832866
    Abstract: A multilayered substrate includes unit substrates laminated in a direction of thickness thereof, and the unit substrates include a photosensitive insulating layer, a conductive pattern disposed in the photosensitive insulating layer, and a bump penetrating into the photosensitive insulating layer and providing an interlayer connection to the conductive pattern.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: November 28, 2017
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seok-Hwan Ahn, Mi-Sun Hwang, Young-Gwan Ko, Jong-Seok Bae, Myung-Sam Kang
  • Patent number: 9831147
    Abstract: In an embodiment, an electronic component includes a first dielectric layer including an organic component having a decomposition temperature of at least 180° C., a semiconductor die embedded in the first dielectric layer, a second dielectric layer arranged on a first surface of the first dielectric layer, the second dielectric layer including a photo definable polymer composition and defining two or more discrete openings having conductive material, and a first substrate arranged on the second dielectric layer and on the conductive material. One or more contact pads are arranged on an outermost surface of the first substrate.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: November 28, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Standing
  • Patent number: 9825209
    Abstract: A method for manufacturing an electronic component package. The method includes (i) providing a package precursor in which an electronic component is embedded such that an electrode of the electronic component is exposed at a surface of a sealing resin layer; (ii) forming a first metal plating layer such that the first metal plating layer is in contact with the exposed surface of the electrode of the electronic component; (iii) disposing a metal foil in face-to-face spaced relationship with respect to the first metal plating layer; and (iv) forming a second metal plating layer. In step (iv), the second metal plating layer is formed so as to fill a clearance between the first metal plating layer and the metal foil, thereby integrating the metal foil, the first metal plating layer and the second metal plating layer with each other.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: November 21, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kazuma Mima, Seiichi Nakatani, Yoshihisa Yamashita, Koji Kawakita, Susumu Sawada
  • Patent number: 9824798
    Abstract: A resistor element includes a base substrate, a resistor layer disposed on one surface of the base substrate, a first electrode layer and a second electrode layer disposed on the resistor layer spaced apart from each other, a third electrode layer disposed between the first electrode layer and the second electrode layer to be spaced apart from the first electrode layer and the second electrode layer and being thicker than each of the first electrode layer and the second electrode layer, and first to third plating layers disposed on the first to third electrode layers, respectively.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: November 21, 2017
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jung Min Nam, Jea Hoon Lee, Young Key Kim, Hae In Kim
  • Patent number: 9812446
    Abstract: An electronics apparatus including a first substrate having a first surface and a second surface, a first switch connected to a second switch and soldered in series on the first surface of the first substrate creating a connection to allow switching between the first switch and the second switch at high frequency, an insulation having a third surface attached to the second surface of the first substrate, and a second substrate having a pocket of low permittivity located between the first switch and the second switch on a fourth surface of the insulation, the fourth surface being opposite to the third surface where the first switch and the second switch are located.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: November 7, 2017
    Assignee: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC.
    Inventors: Jongwon Shin, Chi-Ming Wang
  • Patent number: 9806026
    Abstract: The present disclosure relates to a structure and method to create a self-repairing dielectric material for semiconductor device applications. A porous dielectric material is deposited on a substrate, and exposed with treating agent particles such that the treating agent particles diffuse into the dielectric material. A dense non-porous cap is formed above the dielectric material which encapsulates the treating agent particles within the dielectric material. The dielectric material is then subjected to a process which creates damage to the dielectric material. A chemical reaction is initiated between the treating agent particles and the damage, repairing the damage. A gradient concentration resulting from the consumption of treating agent particles by the chemical reaction promotes continuous diffusion the treating agent particles towards the damaged region of the dielectric material, continuously repairing the damage.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: October 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Tien-I Bao
  • Patent number: 9781844
    Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: October 3, 2017
    Assignee: SANMINA CORPORATION
    Inventors: Shinichi Iketani, Dale Kersten
  • Patent number: 9774067
    Abstract: A plasma power limiter fabricated using wafer-level fabrication techniques with other circuit elements. The power limiter includes a signal substrate having a first side and a second side, an input signal line formed on the first side, a signal transmission line formed on the second side and an output signal line formed on the first side. The power limiter also includes a ground substrate having a first side and a second side, and being bonded to the signal substrate to form a sealed cavity including an ionizable gas therebetween. The ground substrate includes a ground metal layer formed on the second side. A signal propagating on the input signal line at a power level greater than a threshold power level generates a voltage potential across the cavity that ionizes the gas and generates a plasma discharge, and limits power of the output signal coupled to the output signal line.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: September 26, 2017
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Benjamin D. Poust, Michael Conrad Battung, Dino Ferizovic, Patty P. Chang-Chien
  • Patent number: 9758845
    Abstract: Microelectronic substrates having copper alloy conductive routes to reduce warpage due to differing coefficient of thermal expansion of the components used to form the microelectronic substrates. In one embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper and an alloying metal of tungsten, molybdenum, or a combination thereof. In another embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper, an alloying metal of tungsten, molybdenum, or a combination thereof, and a co-deposition metal of nickel, cobalt, iron, or a combination thereof. In still another embodiment, the copper alloy conductive routes may have copper concentrations which are graded therethrough, which may enable better pattern formation during a subtractive etching process used to form the copper alloy conductive routes.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: September 12, 2017
    Assignee: Intel Corporation
    Inventors: Robert A. May, Sri Ranga Sai Boyapati, Amruthavalli P. Alur, Daniel N. Sobieski
  • Patent number: 9728695
    Abstract: A mount substrate includes: an insulation substrate containing resin and glass; connection conductors formed on a surface of the insulation substrate; a first white resist layer that covers the connection conductors; and a second white resist layer that covers the first white resist. Each of the connection conductors includes a copper foil and a plating layer partly formed on the copper foil. The plating layer is formed of metal having oxidation-resistant and corrosion-resistant characteristics higher than those of copper. The first white resist layer is formed with first openings that respectively expose the plating layers of the connection conductors. The second white resist layer covers a periphery of each plating layer of the connection conductors in planar view.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: August 8, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kosuke Takehara, Hisaki Fujitani, Naoki Tagami, Toshiaki Kurachi
  • Patent number: 9711456
    Abstract: A semiconductor device includes a metal-containing structure such as a copper-containing wire or plug and a composite capping layer formed over the metal-containing structure. The composite capping layer includes a manganese-containing layer disposed over the metal-containing structure, a silicon-containing low-k dielectric layer disposed over the manganese-containing layer, and an intermediate layer between the manganese-containing layer and the silicon-containing low-k dielectric layer. The intermediate layer is the reaction product of the manganese-containing layer and the silicon-containing low-k dielectric layer.
    Type: Grant
    Filed: December 19, 2015
    Date of Patent: July 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Donald F. Canaperi, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini
  • Patent number: 9699916
    Abstract: A method of manufacturing a wiring substrate according to the present invention includes a step of forming a wiring layer including connection terminals on a first insulating layer; a step of forming a second insulating layer on the wiring layer and on the first insulating layer; a step of forming electrically insulative dummy portions separated from the wiring layer on the first insulating layer through patterning of the second insulating layer; a step of forming a third insulating layer on the wiring layer, on the dummy portions, and on the first insulating layer; and a step of forming openings in the third insulating layer for exposing the connection terminals in such a manner that upper end portions of the connection terminals protrude from the third insulating layer, and lower end portions of the connection terminals are embedded in the third insulating layer.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: July 4, 2017
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventor: Takahiro Hayashi
  • Patent number: 9661759
    Abstract: Provided is a printed circuit board, including: a core substrate including an internal circuit pattern on an upper surface or a lower surface; electronic devices which are formed to pass through the core substrate; an external insulating layer which covers the internal circuit pattern and the electronic devices; and an external circuit pattern which is formed on an upper surface of the external insulating layer, wherein a lower surface of the electronic devices protrudes from the lower surface of the core substrate to a lower part. Accordingly, in the embedded printed circuit board in which the electronic devices are embedded, when the electronic devices are mounted, because the insulating layer is formed regardless of a thickness of the electronic devices, the printed circuit board having a desired thickness regardless of the thickness of the electronic devices can be formed.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: May 23, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Ji Su Kim, Ki Do Chun, Kyu Won Lee, Sang Myung Lee
  • Patent number: 9659844
    Abstract: An integrated circuit device includes a semiconductor substrate with a top surface, a bottom surface opposite the top surface and an intermediate portion positioned between the top and bottom surfaces. The device also includes interior substrate surfaces defined by at least one void extending from the bottom surface to the intermediate portion.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: May 23, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rajarshi Mukhopadhyay, Daniel N. Carothers, Benjamin Cook
  • Patent number: 9639214
    Abstract: A chip-on-glass device comprises a chip-on-glass substrate, a metal layer, and a plurality of chip-on-glass connection bumps. The metal layer comprises a plurality of passive jumper routing traces. The plurality of chip-on-glass connection humps is coupled with passive jumper routing traces of the plurality of passive jumper routing traces.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: May 2, 2017
    Assignee: Synaptics Incorporated
    Inventors: Jim Dunphy, Joseph Kurth Reynolds