Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same. In detail, according to a preferred embodiment of the present invention, the printed circuit board includes: an insulating layer; and a metal layer formed on the insulating layer, wherein in the metal layer, a ratio occupied by crystal orientations of (110) and (112) is 20 to 80%. By doing so, the preferred embodiment of the present invention provides a printed circuit board including the metal layer having different crystal orientations to minimize factors of hindering electrical characteristics such as electric conductivity and improve isotropy of mechanical properties and a method of manufacturing the printed circuit board.

Abstract: An interposer includes an insulating substrate, a photosensitive dielectric film, a conductive layer, and a conductive via. The insulating substrate includes a bottom surface and a top surface, and defines a receiving through hole extending through the bottom surface and the top surface. The photosensitive dielectric film is mounted on the bottom surface. The photosensitive dielectric film defines a through hole spatially corresponding to and communicating with the receiving through hole. The conductive layer is mounted on an end of the photosensitive dielectric film away from the insulating substrate. The conductive layer covers an end of the through hole. The conductive via is received in the receiving through hole and the through hole. The conductive via contacts and electrically connects to the conductive layer.

Abstract: According to the present disclosure, a manufacturing method of a fine wiring pattern is disclosed. The manufacturing method includes preparing a support member, forming a first layer on the support member by thick-film printing, and forming a second layer including Ag on the first layer by the thick-film printing. The method also includes forming a predetermined fine wiring pattern by performing an etching process upon the first layer and the second layer.

Abstract: An anisotropic conductive adhesive composite and film include a binder and conductive particles dispersed in the binder. The conductive particles include a copper core particle and a metal coating layer coated on a surface of the corresponding copper core particle.

Abstract: Disclosed herein is a printed circuit board, including: a substrate; a seed layer formed on the substrate; and a circuit pattern formed on the seed layer and formed so that a diameter of an upper portion thereof and a width of a lower portion thereof are equal to each other or a diameter of the lower portion is larger than that of the upper portion. Therefore, the printed circuit board according to a preferred embodiment of the present invention forms the circuit pattern having the lower portion having the diameter larger than that of the upper portion, such that the electrical signal loss may be decreased and separation of the circuit pattern may be prevented, thereby improving whole reliability of the board.

Abstract: The present invention relates to an adhesive substrate for forming a conductive pattern, which includes an adhesive substrate, and a precursor pattern of a conductive pattern, or a conductive pattern, provided on one side of the adhesive substrate, a method for preparing a conductive pattern using the adhesive substrate, a conductive pattern prepared using the adhesive substrate, and an electronic device including the conductive pattern.

Abstract: A metal circuit structure, a method for forming a metal circuit and a liquid trigger material for forming a metal circuit are provided. The metal circuit structure includes a substrate, a first trigger layer and a first metal circuit layer. The first trigger layer is disposed on the substrate and includes a first metal circuit pattern. The first metal circuit layer is disposed on the first circuit pattern and is electrically insulated from the substrate. The composition of the first trigger layer includes an insulating gel and a plurality of trigger particles. The trigger particles are at least one of organometallic particles, a chelation and a semiconductor material having an energy gap greater than or equal to 3 eV. The trigger particles are disposed in the insulating gel, such that the dielectric constant of the first trigger layer after curing is between 2 and 6.5.

Abstract: A patterned transparent conductive film is disclosed in the present invention, which includes a substrate, a first conductive layer, a second conductive layer, both the conductive layer includes a conductive area and an insulating area, the conductive area includes a metal mesh formed by a plurality of metal lines; the metal mesh is a buried metal mesh with random irregular grids, a probability density of the slope of the metal lines of the first conductive layer close to transverse direction is greater than that close to longitudinal direction, a probability density of the slope of the metal lines of the second conductive layer close to transverse direction is greater than that close to longitudinal direction, the two conductive layers are laminated and insulated in the thickness direction, the laminated metal meshes are evenly distributed, the light transmittance is increased and the conductivity is constant, the moire fringe is eliminated.

Abstract: A substrate structure includes a substrate and a filling material. The substrate has an upper surface, a lower surface, at least one first blind via and at least one second blind via. The substrate includes an insulation layer, a first copper foil layer and a second copper foil layer. The first copper foil layer and the second copper foil layer are respectively disposed on two opposite side surfaces of the insulation layer. The first blind via extends from the upper surface toward the second copper foil layer and exposes a portion of the second copper foil layer. The second blind via extends from the lower surface toward the first copper foil layer and exposes a portion of the first copper foil layer. The filling material is filled inside of the first blind via and the second blind via and covers the upper surface and the lower surface of the substrate.

Abstract: A laminate substrate may include a slug positioned within a cavity of a laminate core. The laminate substrate may have routing layers on either side of the laminate core, at least one of which is coplanar with an outer side of the slug. A capping layer may then be applied to the laminate substrate which is directly coupled with the slug and the routing layer. In embodiments, a dielectric layer may be coupled with the capping layer, and an additional routing layer may be coupled with the dielectric layer. Therefore, the routing layer may be an “inner” routing layer that is coplanar with, and coupled with, the slug.

Abstract: The invention relates to a layered body, in particular one with two sheets of electric functional layers, as well as a use of this layered body for example in a touch screen with improved resolution. By changing the grid structure at the intersection areas a moiré effect can be avoided by superimposition of the patterns.

Abstract: A touch panel includes a touch sensor layer including a first transparent electrode and a second transparent electrode, wherein an arrangement direction of the first transparent electrode can be perpendicular to that of the second transparent electrode, and both of the first and second transparent electrodes include two transparent metallic patterns which are stacked and electrically connected to each other.

Abstract: The object of the present invention is to provide a multi-layer wiring board which is easy to adjust the characteristic impedance and is able to adapt to the narrow-pitch tendency of terminals, and a process for manufacturing the same.

Abstract: A printed circuit board includes: a substrate; a land that is disposed on a surface of the substrate, and includes a central portion and a plurality of extended portions, the central portion having the same shape and the same size as a land of a surface mount device, and the extended portions being up-and-down symmetry and right-and-left symmetry with respect to a straight line which passes through the center of the central portion; gaps that are disposed on the surface of the substrate, each of the gaps being disposed on a periphery of the central portion and between the extended portions; and a resist that is disposed on the surface of the substrate, and has an opening portion formed at a position corresponding to the central portion and the gaps.

Abstract: A high-frequency module has a multilayer board formed by laminating a plurality of sheets made of a thermoplastic resin material and subjecting the laminated sheets to thermocompression bonding, and an IC chip placed in a cavity provided in the multilayer board. A gap is provided between a side of the IC chip and an inner wall of the cavity. The multilayer board includes a via-hole conductor provided near the inner wall of the cavity for preventing the resin sheets from being softened and flowing into the cavity upon thermocompression bonding.

Abstract: Printed circuit boards are provided. The printed circuit board includes an insulation layer, an interconnection portion and a metal layer. The insulation layer has a flat plate shape and includes a top surface and a bottom surface. The interconnection portion is disposed on at least one of the top and bottom surfaces of the insulation layer. The interconnection portion includes a plurality of interconnection patterns. The metal layer covers the plurality of interconnection patterns of the interconnection portion. Related semiconductor packages are also provided.

Abstract: The present invention provides a new method for manufacturing an electronic part, which is capable of reducing the number of steps of superpose-printing, achieving positional accuracy (alignment accuracy) of precise superposed patterns, and layering with substantially no difference in level, thereby improving productivity and dimensional accuracy and eliminating defects. The method for manufacturing an electronic part includes the steps of forming a composite ink pattern layer on a releasing surface of a transfer plate using a relief offset method, and then simultaneously reversely transferring the composite ink pattern layer to a printing object. Various organic transistor elements are formed by combining a conductive ink, an insulating ink, and an ink containing a semiconductor.

Abstract: A transparent electrical conductor with a transparent substrate and an electrically conductive layer on the substrate are provided. The conductive layer has a plurality of electrically conductive nanoscale additives. The additives are in electrically conductive contact with one another, in order to form the electrically conductive layer. The substrate is formed from a glass or glass-ceramic material or a composite material having a glass and/or glass-ceramic. The additives are embedded in a matrix layer at least in some regions. The matrix layer is formed by a transparent matrix material. In order to make such a transparent electrical conductor useful, particularly for application in a display, as a touch sensor, or the like for cooking surfaces, the transparent electrical conductor exhibits a temperature resistance of at least 140° C. The additives are dispersed in a matrix material, which is applied as a coating material onto the substrate in one coating step.

Abstract: Provided are a transparent conductive substrate production method for an electrostatic capacitance touch panel having a high pattern recognition property, by simple steps without using a vacuum process and a wet etching method, as well as a transparent conductive substrate and an electrostatic capacitance touch panel. An electrode drawing lead wiring pattern is formed on at least one main face of a transparent film using a conductive paste. An electrode pattern forming unit prints an electrode pattern with a transparent conductive pattern forming ink containing metal nanowires or metal nanoparticles so that the electrode pattern is connected to the electrode drawing lead wiring pattern, and dries the printed electrode pattern. The dried electrode pattern is subjected to pulsed light irradiation by a photoirradiation unit 18, to sinter the metal nanowires or the metal nanoparticles contained in the transparent conductive pattern forming ink.

Abstract: A printed wiring board, including a printed wiring member which respectively has object conductor that is subjected to electromagnetic wave shielding on at least one surface of an insulating layer; and an electromagnetic wave shielding member which has an electromagnetic wave shielding layer composed of a low-resistance section and a high-resistance section on at least one surface of a base film. The printed wiring member and the electromagnetic wave shielding member are bonded together with interposition of insulating adhesive layers, and with arrangement of the electromagnetic wave shielding layer separately and in opposition so that the object conductor is covered. The electromagnetic wave shielding layer and the object conductor are composed of the same type of conductive material, and the electromagnetic wave shielding layer is not exposed at the circumferential end faces of the printed wiring board.

Abstract: Disclosed is a transparent electrode which is configured of a first conductive layer that is composed of a metal or metal oxide fine wire that is formed in a pattern on a substrate; and a second conductive layer that covers the first conductive layer and contains a conductive polymer. The transparent electrode is characterized in that the fine wire of the first conductive layer satisfies the conditions mentioned below. Also disclosed is an organic electronic element. Line width (W): 20-200 ?m Height (H): 0.2-2.0 ?m Aspect ratio: 0.001<H/W?0.1 Coefficient of cross-sectional shape: 0.6<S/(W·H)<0.9 (In this connection, S represents the cross-sectional area of the conductive layer.

Abstract: The invention provides methods to mass laminate and interconnect high density interconnect circuit layers fabricated through parallel processing. Invention methods employ an inside-out interconnection strategy that eliminates plating of vias and provides defect-free outer circuit layers. Conductive paste and via layers are also key features of the invention.

Abstract: A method for forming a graphene circuit pattern on an object includes the following steps of: forming a patterned graphene layer on a surface of a film so as to form a laminate; and covering an object with the laminate so as to attach the patterned graphene layer to the object.

Abstract: It is an object of the invention to provide a method for producing a substrate for mounting a semiconductor chip, that can reduce bridging and allows excellent wire bondability and solder connection reliability to be obtained, even when forming fine-pitch wirings.

Abstract: The disclosed structure (10) is provided with: at least three conductors (111, 131, 151) which face one-another; a through-via (101) which passes through each of the conductors (111, 131, 151); openings (112, 152) which are provided so as to surround the circumference of the through-via (101); and conductor elements (121, 141) which are located in different layers to those in which the conductors (111, 131, 151) are located, and which are connected to the through-via (101). Facing opening 112 is conductor element 121, which is larger than said opening (112), and facing opening 152 is conductor element 141, which is larger than said opening (152).

Abstract: One disclosed embodiment comprises formation of a padless via in a substrate. The padless via includes a hole through a metal layer blanketing the substrate, as well as the underlying substrate. An inner wall of the padless via hole receives a seed layer of a conductive material. Electrolytic differential plating is then performed, resulting in a preferential accumulation of a conductive plating material on the via inner wall, relative to that deposited on a surface of the substrate. In one embodiment, the differential plating is performed by addition of an organic suppressant to a plating bath.

Abstract: Embodiments of methods for forming microelectronic device packages include forming a trench on a surface of a package body between exposed ends of first and second device-to-edge conductors, and forming a package surface conductor in the trench to electrically couple the first and second device-to-edge conductors. In one embodiment, the package surface conductor is formed by first forming a conductive material layer over the package surface, where the conductive material layer substantially fills the trench, and subsequently removing portions of the conductive material layer from the package surface adjacent to the trench. In another embodiment, the package surface conductor is formed by dispensing one or more conductive materials in the trench between the first and second exposed ends (e.g., using a technique such as spraying, inkjet printing, aerosol jet printing, stencil printing, or needle dispense). Excess conductive material may then be removed from the package surface adjacent to the trench.

Abstract: A manufacturing method of a package carrier includes the following steps. Firstly, two base metal layers are bonded together. Then, two supporting layers are laminated onto the base metal layers respectively. Next, two release metal films are disposed on the supporting layers respectively, wherein each of the release metal films includes a first metal film and a second metal film separable from each other. Next, two patterned metal layers are formed on the release metal films respectively, wherein each of the patterned metal layers is suitable for carrying and electrically connected to a chip. Then, the base metal layers are separated from each other to form two package carriers independent from each other. A package carrier formed by the manufacturing method described above is also provided.

Abstract: According to various embodiments, a contact pad structure may be provided, the contact pad structure may include: a dielectric layer structure; at least one contact pad being in physical contact with the dielectric layer structure; the at least one contact pad including a metal structure and a liner structure, wherein the liner structure is disposed between the metal structure of the at least one contact pad and the dielectric layer structure, and wherein a surface of the at least one contact pad is at least partially free from the liner structure, and a contact structure including an electrically conductive material; the contact structure completely covering at least the surface being at least partially free from the liner structure of the at least one contact pad, wherein the liner structure and the contact structure form a diffusion barrier for a material of the metal structure of the at least one contact pad.

Abstract: A lead electrode and a preparation method thereof are provided. The lead electrode includes an inner terminal, a lead, and an outer terminal, which are sequentially connected. The lead includes: an insulating substrate; an adhesive material coated on the insulating substrate, the adhesive material defining a trenched mesh; and a conductive material filled in the trenched mesh, wherein an angle formed by a grid line of the trenched mesh and a demolding direction is from 0° to 90°. Since the angle formed by the grid line and the demolding direction is very small, little adhesive material will be attached to the mold, such that the residues of the adhesive material are prevented.

Abstract: The present invention is a membrane wiring board provided with an insulating substrate, and at least one circuit portion provided on the insulating substrate and obtained by coating a circuit layer, formed by an electrically conductive paste containing electrically conductive particles, with an insulating coating layer, wherein the circuit layer contains a resin component having a gel fraction of 90% or more.

Abstract: There is provided a method for producing a substrate (600) suitable for supporting an elongated superconducting element, wherein, e.g., a deformation process is utilized in order to form disruptive strips in a layered solid element, and where etching is used to form undercut volumes (330, 332) between an upper layer (316) and a lower layer (303) of the layered solid element. Such relatively simple steps enable providing a substrate which may be turned into a superconducting structure, such as a superconducting tape, having reduced AC losses, since the undercut volumes (330, 332) may be useful for separating layers of material. In a further embodiment, there is placed a superconducting layer on top of the upper layer (316) and/or lower layer (303), so as to provide a superconducting structure with reduced AC losses.

Abstract: Provided are a conductive structure including a) a base, b) a conductive pattern provided on at least one side of the base, and c) a darkening layer provided on the upper surface and lower surface of the conductive pattern, provided on at least a part of the side of the conductive pattern, and provided in an area corresponding to the conductive pattern area, and a touch panel including the same and a manufacturing method thereof.

Abstract: Flexible electronic substrate systems relating to providing a system for dimensionally-stable substrate systems to support electronic systems is provided.

Abstract: Package substrate, semiconductor packages and methods for forming a semiconductor package are presented. The package substrate includes a base substrate having first and second major surfaces and a plurality of via contacts extending through the first to the second major surfaces of the base substrate. A first conductive layer having a plurality of openings is disposed over the first surface of the base substrate and via contacts. The openings are configured to match conductive trace layout of the package substrate. Conductive traces are disposed over the first conductive layer. The conductive traces are directly coupled to the via contacts through some of the openings of the first conductive layer.

Abstract: An electroconductive ink composition comprising silver particles (A), a compound having a siloxane backbone with a functional group (B), and an organic solvent (C), the silver particles (A) having a protective layer containing an amino group-containing compound and having a mean particle size of 1 nm or more and 100 nm or less, the content of the compound (B) being 4% by weight to 8% by weight based on the total amount of the composition, can form a circuit pattern on a polymer film with low heat resistance, and the obtained circuit pattern has excellent adhesion to a substrate and high conductivity.

Abstract: An apparatus, system, and/or method are described to enable optically transparent reconfigurable integrated electrical components, such as antennas and RF circuits to be integrated into an optically transparent host platform, such as glass. In one embodiment, an Ag NW film may be configured as a transparent conductor for antennas and/or as interconnects for passive circuit components, such as capacitors or resistors. Ag NW may also be used as transmission lines and/or interconnect overlays for devices. A graphene film may also be configured as active channel material for making active RF devices, such as amplifiers and switches.

Abstract: A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI includes a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A solder ball is over the PPI. A compound includes a portion adjoining the solder ball and the polymer layer, wherein the compound includes flux and a polymer.

Abstract: A conductive paste containing a conductive powder (A), a vinyl chloride-vinyl acetate resin (B), a polyester resin and/or polyurethane resin (C), a blocked isocyanate (D) blocked with an active methylene compound, and an organic solvent (E), wherein the resin (C) has a glass transition temperature of ?50° C. to 20° C., a sum of amounts of the resin (C) is 50 to 400 parts by weight relative to 100 parts by weight of the resin (B), and a sum of amounts of the resin (B), the resin (C) component, and the blocked isocyanate (D) is 10 to 60 parts by weight relative to 100 parts by weight of the conductive powder (A). An electric wiring in which this conductive paste is formed on an insulating substrate.

Abstract: A printed circuit board structure comprises a base layer, an insulation layer, and a signal layer sandwiched between the base layer and the insulation layer. The insulation layer includes a plurality of conductive regions. The conductive regions are used for providing a current reflowing path. Each of the conductive regions comprises a plurality of empty regions which are spaced from each other. A space inside the empty region is substantially hollow, and spaces between adjacent empty region are filled with cooper.

Abstract: To provide a conductive particle, which contains a core particle, and a conductive layer formed on a surface of the core particle, where the core particle is formed of a resin, or a metal, or both thereof, and the conductive layer contains a phosphorus-containing hydrophobic group at a surface thereof.

Abstract: A laminated multilayer electronic support structure comprising a dielectric with integral vias and feature layers and further comprising a planar metal core characterized by a thickness of less than 100 microns.

Abstract: The object of the present invention is to provide an etching solution composition for etching a metal oxide containing In and a metal oxide containing Zn and In used as a transparent electrode or an oxide semiconductor of an electronic device such as a semiconductor element or a flat panel display (FPD), the etching solution composition being controllable to give a practical etching rate, having high dissolving power toward Zn, and enabling a long solution life due to suppressed variation of the formulation during use. The object is solved by an etching solution composition that enables microfabrication to be carried out for a metal oxide containing In and a metal oxide containing Zn and In used as a transparent electrode or an oxide semiconductor of an electronic device such as a semiconductor element or an FPD, the composition containing water and at least one type of acid, excluding hydrohalic acids, perhalic acids, etc., having an acid dissociation constant pKan at 25° C.

Abstract: A semiconductor device includes a lead frame having a flag and leads surrounding the flag. The flag includes a first die attach area and an interposer area. An insulated layer with at least one conductive trace is formed on the interposer area.

Abstract: A printed wiring board includes an interlayer resin insulation layer having a penetrating hole, a conductive circuit formed on a first surface of the interlayer resin insulation layer, a filled via conductor formed in the penetrating hole of the interlayer resin insulation layer and connected to the conductive circuit, a first surface-treatment coating structure formed on a first surface of the filled via conductor and having an electroless plating structure, and a second surface-treatment coating structure formed on a second surface of the filled via conductor on an opposite side with respect to the first surface-treatment coating structure and having an electroless plating structure. The filled via conductor includes a first conductive layer formed on side wall of the penetrating hole and a plated material filling the penetrating hole, and the first surface-treatment coating structure has a thickness which is different from a thickness of the second surface-treatment coating structure.

Abstract: An exemplary embodiment of the present invention relates to a conductive structure body that comprises a darkening pattern layer having AlOxNy, and a method for manufacturing the same. The conductive structure body according to the exemplary embodiment of the present invention may prevent reflection by a conductive pattern layer without affecting conductivity of the conductive pattern layer, and improve a concealing property of the conductive pattern layer by improving absorbance. Accordingly, a display panel having improved visibility may be developed by using the conductive structure body according to the exemplary embodiment of the present invention.

Abstract: An electronic device including a solder structure and methods of forming an electrical interconnection are shown. Solder structures are shown including a solder ball formed from a first solder having a first melting temperature, and a connecting structure coupling the solder ball to one or more electrical connection pads, the connecting structure formed from a second solder having a second melting temperature lower than the first melting temperature. Electronic devices are shown including a polymer mold material formed over the solder structures.

Abstract: An electronic element includes a carbon nanotube film, at least one first electrode and at least one second electrode spaced from the at least one first electrode. The carbon nanotube film includes a number of carbon nanotube linear units spaced from each other, and a number of carbon nanotube groups. The carbon nanotube linear units extend along a first direction to form a number of first conductive paths. The carbon nanotube groups are combined with the carbon nanotube linear units by van der Waals force in a second direction intercrossed with the first direction, to form a number of second conductive paths. The carbon nanotube groups between adjacent carbon nanotube linear units are spaced from each other in the first direction. The at least one first and second electrodes are electrically connected with the carbon nanotube film through the first conductive paths or the second conductive paths.

Abstract: Adhesiveness between a wiring layer and a resin layer is improved by forming a nitrided resin layer by nitriding a surface of a substrate by plasma, and furthermore, thinly forming a copper nitride film prior to forming a copper film.

Abstract: A mixture of spherical graphite, carbon black and binder resin is fabricated. The mixture contains the spherical graphite of not less than 50 parts by weight and not more than 70 parts by weight, the carbon black of not less than 1 part by weight and not more than 15 parts by weight and the binder resin of not less than 15 parts by weight and not more than 40 parts by weight, to 100 parts by weight of the mixture. The binder resin includes thermosetting resin and elastomer, and an average particle diameter of the spherical graphite is not less than 1 ?m and not more than 30 ?m. The conductive composition including the mixture can be used for a collector such as a fuel cell.