With Electrical Device Patents (Class 174/260)
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Publication number: 20140262463Abstract: There is provided an embedded multilayer ceramic electronic component including a ceramic body including dielectric layers, having first and second main surfaces, first and second side surfaces, and first and second end surfaces, and having a thickness of 250 ?m or less, first and second internal electrodes alternately exposed to the first or second side surface, and first and second external electrodes formed on the first and second side surfaces, wherein the first external electrode includes a first electrode layer and a first metal layer, the second external electrode includes a second electrode layer and a second metal layer, the first and second external electrodes are extended onto the first and second main surfaces, and widths of the first and second external electrodes formed on the first and second main surfaces are different from each other.Type: ApplicationFiled: July 12, 2013Publication date: September 18, 2014Inventors: Byoung Hwa LEE, Doo Young KIM, Jin Woo LEE, Jin Man JUNG
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Publication number: 20140262459Abstract: A winding-type solid electrolytic capacitor package structure includes a substrate body, a winding capacitor, a package body and an electrode unit. The winding capacitor has a winding body, a positive conductive lead pin having a positive end surface, and a negative conductive lead pin having a negative end surface. The package body is disposed on the substrate body to enclose the winding body, and the package body has a first lateral surface substantially flushed with the positive end surface and a second lateral surface substantially flushed with the negative end surface. The electrode unit includes a positive electrode structure for covering the first lateral surface and electrically contacting the positive end surface and a negative electrode structure for covering the second lateral surface and electrically contacting the negative end surface.Type: ApplicationFiled: March 18, 2013Publication date: September 18, 2014Applicant: APAQ TECHNOLOGY CO., LTD.Inventors: MING-TSUNG CHEN, CHING-FENG LIN
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Patent number: 8835775Abstract: Techniques are provided for electrically connecting components on a printed circuit board (PCB), semiconductor chip package, or other electronic device. More specifically, a first component, configured to generate a differential signal, is disposed on the PCB, while a second component, configured to receive the differential signal from the first component, is also disposed on the PCB. A differential conductor pair comprising first and second parallel conductors extends along a path between the first and second components. The path of the differential conductor pair comprises at least one turn that causes a change in direction of the first and second conductors. The first conductor comprises at least one localized skew compensation bend disposed at the turn such that, at the end of the turn, the first and second conductors have substantially the same length with respect to the first component.Type: GrantFiled: November 15, 2011Date of Patent: September 16, 2014Assignee: Cisco Technology, Inc.Inventors: Hongmei Fan, Xiaoxia Zhou, Alpesh U. Bhobe, Jinghan Yu, Hailong Zhang, Phillipe Sochoux
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Patent number: 8832930Abstract: A touchscreen panel includes an upper substrate having a first transparent conductor layer provided on a first base layer, and a lower substrate having a second transparent conductor layer provided on a second base layer. The first and second transparent conductor layers oppose each other via a spacer and make contact when the first base layer is pressed. The first transparent conductor layer is segmented into a plurality of conductive regions that are electrically insulated from each other.Type: GrantFiled: October 22, 2013Date of Patent: September 16, 2014Assignee: Fujitsu Component LimitedInventors: Koichi Kondoh, Takashi Nakajima, Nobuyoshi Shimizu, Masanobu Hayama, Norio Endo
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Patent number: 8835769Abstract: A high speed serial interface comprises a rectilinear array of rows and columns of contact sites on a substrate. In the first four columns, pairs of transmitter and receiver contacts alternate row-by-row with pairs of ground contacts In the fifth column, there is a permanent (or hard) ground contact adjacent to each transmitter or receiver contact pair located in a row in the third and fourth columns and the remaining contacts in the fifth column are general purpose input/output (GPIO) contacts. As a result, up to 50 percent of the contacts in the fifth column may be GPIO contacts. In the sixth column, all the contacts are GPIO contacts.Type: GrantFiled: June 15, 2012Date of Patent: September 16, 2014Assignee: Altera CorporationInventors: Arch Zaliznyak, Surinder Singh
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Patent number: 8837163Abstract: An integrated structure for interconnection of electrical components is provided. In one embodiment, the integrated structure includes a through mold via (TMV) module having a substrate and at least one component coupled to the substrate. A flexible printed circuit board (flex-PCB) is integrated with the substrate of the TMV module. A TMV is provided through a body of the module to allow the flex-PCB to couple with a logic board.Type: GrantFiled: December 27, 2011Date of Patent: September 16, 2014Assignee: Apple Inc.Inventors: Emery A. Sanford, Sean A. Mayo
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Patent number: 8835774Abstract: According to an aspect of the invention, there is provided a circuit board assembly including a first circuit board including a first circuit pattern formed on a surface of the first circuit board, and an opening that is adjacent to the first circuit pattern; and a second circuit board including a second circuit pattern corresponding to the first circuit pattern and a protection film that is applied to a surface of the second circuit board so as to form a hollow place located corresponding to the opening, wherein the first circuit board and the second circuit board are combined with each other.Type: GrantFiled: October 28, 2011Date of Patent: September 16, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-seok Kim, Inh-seok Suh, Tak-kyoum Kim
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Patent number: 8835773Abstract: A method of manufacturing a wiring board for use in mounting of an electronic component includes: forming an outermost wiring layer on a surface side where the electronic component is mounted; forming an insulating layer so as to cover the wiring layer; and forming a concave portion in the insulating layer. The concave portion is formed by removing, using a mask formed in a required shape by patterning, an exposed portion of the insulating layer in a step-like shape until a surface of a pad defined at a portion of the wiring layer is exposed. The concave portion is preferably formed by removing the portion of the insulating layer by sand blast.Type: GrantFiled: April 1, 2010Date of Patent: September 16, 2014Assignee: Shinko Electric Industries Co., Ltd.Inventors: Shigetsugu Muramatsu, Yasuhiko Kusama
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AUTOMATIC MANUFACTURING PROCESS FOR PROVIDING BUFFER PADS FOR A PCB AND PCB STRUCTURE USING THE SAME
Publication number: 20140251668Abstract: An automatic manufacturing process for providing buffer pads (40) for a PCB (10), includes a) providing the PCB (10); b) providing an automatic dispensing device and an adhesive (30); c) using the automatic dispensing device to dispense the adhesive (30) to a buffer zone (12) on the PCB (10); d) providing a pick-and-place machine and the buffer pads (40); e) using the pick-and-place machine to place the buffer pads (40) on the buffer zone (12) moistened with the adhesive (30); and f) curing the adhesive (30) to attach the buffer pads (40) to the PCB (10). Thus, labor is saved and manufacturing time is reduced.Type: ApplicationFiled: August 19, 2013Publication date: September 11, 2014Applicant: DELTA ELECTRONICS, INC.Inventors: Chun-Kai CHUANG, Yu-Wei LEE, Kuo-Liang LEE -
Publication number: 20140251659Abstract: A circuit board, onto which an electronic component is to be mounted, is provided with insulating core substrates and patterned metal plates. The metal plates are bonded to at least one side of the insulating core substrates. The insulating core substrates and the metal plates form a laminated body, in which a gas-vent hole is provided. The gas-vent hole is formed so that when the electronic component is mounted, the gas present between the insulating core substrates and the metal plates expands and is released to a side open to the atmosphere via the gas-vent hole.Type: ApplicationFiled: July 2, 2012Publication date: September 11, 2014Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKIInventors: Hiroaki Asano, Yasuhiro Koike, Kiminori Ozaki, Hitoshi Shimadu, Tetsuya Furuta, Masao Miyake, Takahiro Hayakawa, Tomoaki Asai, Ryou Yamauchi
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Publication number: 20140251665Abstract: A device for storing electromagnetic energy and signals, for example from biological systems and, possibly modifying, and emitting them again is provided with a planar substrate, having a first side and a second side, at least one first arrangement being provided on the first side, which has at least one first single-wire and possibly at least one first cavity, and at least one first device for storing electromagnetic energy being provided, one end of a single-wire being connected to the device for storing the electromagnetic energy, and the other end of the single-wire being disposed possibly, as free end, in, below or abutting on the first cavity.Type: ApplicationFiled: February 3, 2014Publication date: September 11, 2014Inventor: Dietrich REICHWEIN
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Publication number: 20140251669Abstract: The present description relates to the field of fabricating microelectronic structures. The microelectronic structure may include a microelectronic substrate have an opening, wherein the opening may be formed through the microelectronic substrate or may be a recess formed in the microelectronic substrate. A microelectronic package may be attached to the microelectronic substrate, wherein the microelectronic package may include an interposer having a first surface and an opposing second surface. A microelectronic device may be attached to the interposer first surface and the interposer may be attached to the microelectronic substrate by the interposer first surface such that the microelectronic device extends into the opening. At least one secondary microelectronic device may be attached to the interposer second surface.Type: ApplicationFiled: April 24, 2012Publication date: September 11, 2014Inventors: Mathew J. Manusharow, Mihir K. Roy, Kaladhar Radhakrishnan, Debendra Mallik, Edward A. Burton
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Publication number: 20140251670Abstract: A module includes a wiring board; a component mounted on the wiring board; a columnar conductor for external connection, the columnar conductor being connected at one end thereof to the wiring board; and a resin layer disposed on the wiring board and configured to cover the columnar conductor and the component, with an end face of the columnar conductor exposed from a surface of the resin layer, the end face being at the other end of the columnar conductor. A gap to be filled with solder is formed between the resin layer and a periphery of an end portion of the columnar conductor, the end portion being at the other end of the columnar conductor.Type: ApplicationFiled: March 7, 2014Publication date: September 11, 2014Applicant: Murata Manufacturing Co., Ltd.Inventors: Norio SAKAI, Yoshihito OTSUBO
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Patent number: 8829357Abstract: A wiring board includes a core substrate having an opening portion and a through hole adjacent to the opening portion, a capacitor positioned in the opening portion, and a through-hole conductor formed in the through hole of the core substrate and having a conductor filling the through hole. The core substrate has a first surface and a second surface on the opposite side of the first surface, the opening portion of the core substrate penetrates from the first surface to the second surface, the through-hole conductor has a first conductive portion and a second conductive portion connected to the first conductive portion in the core substrate, the first conductive portion of the through-hole conductor becomes narrower from the first surface toward the second surface, and the second conductive portion of the through-hole conductor becomes narrower from the second surface toward the first surface.Type: GrantFiled: November 30, 2011Date of Patent: September 9, 2014Assignee: Ibiden Co., Ltd.Inventors: Yukinobu Mikado, Shunsuke Sakai, Mitsuhiro Tomikawa
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Patent number: 8826527Abstract: Disclosed herein is a printed circuit board, including: a substrate including an insulation layer in which a cavity is formed; an electronic component mounted in the cavity of the substrate and having connection terminals; an insulation material layer formed on one side of the substrate to bury the electronic component; a first circuit layer formed on the other side of the substrate and including a connection pattern connecting with the connection terminals of the electronic component; and a second circuit layer formed on the insulation material layer. The printed circuit board is advantageous in that it can prevent the warpage thereof and ensure the reliability of electrical connection between an electronic component and a circuit layer by adjusting the thickness, thermal expansion coefficient and elastic modulus of insulation layer or the insulating material.Type: GrantFiled: September 14, 2012Date of Patent: September 9, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventor: Jin Seon Park
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Patent number: 8829361Abstract: A wiring board includes a rectangular mount region surrounded by four sides circumscribed to pads located in an outer peripheral area among a plurality of pads arranged in a substantially matrix form, a corner pad close to a corner of the mount region, and a second via-conductor and a second corner via-conductor electrically connected to the corner pad via a first via-conductor and a first wiring conductor. In the wiring board, a distance in a plane direction between the second corner via-conductor and a center of the mount region is smaller than a distance in the plane direction between the corner pad and the center of the mount region.Type: GrantFiled: October 22, 2013Date of Patent: September 9, 2014Assignee: KYOCERA CorporationInventor: Takafumi Oyoshi
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Patent number: 8830692Abstract: A printed circuit board according to one example embodiment includes a Z-directed component mounted in a mounting hole in the printed circuit board. The Z-directed component includes a body having a top surface, a bottom surface and a side surface. Four conductive channels extend through a portion of the body along the length of the body. The four conductive channels are spaced substantially equally around a perimeter of the body. An integrated circuit is mounted on a surface of the printed circuit board. The integrated circuit has a ball grid array that includes four conductive balls electrically connected to a corresponding one of the four conductive channels of the Z-directed component.Type: GrantFiled: March 29, 2012Date of Patent: September 9, 2014Assignee: Lexmark International, Inc.Inventor: Keith Bryan Hardin
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Patent number: 8830691Abstract: A printed circuit board including a core substrate including a first resin substrate, a second resin substrate having an opening and a third resin substrate in a multilayer manner while interposing bonding plates, insulating layers and conductive circuit layers alternately laminated on the core substrate, solder bumps formed on an outer surface of the printed circuit board, a first capacitor formed in the opening of the second resin substrate, a conductive pad formed on the first resin substrate and connected to an electrode of the first capacitor, a via hole formed in the first resin substrate and directly connected to the conductive pad and a conductive circuit on the core substrate, and a second capacitor mounted on a surface of the printed circuit board.Type: GrantFiled: May 21, 2010Date of Patent: September 9, 2014Assignee: IBIDEN Co., Ltd.Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai
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Patent number: 8829356Abstract: A packaging substrate includes: a dielectric layer unit having top and bottom surfaces; a positioning pad embedded in the bottom surface of the dielectric layer unit; at least a passive element having a plurality of electrode pads disposed on upper and lower surfaces thereof, the passive element being embedded in the dielectric layer unit and corresponding to the positioning pad; a first circuit layer disposed on the top surface of the dielectric layer unit, the first circuit layer having first conductive vias electrically connected to the electrode pads disposed on the upper surface of the passive element; and a second circuit layer disposed on the bottom surface of the dielectric layer unit, the second circuit layer having second conductive vias electrically connected to the electrode pads disposed on the lower surface of the passive element. Through the embedding of the passive element, the overall structure may have a reduced height.Type: GrantFiled: August 12, 2011Date of Patent: September 9, 2014Assignee: Unimicron Technology CorporationInventors: Shih-Ping Hsu, Zhao-Chong Zeng
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Patent number: 8830690Abstract: Embodiments of the present invention are directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A first outer layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A capacitor is used to capacitively couple the plating stub to a ground layer.Type: GrantFiled: September 25, 2008Date of Patent: September 9, 2014Assignee: International Business Machines CorporationInventors: Bhyrav M Mutnury, Moises Cases, Nanju Na, Tae Hong Kim
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Patent number: 8829358Abstract: A Z-directed signal pass-through component for insertion into a printed circuit board while allowing electrical connection from external surface conductors to internal conductive planes or between internal conductive planes. The Z-directed pass-through component is mounted within the thickness of the PCB allowing other components to be mounted over it. The body may contain one or more conductors and may include one or more surface channels or wells extending along at least a portion of the length of the body.Type: GrantFiled: January 13, 2012Date of Patent: September 9, 2014Assignee: Lexmark International, Inc.Inventors: Keith Bryan Hardin, John Thomas Fessler, Paul Kevin Hall, Brian Lee Nally, Robert Aaron Oglesbee
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Patent number: 8829359Abstract: A substrate includes a functional element. An insulating first film forms a cavity which stores the functional element, together with the substrate, and includes a plurality of through-holes. An insulating second film covers the plurality of through-holes, is formed on the first film, and has a gas permeability which is higher than that of the first film. An insulating third film is formed on the second film and has a gas permeability which is lower than the second film. An insulating fourth film is formed on the third film and has an elasticity which is larger than the third film.Type: GrantFiled: October 9, 2012Date of Patent: September 9, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Akihiro Kojima, Yoshiaki Sugizaki, Yoshiaki Shimooka
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Publication number: 20140247535Abstract: A high power, low passive inter-modulation capacitor is presented, which is formed using metal clad substrates, which are broad-side coupled through a thin air gap. Each substrate may include metal layers affixed on both sides which are electrical coupled together to form a single capacitor plate, or each substrate may have only a single metal layer on the surface adjacent to the air gap. The capacitor has particular application in low cost RF and microwave filters, which may be used in communication equipment and communication test equipment such a diplexers, for low PIM applications.Type: ApplicationFiled: May 16, 2014Publication date: September 4, 2014Applicant: K&L Microwave, Inc.Inventor: Rafi Hershtig
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Patent number: 8822840Abstract: A Z-directed component for mounting in a mounting hole in a printed circuit board according to one example embodiment includes a body having a top surface, a bottom surface and a side surface. The body has a cross-sectional shape that is insertable into the mounting hole in the printed circuit board. A portion of the body is composed of an insulator. A first conductive channel extends through an interior portion of the body along the length of the body from the top surface to the bottom surface. The first conductive channel forms a signal path through the body. A second conductive channel and a third conductive channel each extends through the interior portion of the body along the length of the body. The second and third conductive channels are positioned next to and on opposite sides of the first conductive channel.Type: GrantFiled: March 29, 2012Date of Patent: September 2, 2014Assignee: Lexmark International, Inc.Inventor: Keith Bryan Hardin
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Patent number: 8822836Abstract: A bonding sheet includes an insulating sheet with cavities formed within the insulating sheet, and adhesive-filling portions made of an electrically conductive adhesive filled in the cavities. An electronic circuit device includes an IC package mounted on a circuit board, with the bonding sheet disposed between the IC package and the circuit board. The IC package is provided with terminal electrodes in the lower surface, and electrode bumps project from the terminal electrodes. The circuit board has recesses in the upper surface, and electrode pads are formed on the bottom of the recesses. The electrically conductive adhesive that flows out from the adhesive-filling portions filled the recesses and fix the electrode bumps and the electrode pads.Type: GrantFiled: September 9, 2009Date of Patent: September 2, 2014Assignee: NEC CorporationInventor: Eiji Hori
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Patent number: 8822837Abstract: A wiring board or an electronic component embedded substrate includes a substrate that includes a resin containing a plurality of fillers; and a via that is electrically connected to at least one interconnect provided to the substrate, wherein the via includes a mix area in which metal is provided between the fillers on an inner radial side with respect to the substrate. A method of manufacturing a wiring board or an electronic component embedded substrate includes preparing a substrate that includes a resin containing a plurality of fillers; forming a via formation hole in the substrate; performing an ashing process on at least an inner wall of the via formation hole; and performing electroless plating an the inner wall of the via formation hole.Type: GrantFiled: December 5, 2011Date of Patent: September 2, 2014Assignee: TDK CorporationInventors: Hiroyuki Uematsu, Kenichi Kawabata
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Patent number: 8822838Abstract: A Z-directed component for mounting in a mounting hole in a printed circuit board according to one example embodiment includes a body having a top surface, a bottom surface and a side surface. The body has a cross-sectional shape that is insertable into the mounting hole in the printed circuit board. A portion of the body is composed of an insulator. Four conductive channels extend through a portion of the body along the length of the body. The four conductive channels are spaced substantially equally around a perimeter of the body.Type: GrantFiled: March 29, 2012Date of Patent: September 2, 2014Assignee: Lexmark International, Inc.Inventor: Keith Bryan Hardin
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Publication number: 20140238732Abstract: A main body of an electronic part has multiple electrodes, to which multiple terminals are respectively connected. The terminals include a normal terminal and a fuse terminal, each of which extends from lands formed in a printed board so as to hold the main body at a position above and separated from a board surface of the printed board. The fuse terminal has multiple leg portions divided by slits. A first leg portion forms an electrical path portion having a cut-off portion, a width of which is smaller than that of other portions of the electrical path portion. A second leg portion has a first supporting leg and a second supporting leg, which are arranged at both sides of the first leg portion. Each of the supporting legs is connected to each of dummy lands formed in the printed board.Type: ApplicationFiled: February 26, 2014Publication date: August 28, 2014Applicants: Murata Manufacturing Co., Ltd., DENSO CORPORATIONInventors: Toru ITABASHI, Yuki MIKAMI, Ryoichi SHIRAISHI, Akihiro YANAGISAWA, Shigeki NISHIYAMA
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Patent number: 8813353Abstract: A dielectric structure including a metal foil, a dielectric layer and a conductor layer provided in this order, wherein the metal foil has a thickness of from 10 to 40 ?m, the dielectric layer has a thickness of from 0.3 to 5 ?m, and the conductor layer has a thickness of from 0.3 to 10 ?m. The dielectric structure has plural vias which are separated from each other, and which penetrate through both of the dielectric layer and the conductor layer. The vias of the dielectric layer have different diameters which are in a range of from 100 to 300 ?m, a diameter of each of the vias of the conductor layer is larger than a diameter of a corresponding via of the dielectric layer by 5 to 50 ?m, and a minimum via pitch is from 100 to 350 ?m.Type: GrantFiled: May 21, 2010Date of Patent: August 26, 2014Assignee: NGK Spark Plug Co., Ltd.Inventors: Yasuhiko Inui, Takamichi Ogawa, Seiji Ichiyanagi, Jun Otsuka, Manabu Sato
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Patent number: 8811019Abstract: An electronic device comprising an electrically conductive core layer with a first layer composed of electrically conductive material, the first layer being applied on both sides and with at least one electronic component arranged in a cutout of the first layer, wherein the first layer is covered in each case with an electrically insulating, thermally conductive layer and a further layer composed of electrically conductive material is provided in each case on the thermally conductive layer, the further layer being coated in each case with a covering layer composed of electrically conductive material, and furthermore having plated-through boles composed of the material of the covering layer, which extend through the electrically insulating, thermally conductive layer covering the electronic component and the further layer composed of electrically and thermally conductive material for the purpose of making contact with the electronic component.Type: GrantFiled: November 24, 2011Date of Patent: August 19, 2014Assignee: Schweizer Electronic AGInventors: Thomas Gottwald, Christian Rossle
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Patent number: 8809691Abstract: A wired circuit board includes an insulating layer, and a conductive layer formed on the insulating layer. The insulating layer includes a first insulating layer, and a second insulating layer formed on the first insulating layer. The conductive layer includes a first conductive pattern, and a second conductive pattern. The first conductive pattern includes a first connecting portion formed on the first insulating layer and under the second insulating layer, and at least one pair of first terminals configured continuously to the first connecting portion so as to electrically connect to an external electronic element and spaced apart from each other to allow the electronic element to extend therebetween. The second conductive pattern includes a second connecting portion formed on the second insulating layer, and a second terminal configured continuously to the second connecting portion so as to electrically connect to a magnetic head provided on an external slider.Type: GrantFiled: July 20, 2012Date of Patent: August 19, 2014Assignee: Nitto Denko CorporationInventor: Tetsuya Ohsawa
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Patent number: 8809693Abstract: A three-dimensional circuit board is formed by comprising a board, a first wiring-electrode group provided on a plurality of steps above the board, and a second wiring-electrode connected to the first wiring-electrode group at least in an altitude direction, in which at least a connecting portion between the first wiring-electrode group and the second wiring-electrode is integrated in a continuously identical shape.Type: GrantFiled: January 31, 2012Date of Patent: August 19, 2014Assignee: Panasonic CorporationInventors: Daisuke Sakurai, Yoshihiko Yagi
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Patent number: 8809694Abstract: A circuit module includes a substrate that has a substantially rectangular parallelepiped shape and includes a plurality of inner conductive layers, an electronic component disposed on a first main surface of the substrate, an insulating layer disposed on the first main surface of the substrate so as to cover the electronic component, a shielding layer disposed on a surface of the insulating layer, and a ground electrode connected to the plurality of inner conductive layers. At least two of the inner conductive layers are directly connected to the shielding layer.Type: GrantFiled: June 28, 2012Date of Patent: August 19, 2014Assignee: Murata Manufacturing Co., Ltd.Inventor: Masato Yoshida
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Patent number: 8810007Abstract: A wiring board provided with a silicon substrate including a through hole that communicates a first surface and a second surface of the silicon substrate. A capacitor is formed on an insulating film, which is applied to the silicon substrate, on the first surface and a wall surface defining the through hole. A capacitor part of the capacitor includes a first electrode, a dielectric layer, and a second electrode that are sequentially deposited on the insulating film on the first surface and the wall surface of the through hole. A penetration electrode is formed in the through hole covered by the first electrode, the dielectric layer, and the second electrode of the capacitor part.Type: GrantFiled: April 17, 2012Date of Patent: August 19, 2014Assignees: Shinko Electric Industries Co., Ltd., Taiyo Yuden Co., Ltd.Inventors: Akihito Takano, Masahiro Sunohara, Hideaki Sakaguchi, Mitsutoshi Higashi, Kenichi Ota, Yuichi Sasajima
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Patent number: 8809692Abstract: A wiring board including a conductor post corresponding to high-density packaging is provided. The wiring board may include a conductor layer, a solder resist layer laminated thereon, and a conductor post provided at least within the through-hole and that is electrically connected to a conductor layer which is disposed in a lower portion of a through-hole provided in the layer, wherein the solder resist layer comprises a thermosetting resin; the conductor post comprises tin, copper, or a solder and includes a lower conductor post located within the through-hole and an upper conductor post located above the lower conductor post and projected outside the layer; the lower conductor post includes an external alloy layer disposed on an external side surface thereof; and the conductor post is brought into intimate contact with an internal side surface of the through-hole via the external alloy layer.Type: GrantFiled: December 14, 2011Date of Patent: August 19, 2014Assignee: NGK Spark Plug Co., Ltd.Inventors: Erina Yamada, Kazunaga Higo, Hironori Sato
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Patent number: 8811031Abstract: A multichip module comprising: a base substrate; a wiring board disposed on the base substrate and having a wiring pattern; an adhesive layer configured to bond the base substrate to the wiring board while maintaining an electrical connection between the base substrate and the wiring board; and a plurality of chips connected to a surface of the wiring board, the surface being opposite the adhesive layer, wherein, assuming that ? is a coefficient of thermal expansion of the wiring board, ? is a coefficient of thermal expansion of the base substrate, and ? is a coefficient of thermal expansion of the adhesive layer, the relationship ?<?<? is satisfied.Type: GrantFiled: August 9, 2010Date of Patent: August 19, 2014Assignee: Fujitsu LimitedInventors: Masateru Koide, Daisuke Mizutani
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Patent number: 8803310Abstract: An embedded electronic device package structure includes a core layer, an electronic device, a first dielectric layer, a second dielectric layer and conductive vias. The core layer has cavity, a first surface and a second surface opposite to the first surface. The electronic device is disposed in the cavity. The first dielectric layer disposed on the first surface is filled in part of the cavity and covers one side of the electronic device. The second dielectric layer disposed on the second surface is filled in the cavity, covers another side of the electronic device and connects the first dielectric layer. The first and the second dielectric layers fully cover the electronic device. The conductive vias are disposed around the surrounding of the electronic device and penetrates through the first and the second dielectric layer and the core layer. The conductive vias respectively connects the first and the second dielectric layer.Type: GrantFiled: February 8, 2013Date of Patent: August 12, 2014Assignee: Unimicron Technology Corp.Inventors: Yu-Chen Chuo, Wei-Ming Cheng
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Patent number: 8800138Abstract: A method for forming an electronic device on a flexible substrate conditions a surface of the flexible substrate to increase its malleability and to provide a conditioned substrate surface. A master surface is impressed against the conditioned substrate surface. The master surface is then released from the conditioned substrate surface, thereby forming a circuit-side surface on the substrate. The electronic device is then formed on the circuit-side surface. The substrate may be supported on a carrier during the method.Type: GrantFiled: February 27, 2009Date of Patent: August 12, 2014Assignee: Carestream Health, Inc.Inventors: Timothy J. Tredwell, Roger S. Kerr
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Patent number: 8804364Abstract: A footprint of a printed circuit board (PCB) for a leadframe-based package includes a plurality of pads arranged within a central region on a main surface of the PCB; and an array of signal pads disposed within a peripheral region surrounding the central region.Type: GrantFiled: June 26, 2011Date of Patent: August 12, 2014Assignee: Mediatek Inc.Inventor: Hao-Jung Li
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Patent number: 8804339Abstract: A power electronics assembly includes a semiconductor device, an insulated metal substrate, and a cooling structure. The insulated metal substrate includes a dielectric layer positioned between first and second metal layers, and a plurality of stress-relief through-features extending through the first metal layer, the second metal layer, the dielectric layer, or combinations thereof. The semiconductor device is thermally coupled to the first metal layer and the plurality of stress relief through-features is positioned around the semiconductor device. The cooling structure is bonded directly to the second metal layer of the insulated metal substrate. Insulated metal substrate assemblies are also disclosed. The insulated metal substrate includes a plurality of stress-relief through-features extending through a first metal layer, a second metal layer, and a dielectric layer. Vehicles having power electronics assemblies with stress-relief through-features are also disclosed.Type: GrantFiled: February 28, 2011Date of Patent: August 12, 2014Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.Inventor: Brian Joseph Robert
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Patent number: 8802999Abstract: An embedded printed circuit board (PCB) includes: a copper foil laminate; an internal electronic component inserted into the copper foil laminate; a first circuit pattern formed on a surface of the internal electronic component; and a second circuit pattern formed on the copper foil laminate.Type: GrantFiled: May 23, 2012Date of Patent: August 12, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jong In Ryu, Yul Kyo Chung, Tae Sung Jeong
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Patent number: 8802998Abstract: A ceramic multilayer substrate incorporating a chip-type ceramic component, in which, even if the chip-type ceramic component is mounted on the surface of the ceramic multilayer substrate, bonding strength between the chip-type ceramic component and an internal conductor or a surface electrode of the ceramic multilayer substrate is greatly improved and increased. The ceramic multilayer substrate includes a ceramic laminate in which a plurality of ceramic layers are stacked, an internal conductor disposed in the ceramic laminate, a surface electrode disposed on the upper surface of the ceramic laminate, and a chip-type ceramic component bonded to the internal conductor or the surface electrode through an external electrode. The internal conductor or the surface electrode is bonded to the external electrode through a connecting electrode, and the connecting electrode forms a solid solution with any of the internal conductor, the surface electrode, and the external electrode.Type: GrantFiled: March 10, 2010Date of Patent: August 12, 2014Assignee: Murata Manufacturing Co., Ltd.Inventors: Yoshiko Okada, Osamu Chikagawa, Hidekiyo Takaoka, Shodo Takei
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Patent number: 8804358Abstract: A method for electrically interconnecting two substrates, each having a corresponding set of preformed electrical contacts, the substrates comprising an electronic circuit, and the resulting module, is provided. A liquid curable adhesive is provided over the set of contacts of a first substrate, and the set of electrical contacts of the second substrate is aligned with the set of electrical contacts of the first substrate. The sets of electrical contacts of the first and second substrate are compressed to displace the liquid curable adhesive from the inter-contact region, and provide electrical communication between the respective sets of electrical contacts. The liquid curable adhesive is then cured to form a solid matrix which maintains a relative compression between the respective sets of electrical contacts. One embodiment of the module comprises a high-speed superconducting circuit which operates at cryogenic temperatures.Type: GrantFiled: April 17, 2012Date of Patent: August 12, 2014Assignee: Hypres Inc.Inventor: Vladimir V. Dotsenko
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Patent number: 8803000Abstract: There is provided a device for surface mounting that has a substrate and a capacitor element loaded on a loading-side surface of the substrate and is integrally molded including the substrate and the capacitor element using a packaging resin. The substrate includes a first terminal electrode electrically connected to a first electrode of the capacitor element and a second terminal electrode electrically connected to a second electrode of the capacitor element, at least part of a mounting-side surface on an opposite side to the loading-side surface of the substrate is exposed on a mounting surface of the device, and the first terminal electrode and the second terminal electrode are adjacently disposed around an entire circumference of the mounting surface of the device.Type: GrantFiled: May 19, 2010Date of Patent: August 12, 2014Assignees: Rubycon Corporation, Rubycon Carlit Co., Ltd., Carlit Holdings Co., Ltd.Inventors: Takuya Miyahara, Tetsuo Shiba
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Patent number: 8793868Abstract: A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.Type: GrantFiled: June 23, 2011Date of Patent: August 5, 2014Assignee: Shinko Electric Industries Co., Ltd.Inventors: Takaharu Yamano, Hajime Iizuka, Hideaki Sakaguchi, Toshio Kobayashi, Tadashi Arai, Tsuyoshi Kobayashi, Tetsuya Koyama, Kiyoaki Iida, Tomoaki Mashima, Koichi Tanaka, Yuji Kunimoto, Takashi Yanagisawa
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Patent number: 8797757Abstract: A wiring substrate includes plural insulating layers including an outermost insulating layer; and plural wiring layers which are alternately laminated between the insulating layers and include outermost wiring layers exposed from the outermost insulating layer and through wirings having electrode pads on end portions of the through wirings and penetrating through the outermost insulating layer, wherein the electrode pads of the through wirings are exposed from the outermost insulating layer, and a part of the outermost wiring layers overlaps the end portions of the through wirings and is connected to the through wirings.Type: GrantFiled: January 6, 2012Date of Patent: August 5, 2014Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kentaro Kaneko, Toshiaki Aoki, Kazuhiro Kobayashi, Kotaro Kodani, Junichi Nakamura
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Patent number: 8796563Abstract: In ultrasonic bonding of a metal terminal to a substrate pad, a thin buffer metal layer which is formed of a soft metal or a highly slidable metal is interposed between a terminal edge and a pad so as to prevent direct contact between an end of the terminal and the pad upon bonding. This makes it possible to prevent abrasion and a crack in the pad at the end of the terminal caused by pressure and an ultrasonic wave upon the ultrasonic bonding. This makes it possible to realize a compact bonded structure with high reliability.Type: GrantFiled: January 29, 2010Date of Patent: August 5, 2014Assignee: Hitachi Automotive Systems, Ltd.Inventors: Ukyo Ikeda, Masato Nakamura, Shiro Yamashita
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Patent number: 8796561Abstract: A fan out build up substrate stackable package includes an electronic component having an active surface including a bond pad. A package body encloses the electronic component, the package body having a first surface coplanar with the active surface of the electronic component. A buildup dielectric layer is applied to the active surface of the electronic component and the first surface of the package body. A circuit pattern is formed within the first buildup dielectric layer and electrically connected to the bond pad, the first circuit pattern including via capture pads. Via capture pad apertures extend through the package body and expose the via capture pads. In this manner, direct connection to the first circuit pattern, i.e., the first metal layer, of the fan out build up substrate stackable package is facilitated. Further, the fan out build up substrate stackable package is extremely thin resulting in extremely thin stacked assemblies.Type: GrantFiled: October 5, 2009Date of Patent: August 5, 2014Inventors: Christopher M. Scanlan, Roger D. St. Amand, Jae Dong Kim
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Patent number: 8796558Abstract: A base of a surface-mount electronic component package holds an electronic component element and is to be mounted on a circuit board with a conductive bonding material. The base has a principal surface and an external connection terminal to be electrically connected to the circuit board. The external connection terminal is formed in the principal surface. The base includes a bump formed on the external connection terminal. The bump is smaller than the external connection terminal. The base has a distance d between an outer periphery end edge of the external connection terminal and an outer periphery end edge of the bump along an attenuating direction of stress on the external connection terminal The stress is generated in association of mounting of the base on the circuit board. The distance d is more than 0.00 mm and equal to or less than 0.45 mm.Type: GrantFiled: March 24, 2011Date of Patent: August 5, 2014Assignee: Daishinku CorporationInventors: Minoru Iizuka, Yuka Kojo
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Patent number: 8796145Abstract: A method of manufacturing a metal-base substrate having an insulative adhesive layer and a conductor layer on a metal-based material is provided. The method includes the steps of dispersing a disperse phase in an insulative adhesive-dispersing medium that contains a wetting dispersant and constitutes the insulative adhesive layer; laminating step of laminating the insulative adhesive on the conductor foil as feeding the roll-shaped conductor foil; curing the insulative adhesive on the conductor foil under heat into a B stage state and thus forming a composite of the conductor foil and the insulative adhesive layer in the B stage state; laminating the metal-based material on the insulative adhesive layer in the B stage state to give a laminate; and then curing the insulative adhesive layer in the B stage state into a C stage state by heat pressurization of the laminate.Type: GrantFiled: April 6, 2011Date of Patent: August 5, 2014Assignee: Denki Kagaku Kogyo Kabushiki KaishaInventors: Taiki Nishi, Takeshi Miyakawa, Katsunori Yashima, Kensuke Okoshi, Hidenori Ishikura