Abstract: A printed circuit board includes a first layer stack and a second layer stack coupled to the first layer stack. The first layer stack includes a first electrically-insulating layer, a first electrically-conductive layer, and a cut-out area defining a void that extends therethrough. The first electrically-insulating layer includes a first surface and an opposite second surface. The first electrically-conductive layer is disposed on the first surface of the first electrically-insulating layer. The second layer stack includes a second electrically-insulating layer. The second electrically-insulating layer includes a first surface and an opposite second surface. One or more electrically-conductive traces are disposed on the first surface of the second electrically-insulating layer. The printed circuit board further includes a device at least partially disposed within the cut-out area.

Abstract: An electronic component includes an electrically conductive carrier. The electrically conductive carrier includes a carrier surface and a semiconductor chip includes a chip surface. One or both of the carrier surface and the chip surface include a non-planar structure. The chip is attached to the carrier with the chip surface facing towards the carrier surface so that a gap is provided between the chip surface and the carrier surface due to the non-planar structure of one or both of the carrier surface and the first chip surface. The electronic component further includes a first galvanically deposited metallic layer situated in the gap.

Abstract: A printed circuit board, including: a substrate on which a component is mounted by solder; and a contact plate having a soldered portion soldered on the substrate, the contact plate being configured to be brought into contact with a contact of an apparatus to which the substrate is to be attached, wherein the soldered portion is soldered on a surface of the substrate opposite to a surface of the substrate on which the component is mounted, and wherein the contact plate has a suppressing portion configured to suppress an adhesion of a flux of the solder to a portion in which the contact plate is to be contacted by the contact, the suppressing portion making a flow path of the flux from the soldered portion to the portion longer than a straight-line distance from the soldered portion to the portion.

Abstract: There is provided a multilayer ceramic capacitor including: a ceramic body including dielectric layers; and a plurality of internal electrodes disposed within the ceramic body, having the dielectric layer interposed therebetween, wherein, on a cross section of the ceramic body in a width-thickness direction thereof, when a distance between an uppermost internal electrode and a lowermost internal electrode measured at centers thereof in a width direction thereof is defined as a and a distance between the uppermost internal electrode and the lowermost internal electrode measured at edges thereof in the width direction thereof is defined as b, 0.953?a/b?0.996 is satisfied.

Abstract: There is provided a nickel powder for internal electrodes satisfying the following equation: 0.8?b*D*?/6?1.0 wherein a specific surface area of the nickel powder is defined as b, an average particle size of the nickel powder is defined as D, and a density of the nickel powder is defined as ?.

Abstract: Stacked arrays of components are disclosed. In one embodiment, a first and a second layer of components are electrically and mechanically coupled to a thin interposer disposed between the first and second layers. The first layer can be configured to attach the stacked array to a host printed circuit board. The interposer can insulate the components from one another and also couple signals between the components on the first and second layers. In one embodiment, the components in the first and second layers are passive components.

Abstract: A laminated wiring board, includes: a first substrate in which a conductor circuit is formed on one surface of an insulating layer and an adhesive layer is formed on an other surface of the insulating layer, and conductors are formed in via holes that pass through the insulating layer and the adhesive layer so that the conductor circuit is partially exposed therefrom; an electronic component electrically connected to the conductor circuit by allowing electrodes of the electronic component to be connected to the conductors; an embedding member arranged around the electronic components so that the electronic component is embedded therein; and a second substrate having an adhesive layer laminated to face the adhesive layer of the first substrate and sandwich the electronic component and the embedding member, wherein each of the electrodes of the electronic component is continuous with the conductor circuit through two or more of the conductors.

Abstract: An embedded capacitor substrate module includes a substrate, a metal substrate and a solid electrolytic capacitor material. The solid electrolytic capacitor material is formed on the metal substrate, so as to form a solid electrolytic capacitor with the substrate. The embedded capacitor substrate module further includes an electrode lead-out region formed by extending the substrate and the metal substrate. The metal substrate serves as a first electrode, and the substrate serves as a second electrode. An insulating material is formed between the substrate and the metal substrate. Therefore, the embedded capacitor substrate module is not only advantageous in having a large capacitance as the conventional solid capacitor, but also capable of being drilled or plated and electrically connected to other circuits after being embedded in a printed circuit board.

Abstract: There is provided a multilayer ceramic electronic part to be embedded in a board including: a ceramic body including dielectric layers; an active layer including a plurality of first and second internal electrodes; upper and lower cover layers disposed on and below the active layer, respectively; and first and second external electrodes formed on both end portions of the ceramic body, wherein a first internal electrode positioned at an outermost position among the first electrodes is connected to the first external electrode by at least one first via extended to at least one of first and second main surfaces of the ceramic body, and a second internal electrode positioned at an outermost position among the second internal electrodes is connected to the second external electrode by at least one second via extended to at least one of first and second main surfaces of the ceramic body.

Abstract: There is provided a multilayer ceramic electronic component, including a ceramic body having first and second side surfaces facing each other, and first and second end surfaces facing each other; first and second internal electrodes having first and second lead portions; and first and second external electrodes extended from the first and second end surfaces of the ceramic body to the first and second side surfaces, respectively, wherein when a distance from an end portion of the first or second external electrode formed on the first or second side surface of the ceramic body to a point of the first or second external electrode connected to the first or second lead portion is defined as G, and a width of the first or second external electrode on the first or second side surface of the ceramic body is defined as BW, 30 ?m?G<BW is satisfied.

Abstract: A multilayer ceramic capacitor may include: a ceramic body including a plurality of dielectric layers; first and second internal electrodes disposed in the ceramic body, the first internal electrode having first and second lead portions exposed to a first surface of the ceramic body in a width direction, and the second internal electrode having a third lead portion exposed to the first surface of the ceramic body in the width direction; first to third external electrodes disposed on the first surface of the ceramic body in the width direction to be connected to the first to third lead portions, respectively; and an insulation layer disposed on the first surface of the ceramic body in the width direction. Each of the first and second lead portions may be spaced apart from the third lead portion by a predetermined distance.

Abstract: A method of manufacturing a wiring substrate that has a wiring including a through glass via and is formed of a glass substrate includes forming an alteration layer that penetrates the wiring substrate and is patterned, forming the wiring on a front surface of the wiring substrate in which the alteration layer has been formed, and filling an electrode material in a hole formed by removing the alteration layer, thereby forming the through glass via that connects the wiring on the front surface of the wiring substrate and the wiring on a back surface side thereof.

Abstract: An electronic device comprising a first magnetic powder; a second magnetic powder, wherein the mean particle diameter of the first magnetic powder is larger than the mean particle diameter of the second magnetic powder, the Vicker's Hardness of the first magnetic powder is greater than the Vicker's Hardness of the second magnetic powder by a first hardness difference, and the first magnetic powder mixes with the second magnetic powder; and a conducting wire buried in the mixture of the first magnetic powder and the second magnetic powder; wherein by means of the first hardness difference of the first magnetic powder and the second magnetic powder, the mixture of the first magnetic powder and the second magnetic powder and the conducting wire buried therein are combined to form an integral magnetic body at a temperature lower than the melting point of the conducting wire.

Abstract: There is provided an array type multilayer ceramic electronic component including a ceramic body having a plurality of dielectric layers stacked in a length direction, a first capacitor part including a plurality of first and second internal electrodes alternately exposed through both side surfaces of the ceramic body, a second capacitor part disposed to be spaced apart from the first capacitor part and including a plurality of third and fourth internal electrodes, a first external electrode formed on one side surface, a second external electrode disposed to be spaced apart from the first external electrode, formed on one side surface of the ceramic body, and a third external electrode formed on the other side surface of the ceramic body.

Abstract: A chip-on-glass device comprises a chip-on-glass substrate, a metal layer, and a plurality of chip-on-glass connection bumps. The metal layer comprises a plurality of passive jumper routing traces. The plurality of chip-on-glass connection humps is coupled with passive jumper routing traces of the plurality of passive jumper routing traces.

Abstract: There is provided a multilayer ceramic electronic component to be embedded in a board, including a ceramic body including dielectric layers and having first and second main surfaces facing each other, first and second side surfaces facing each other, and first and second end surfaces facing each other, an active layer including a plurality of first and second internal electrodes alternately exposed through both end surfaces of the ceramic body with the dielectric layers interposed therebetween, to form capacitance therein, upper and lower cover layers formed on upper and lower portions of the active layer, and first and second external electrodes formed on both end surfaces of the ceramic body, wherein when a thickness of the upper or lower cover layer is defined as tc, 4 ?m?tc?20 ?m may be satisfied.

Abstract: There is provided a multilayer ceramic electronic part to be embedded in a board, including: a ceramic body including dielectric layers and having first and second main surfaces facing each other, first and second side surfaces facing each other, and first and second end surfaces facing each other; first and second internal electrodes; and first and second external electrodes formed on both end portions of the ceramic body, wherein the first external electrode includes a first base electrode and a first terminal electrode formed on a portion of the first base electrode formed on at least one of the first and second main surfaces of the ceramic body, the second external electrode includes a second base electrode and a second terminal electrode formed on a portion of the second base electrode formed on at least one of the first and second main surfaces of the ceramic body.

Abstract: An electronic module includes a substrate, a built-in electronic component and a surface mount electronic component. A suckable region is provided on a front surface of the substrate. When viewed in a see-through manner in a direction perpendicular or substantially perpendicular to the front surface of the substrate, the suckable region is inside of a region in which one built-in electronic component is built in and a center of gravity of the electronic module is located inside of the suckable region. A protective layer is not provided on the front surface of the substrate on which the surface mount electronic component is mounted.

Abstract: A method for manufacturing a wiring board for mounting an electronic component, a wiring board for mounting an electronic component, and a method for manufacturing an electronic-component-mounted wiring board are provided. A bonding material paste, which can include solder and an electric insulation material made of a resin, can be placed on chip mount terminal pads and heated to fuse the solder and soften the electric insulation material. Subsequently, the solder is solidified to form solder bumps. Further, the electric insulation material is cured on a surface of each of the solder bumps and a surface of a multilayer board around each of the solder bumps to form an electric insulation surface layer. Accordingly, when a chip is mounted to such wiring boards, the electric insulation surface layer minimizes or eliminates the connection between adjacent solder bumps during re-fusing of the solder.

Abstract: A method for electrically interconnecting two substrates, each having a corresponding set of preformed electrical contacts, the substrates comprising an electronic circuit, and the resulting module, is provided. A liquid curable adhesive is provided over the set of contacts of a first substrate, and the set of electrical contacts of the second substrate is aligned with the set of electrical contacts of the first substrate. The sets of electrical contacts of the first and second substrate are compressed to displace the liquid curable adhesive from the inter-contact region, and provide electrical communication between the respective sets of electrical contacts. The liquid curable adhesive is then cured to form a solid matrix which maintains a relative compression between the respective sets of electrical contacts. One embodiment of the module comprises a high-speed superconducting circuit which operates at cryogenic temperatures.

Abstract: A substrate structure has a first surface and a second surface. A plurality of carrying members are formed on the first surface and a plurality of conductive traces are formed on the second surface. In addition, the substrate structure has a first, a second and a third thermal stress relief structures. The first thermal stress relief structure is that lengths of the substrate structure in different axial directions are substantially equal to each other. The second thermal stress relief structure is that a plurality of separated alignment marks are formed on the substrate structure. The third thermal stress relief structure is that the substrate structure has at least one clearance area extending along one of the axial directions of the substrate structure and the clearance area has no carrying members and no conductive traces formed thereon.

Abstract: There is provided a multilayer ceramic capacitor including a ceramic body including a plurality of dielectric layers stacked in a width direction, a plurality of first and second internal electrodes, first and second lead parts having at least one space part and extended from the first internal electrode to be exposed through the bottom surface of the ceramic body and be spaced apart from each other in a length direction, a third lead part positioned between the first and second lead parts and extended from the second internal electrode, first and second external electrodes formed on the bottom surface of the ceramic body and electrically connected to the first and second lead parts, respectively, and a third external electrode formed between the first and second external electrodes and electrically connected to the third lead part.

Abstract: There is provided a multilayer ceramic capacitor includes a ceramic body including dielectric layers and having first and second main surfaces facing each other, first and second side surfaces facing each other, and first and second end surfaces facing each other; a capacitor part formed in the ceramic body and including a first internal electrode having a lead exposed to the first side surface and a second internal electrode exposed to the second end surface; first to third internal connecting conductors formed in the ceramic body and having at least one polarity; and first to fourth external electrodes electrically connected to the first and second internal electrodes and the first to third internal connecting conductors, wherein the first and second internal connecting conductors and the third internal connecting conductor are connected in parallel, and the first to third internal connecting conductors and the capacitor part are connected in series.

Abstract: There is provided a multilayer ceramic capacitor including a ceramic body including a plurality of dielectric layers and having first and second main surfaces, first and second side surfaces, and first and second end surfaces, a capacitor part formed in the ceramic body and including a first internal electrode exposed to the first and second end surfaces and a second internal electrode having a lead-out portion exposed to the first main surface, an internal connection conductor formed in the ceramic body and exposed to the first and second main surfaces, and first to fourth external electrodes formed on outer surfaces of the ceramic body and electrically connected to the first and second internal electrodes and the internal connection conductor, wherein the internal connection conductor is connected to the capacitor part in series.

Abstract: Disclosed herein are a printed circuit board having an embedded electronic device and a method of manufacturing the same. According to a preferred embodiment of the present invention, the printed circuit board having an embedded electronic device includes: a core substrate having circuit layers formed on both surfaces thereof; a taper-shaped cavity formed on the core substrate; and an electronic device embedded in the cavity.

Abstract: There is provided a multilayer ceramic capacitor includes a ceramic body including dielectric layers; first and second external electrodes formed on end surfaces of the ceramic body; first and second terminal electrodes formed on side surfaces of the ceramic body; an active layer including a first internal electrode simultaneously connected to the first terminal electrode and the first external electrode and a second internal electrode simultaneously connected to the second terminal electrode and the second external electrode; upper and lower cover layers formed above and below the active layer; and third and fourth internal electrodes disposed to face each other on a single dielectric layer of the upper or lower cover layer and connected to the first and second terminal electrodes, respectively.

Abstract: There is provided a multilayer ceramic capacitor including: a ceramic body; first and second internal electrodes disposed to face each other within a ceramic body, and having respective lead portions exposed to an upper surface of the ceramic body; first and second external electrodes formed on the upper surface of the ceramic body and connected to the lead portions, respectively; and first and second terminal frames each including a vertical portion facing end surfaces of the ceramic body and upper and lower horizontal portions facing upper and lower surfaces of the ceramic body, respectively, wherein the upper horizontal portions are connected to the first and second external electrodes, respectively, and adhesive layers are provided between the upper horizontal portions and the first and second external electrodes, respectively.

Abstract: There is disclosed a supply feed network for an envelope tracking power amplifier arrangement comprising a power amplifier and a voltage modulator for providing a supply voltage to the power amplifier, the supply feed network comprising: a power distribution plane arranged to connect the supply voltage from the voltage modulator to the power amplifier.

Abstract: A printed circuit board includes an insulating layer; a via in the insulating layer, a first circuit layer formed at a first side of the insulating layer and having a portion buried in the via; a second circuit layer formed at a second side of the insulating layer and electrically connected with the portion of the first circuit layer in the via.

Abstract: A multilayer ceramic capacitor may include three external electrodes disposed on a mounting surface of a ceramic body and spaced apart from each other, and first and second lead-out portions extended from a first internal electrode so as to be exposed through the mounting surface of the ceramic body and spaced apart from each other in a length direction of the ceramic body have one or more space portions, respectively, and a board for mounting thereof is provided.

Abstract: A wiring board includes a first resin insulation layer, an electronic component positioned on first surface of the first insulation layer, a second resin insulation layer formed on the first surface of the first insulation layer such that the second insulation layer is embedding the electronic component, a conductive layer formed on the second insulation layer, a third resin insulation layer formed on the conductive layer and second insulation layer, and a connection via conductor formed in the second insulation layer such that the connection via conductor is connecting electrode of the electronic component and conductive layer on the second insulation layer. The first insulation layer has a pad structure on second surface side of the first insulation layer on opposite side of the first surface, and the first insulation layer has coefficient of thermal expansion set lower than coefficients of thermal expansion of the second and third insulation layers.

Abstract: Disclosed are an insulating material (high-k layer) which includes a fiber assembly mainly composed of a cellulose nanofiber, and an electroconductive metal material supported by the fiber assembly; and a passive element (capacitor) which includes a high-k layer which is composed of the insulating material, and an electroconductive part stacked on the high-k layer.

Abstract: An electronic structure includes a substrate body, an electronic package structure and a conductive unit. The electronic package structure is disposed on the substrate body. The electronic package structure includes a first inner electrode portion, a second inner electrode portion, a first outer electrode portion electrically connected to the first inner electrode portion, and a second outer electrode portion electrically connected to the second inner electrode portion. The conductive unit includes a first conductive body and a second conductive body respectively electrically contacting the first and the second outer electrode portions. The electronic package structure has a first notch and a second notch, the first outer electrode portion is extended into the first notch to contact the top surface of the first inner electrode portion, and the second outer electrode portion is extended into the second notch to contact the top surface of the second inner electrode portion.

Abstract: The present invention provides a display substrate for reducing resistance deviation occurring in a fan out unit, and a display apparatus including the display substrate. According to the present invention, resistance units are disposed in lines having a relatively short length in an area where lengths of adjacent lines increase or decrease non-linearly, and the adjacent lines have substantially equal resistance or have linear resistance variation.

Abstract: A wiring substrate includes a substrate main body having a first main face and a second main face opposite the first main face; a resistor formed on the first main face; a plurality of first-main-face-side wiring layers which are each formed on the resistor and which each include a grounding metal layer formed of a metal having a resistance lower than that of the resistor and a conductor layer formed on the grounding metal layer; a second-main-face-side wiring layer formed on the second main face; and a via which is formed in the substrate main body and which establishes electrical connectivity between the first-main-face-side wiring layers and the second-main-face-side wiring layer. The wiring substrate further includes a conductive covering layer which covers an upper surface and substantially covers the side surfaces of each of the first-main-face-side wiring layers.

Abstract: An assembler receives a circuit board. The circuit board includes at least a first node and a second node that are adjacent but electrically isolated from each other. There is a gap between the first node and the second node. The first node is electrically isolated from other components on the circuit board. The second node is electrically coupled to circuitry residing on the circuit board. The assembler initiates positioning of a conductive lead of a battery in a vicinity of the first node. The gap between the first node and second node initially prevents the live conductive lead from being in electrical contact with the second node. Eventually, the assembler bridges the gap to provide an electrical connection between at least the conductive lead and the second node to electrically couple the conductive lead to the second node and thus the circuitry residing on the circuit board.

Abstract: There is provided a multilayer ceramic capacitor including a ceramic body having first and second main surfaces, third and fourth end surfaces, and fifth and sixth side surfaces; a plurality of first and second internal electrodes having a dielectric layer to be alternately exposed to the third and fourth end surfaces; and first and second external electrodes formed on the end surfaces and the main surfaces and electrically connected to the first and second internal electrodes, wherein when a width of the first or second external electrode is A and a length of a margin part of the ceramic body in the length direction is B, a ratio (A/B) of the width of the first or second external electrode to the length of the margin part of the ceramic body in the length direction is 3.3 or less (A/B?3.3).

Abstract: A fanout line structure of an array substrate includes first fanout lines arranged on a fanout area of the array substrate, and second fanout lines arranged on the fanout area of the array substrate. A second conducting film is arranged at a bottom of the second fanout line, a second capacitor is formed between the second conducting film and a first conducting film of the second fanout line, the second capacitor is used to reduce an impedance difference between the fanout lines. Capacitance value of the second capacitor is dependent on an overlapping area between the second conducting film and the first conducting film.

Abstract: There is provided a multilayer ceramic capacitor including, a ceramic body including a plurality of dielectric layers, a plurality of first and second internal electrodes disposed in the ceramic body to be alternately exposed through the double side surfaces facing each other in a width direction, having the dielectric layers therebetween, and first and second external electrodes formed on the surfaces of the ceramic body in the width and thickness directions and electrically connected to the first and second internal electrodes, wherein when a length of the ceramic body is defined as L and a width of the ceramic body is defined as W, a ratio L/W of the length L to the width W of the ceramic body satisfies 1.39?L/W?2.12.

Abstract: An electronic component is provided with: an electronic component body including a top face, a bottom face, a pair of side faces, and a pair of end faces provided with an outside electrode; and a pair of metal terminals individually connected to the pair of outside electrodes of the electronic component body, wherein the metal terminals is electrically and mechanically connected to the outside electrode of the electronic component body, and is also in contact with bottom face of the electronic component. The electronic component requires no jig or a simple jig if any for securing a metal terminal and electronic component body in place.

Abstract: A method of manufacturing a printed circuit board (PCB) having an embedded bare chip includes attaching a tape to one side of an insulated substrate having a penetration hole formed therein, and attaching the bare chip onto the tape inside the penetration hole such that electrode pads of the bare chip face the tape; filling up the penetration hole with a filler, and removing the tape; laminating a metal layer onto a surface of the filler and the insulated substrate from which the tape is removed; and forming electrode bumps by removing portions of the metal layer. The forming of electrode bumps further includes simultaneously removing portions of the metal layer and forming an circuit pattern on one side of the insulated substrate. The circuit pattern is formed directly on the upper side of the insulated substrate and the electrode bumps are formed on the surface of the electrode pads.

Abstract: An object of the present invention is to propose a functional element built-in substrate which enables an electrode terminal of a functional element to be well connected to the back surface on the side opposite to the electrode terminal of the functional element, and which can be miniaturized.

Abstract: There is provide a manufacturing method of a fin-integrated substrate capable of producing by simple process a fin-integrated substrate with heat radiating fins at fine pitches by a processing method in which warpage of a metal base plate and corrugation (wavy shape) of the heat radiating fins are suppressed. There is provided a manufacturing method of a fin-integrated substrate in which bonding of the metal circuit board to the ceramic substrate is performed by a molten metal bonding method, and formation of the plurality of heat radiating fins at a cut part that is a part of the metal base plate is performed by fixing by a jig to apply a tensile stress on a surface of the cut part where the heat radiating fins are to be formed, and performing grooving processing of forming a plurality of grooves by moving a multi-cutter composed of a plurality of stacked disc-shaped cutters, on the surface to which the tensile stress is applied, while rotating the multi-cutter.

Abstract: A method, and apparatus resulting from the method, for fabricating a circuit board suitable for mounting electronic components. The method includes drilling a plurality of through-holes in a plurality of dielectric sheets, forming a conductive film on at least one side of each of the plurality of dielectric sheets, and substantially filling each of the plurality of through holes with a conductive material. The conductive material is both electrically and thermally uninterrupted from a first face to a second face of each of the plurality of dielectric sheets. The plurality of dielectric sheets are then sequentially mounted, one atop another, to form the circuit board. The sequential mounting step is performed after the steps of drilling the plurality of through-holes, forming the conductive layer, and substantially filling the plurality of through-holes.

Abstract: Structures and methods for forming good electrical connections between an integrated circuit (IC) chip and a chip carrier of a flip chip package include forming one of: a tensile layer on a front side of the IC chip, which faces a tops surface of the chip carrier, and a compressive layer on the backside of the IC chip. Addition of one of: a tensile layer to the front side of the IC chip and a compressive layer the backside of the IC chip, may reduce or modulate warpage of the IC chip and enhance wetting of opposing solder surfaces of solder bumps on the IC chip and solder formed on flip chip (FC) attaches of a chip carrier during making of the flip chip package.

Abstract: A wiring board includes a first insulating layer; a first wire that is provided at a first surface of the first insulating layer and transmits a first signal; and a second wire that is provided at a second surface of the first insulating layer that is opposite to the first surface, includes a first portion that is parallel to at least a portion of the first wire, and transmits a first component of the first signal that is transmitted through the first wire.

Abstract: A wiring board includes an insulating board, a wiring sub board having a wiring layer, and an insulating layer. The insulating layer has a via hole in which a conductor is formed by plating. The insulating board and the wiring sub board are horizontally laid out. The insulating layer is laid out to cover a boundary portion between the insulating board and the wiring sub board and continuously extends from the insulating board to the wiring sub board. A resin which constitutes the insulating layer is filled in the boundary portion. The conductor is electrically connected to the wiring layer.

Abstract: A component-embedded substrate includes an electrically insulating base (11) of resin, an electric or electronic embedded component (8) and a dummy embedded component (7) both embedded in the insulating base (11), a conductor pattern (18) formed on at least one side of the insulating base (11) and connected directly to or indirectly via a connection layer (6) to the embedded component (8) and the dummy embedded component (7), and a mark (10) formed on a surface of the dummy embedded component (7) and used as a reference when the conductor pattern (18) is formed, whereby positional accuracy of the conductor pattern (18) relative to the embedded component (8) can be improved.

Abstract: A method of forming solder-less printed wiring boards includes attaching a electronic components to a workpiece using an adhesive material. A mold material is added to partially cover the electronic components to form a sub-assembly including the electronic components attached to the mold material and a planar surface on the workpiece side. At least tops of the electronic components extend beyond a height of the mold material. The adhesive material is removed to separate the workpiece and sub-assembly. A first prepreg dielectric is attached to the planar surface of the mold material. First vias are formed in the first prepreg dielectric to expose bondable contacts of the electronic components. The first vias are filled with electrically conductive plugs to provide connections to the bondable contacts of the electronic components. A circuit layer is formed on a surface of the first prepreg dielectric to provide contact to the first plugs.

Abstract: Methods of forming coreless package structures comprising backside land side capacitors (LSC) and dual sided solder resist are described. Those methods and structures may include forming a nickel coating on a first and second side of a core, forming a conductive plating on the nickel coating, forming building up layers on the conductive plating to form two panels on the core, de-paneling the panels from the core to form two coreless substrates, forming a laminate on the first and second sides of the coreless substrates, and forming an LSC on a backside of the coreless substrates.