Abstract: There is provided a multilayered ceramic electronic component including a ceramic body having a hexahedral shape, including a dielectric layer, satisfying T/W>1.0 when a length thereof is L, a width thereof is W, and a thickness thereof is T, and having first and second main surfaces, first and second end surfaces, and first and second side surfaces, a plurality of first and second internal electrodes, and first and second external electrodes electrically connected to the first and second internal electrodes, wherein the first and second external electrodes are electrically connected to the exposed portions of the first and second internal electrodes, include first and second head parts formed on the first and second end surfaces, and first and second band parts formed on the first and second main surfaces, and are not formed on the first and second side surfaces.

Abstract: There are provided a multilayer ceramic electronic component and a board for mounting the same. The multilayer ceramic electronic component includes a hexahedral ceramic body including dielectric layers and satisfying T/W>1.0 when a width thereof is defined as W and a thickness thereof is defined as T; an active layer in which capacitance is formed, by including a plurality of first and second internal electrodes alternately exposed through both end surfaces of the ceramic body, having the dielectric layer interposed therebetween, an upper cover layer formed above the active layer; a lower cover layer formed below the active layer and having a greater thickness than the upper cover layer; and first and second external electrodes covering the end surfaces of the ceramic body, wherein when a thickness of the lower cover layer is defined as Tb, 0.03?Tb/T?0.25 is satisfied.

Abstract: The circuit substrate includes at least two lands formed on a substrate, wherein one electrode is to be mounted on the at least two lands, an electronic part having electrodes, one of the electrodes is soldered on the at least two lands with solders whose amounts are adjusted by a metal mask having at least two opening parts, positions of the at least two opening parts corresponding to the at least two lands when the solders are applied and melted, areas of the at least two opening parts being different with each other, wherein a height of one of the solders is different from a height of the other of the solders according to the difference of the areas of the at least two opening parts of the metal mask, whereby the electronic part is mounted on the circuit substrate in an inclined state.

Abstract: There is provided a multilayer ceramic electronic component including a ceramic body satisfying T/W>1.0 when a width and a thickness thereof are defined as W and T, respectively, a plurality of first and second internal electrodes having the respective dielectric layers interposed therebetween, and alternately exposed through both end surfaces of the ceramic body, and first and second external electrodes formed to be extended from the both end surfaces to both upper and lower main surfaces of the ceramic body, wherein, the ceramic body is formed such that a cross-section thereof in a width-thickness direction has a trapezoidal shape in which two sides among four sides are inclined in one direction, and when an angle formed by a bottom side and a side connected thereto is defined as ?, 86°??<90° is satisfied.

Abstract: There are provided a multilayer ceramic electronic component and a mounting board therefor, the multilayer ceramic electronic component including a ceramic body having a hexahedral shape, including dielectric layers, and satisfying T/W>1.0 when a length of the ceramic body is defined as L, a width of a lower surface of the ceramic body is defined as W, and a thickness of the ceramic body is defined as T, and first and second internal electrodes stacked in the ceramic body so as to face each other, having the respective dielectric layers interposed therebetween, wherein when a width of an upper surface of the ceramic body is defined as Wa, 0.800?Wa/W?0.985 is satisfied.

Abstract: Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods are disclosed. A system in accordance with one embodiment includes a support member having first package bond sites electrically coupled to leadframe bond sites. A microelectronic die can be carried by the support member and electrically coupled to the first packaged bond sites. A leadframe can be attached to the leadframe bond sites so as to extend adjacent to the microelectronic die, with the die positioned between the leadframe and the support member. The leadframe can include second package bond sites facing away from the first package bond sites. An encapsulant can at least partially surround the leadframe and the microelectronic die, with the first and second package bond sites accessible from outside the encapsulant.

Abstract: A device includes a wiring board, an element mounted on the wiring board, a spacer member intervening between the wiring board and the element to form a space therebetween, and an encapsulation body filling the space and encapsulating the element on the wiring board.

Abstract: A multilayer laminate package and a method of manufacturing the same are provided. The multilayer laminate package includes a cavity layer, a non-cavity layer, an electronic component, and a metalized blind via. The cavity layer includes a first adhesive layer and two first circuit layers, which are stacked with the first adhesive layer between, and an opening. The non-cavity layer includes a second adhesive layer and a second circuit layer. The non-cavity layer is bonded to the cavity layer with the second adhesive layer so as to close one side of the opening. The electronic component is mounted in the opening and is electrically connected to the non-cavity layer exposed through the opening. The metalized blind via electrically connects the non-cavity layer to one of the circuit layers of the cavity layer.

Abstract: There is provided a multilayer ceramic capacitor including a ceramic body including a plurality of dielectric layers and having first and second main surfaces, first and second side surfaces, and first and second end surfaces; a first capacitor part including a first internal electrode exposed to the first end surface and a second internal electrode exposed to the second side surface and a second capacitor part including a third internal electrode exposed to the first side surface and a fourth internal electrode exposed to the second end surface; an internal connection conductor exposed to the first and second side surfaces; and first to fourth external electrodes electrically connected to the first to fourth internal electrodes and the internal connection conductor, wherein the internal connection conductor is connected to the first and second capacitor parts in series.

Abstract: There is provided a multilayer ceramic capacitor including a ceramic body, first and second capacitor parts, first and second internal connection conductors, and first to fourth external electrodes, wherein the first capacitor part is connected to the first connection conductor in series, and the second capacitor part is connected to the second connection conductor in series, the second connection conductor being connected to the first connection conductor in series.

Abstract: A multilayer ceramic capacitor includes a ceramic body including dielectric layers and having first and second side surfaces opposing each other; a first capacitor part including a first internal electrode exposed to the first side surface and a second internal electrode exposed to the second side surface and a second capacitor part including a third internal electrode exposed to the first side surface and a fourth internal electrode exposed to the second side surface; first and second internal connection conductors exposed to the first and second side surfaces; and first to fourth external electrodes formed on the first and second side surfaces and electrically connected to the first to fourth internal electrodes and the first and second internal connection conductors, the first and second capacitor parts being connected in series with the first and second internal connection conductors, respectively.

Abstract: A multilayer ceramic electronic component includes a ceramic body including dielectric layers stacked in a thickness direction and satisfying T/W>1.0 when a width thereof is W and a thickness thereof is T; first and second internal electrodes; and first and second external electrodes, wherein when the ceramic body is divided into five regions in a width direction and a central region among the five regions is CW1 and regions adjacent to the central region CW1 are CW2 and CW3, a difference between electrode connectivity of the central region CW1 and electrode connectivity of the region CW2 or CW3 satisfies 0.02?(CW2 or CW3)?CW1?0.10.

Abstract: There is provided a multilayer ceramic electronic component including, a ceramic body including a plurality of dielectric layers stacked in a thickness direction, satisfying T/W>1.0 when a width and a thickness thereof are defined as W and T, respectively, and having a groove portion inwardly recessed in a length direction in at least one main surface thereof, a plurality of first and second internal electrodes disposed in the ceramic body to face each other, having the dielectric layers interposed therebetween, and alternately exposed through both end surfaces of the ceramic body, and first and second external electrodes formed to extend from the both end surfaces of the ceramic body to the at least one main surface having the groove portion formed therein.

Abstract: Memristive elements are provided that include an active region disposed between a first electrode and a second electrode. The active region includes an switching layer of a first metal oxide and a conductive layer of a second metal oxide, where a metal on of the first metal oxide differs from a metal ion of the second metal oxide. The memristive element exhibits a nonlinear current-voltage characteristic in the low resistance state based on the oxide hetero-junction between the first metal oxide and the second metal oxide. Multilayer structures that include the memristive elements also are provided.

Abstract: A multilayer ceramic electronic component includes a ceramic main body including dielectric layers and satisfying T/W>1.0 when W and T are width and thickness, respectively; and first and second internal electrodes stacked in the ceramic main body and facing each other with the dielectric layer interposed therebetween, the ceramic main body including an active layer corresponding to a capacitance forming portion contributing to capacitance formation and a cover layer corresponding to a non-capacitance forming portion provided on at least one of uppermost and lowermost surfaces of the active layer, and when the active layer is divided into three regions in a direction in which the first and second internal electrodes are stacked, an average width of internal electrodes in a central region of the three regions is Wa, and an average width of internal electrodes in upper and lower regions of the three regions is Wb, 0.920?Wb/Wa?0.998 is satisfied.

Abstract: There is provided a multilayered ceramic capacitor including a ceramic body including a plurality of dielectric layers and having first and second main surfaces, first and second side surfaces, and first and second end surfaces; a first capacitor part including a first internal electrode exposed to the first end surface and a second internal electrode exposed to the second end surface, and a second capacitor part including a third internal electrode exposed to the first end surface and a fourth internal electrode exposed to the second side surface; an internal connection conductor exposed to the first and second side surfaces; and first to fourth external electrodes formed on the outer surfaces of the ceramic body and electrically connected to the first to fourth internal electrodes and the internal connection conductor, wherein the first capacitor part has capacitance larger than that of the second capacitor part.

Abstract: There is provided a multilayer ceramic capacitor including a ceramic body, first to third capacitor parts, first and second internal connection conductors, and first to fourth external electrodes, wherein the first capacitor part is connected in series with the second internal connection conductor, and the second capacitor part is connected in series with the first internal connection conductor.

Abstract: A method is for making an electronic device and includes forming an interconnect layer stack on a sacrificial substrate and having a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers. The method also includes laminating and electrically joining through an intermetallic bond a liquid crystal polymer (LCP) substrate to the interconnect layer stack on a side thereof opposite the sacrificial substrate. The method further includes removing the sacrificial substrate to expose a lowermost patterned electrical conductor layer, and electrically coupling at least one first device to the lowermost patterned electrical conductor layer.

Abstract: A device includes a substrate, a first antenna connection, and a first retention mechanism. The substrate has a top surface and a bottom surface. The first antenna connection is mounted directly to the top surface of the substrate, and is configured to connect with a first antenna. The first retention mechanism is connected at a first location of the bottom surface of the substrate to provide support for the substrate at the first antenna connection when the first antenna connection is connected to the first antenna. The first location of the first retention mechanism is selected to be directly below the first antenna connection.

Abstract: A module includes a multilayer body including laminated ceramic green sheets that have been fired, multiple mounting terminals arranged to mount a component thereon, the mounting terminals each including an end surface that is exposed at a main surface of the multilayer body, and multiple via conductors disposed inside the multilayer body so as to correspond to the mounting terminals at positions overlapped by the corresponding mounting terminals when viewed in a plan view. The lengths of the via conductors are adjusted so that predetermined points on the mounting terminals are positioned on the same plane.

Abstract: A multilayer wiring substrate includes a multilayer body in which a plurality of insulating layers is stacked and to which an electronic component is mounted, a plurality of connection terminals disposed on one principal surface of the multilayer body for connection to the electronic component, and a plurality of rear electrodes disposed on the other principal surface of the multilayer body, wherein the connection terminals are each arranged in overlapped relation to one of the rear electrodes when looked at in a plan view of the multilayer wiring substrate.

Abstract: A circuit substrate includes a base substrate provided with a first pad and a second pad which are electrically connected to an electronic component, a first lateral face and a second lateral face, a first terminal electrically connected to the first pad and a second terminal electrically connected to the second pad which are disposed on the first lateral face, and a third terminal and a fourth terminal which are disposed on the second lateral face. The first terminal and the fourth terminal are located at point-symmetric positions to a center of the base substrate. The second terminal and the third terminal are located at point-symmetric positions to the center of the base substrate. The third terminal and the fourth terminal are electrically connected to each other.

Abstract: A fixing mechanism for fixing an electronic component is disclosed in the present invention. The fixing mechanism includes a first casing, a boss disposed on the first casing. The electronic component is disposed on the boss. The fixing mechanism further includes a resilient component disposed on the boss and located between the first casing and the electronic component, a circuit board putting on the electronic component and fixed on the first casing, and a second casing pressing the circuit board and fixed on the first casing. The circuit board contacts against the electronic component tightly by an assembly of the first casing and the second casing.

Abstract: This relates to systems and methods for providing one or more vias through a module of an electrical system. For example, in some embodiments, the module can include one or more passive elements and/or active of the electrical system around which a packaging has been plastic molded. The module can be stacked under another component of the electrical system. Vias can then be provided that extend through the module. The vias can include, for example, electrically conductive pathways. In this manner, the vias can provide electrical pathways for coupling the component stacked on top of the module to other entities of an electronic device including the electrical system. For example, the component can be coupled to other entities such as other components, other modules, printed circuit boards, other electrical systems, or to any other suitable entity.

Abstract: The method includes forming an annular seat and main marks on a metal layer simultaneously so that the annular seat opposes with a terminal of an electronic component when the component is placed above the annular seat at a subsequent step; then positioning the electronic component in a mounting expected region using the main marks and mounting the electronic component with an adhesive layer therebetween; then burying the electronic component and the main marks in an insulating substrate; then removing part of the metal layer and thereby forming first and second windows; then irradiating the adhesive layer with laser using the exposed main marks thereby forming a laser via hole; and then filling the laser via hole with copper and forming a wiring pattern from the metal layer electrically connected to the terminal through a conductive via.

Abstract: A method of fabricating packaging for a product comprises forming a plurality of conductive tracks on a sheet of material and forming a physical barrier, such as a hole, for impeding fluid flow between adjacent conductive tracks. The method may further comprise depositing first and second regions conductive fluid onto adjacent first and second conductive tracks either side of the physical barrier and mounting an electronic device having first and second terminals such that the electronic device forms a bridge over the physical barrier and the first ands second terminals contact the first and second conductive adjacent tracks.

Abstract: A printed wiring board is configured such that copper-laminated plates and prepregs are alternately laminated and surface conductive layers are arranged on the outermost positions outside the prepregs, wherein all leading wires from pads for surface-mount parts to be mounted on the surface of the printed wiring board are connected to inner conductive layers of the copper laminated plates through blind via holes connecting the surface conductive layer and the copper-laminated plate therebelow, and inner via holes connecting conductive layers on the top and rear surfaces of at least one of the copper-laminated plates that is nearest to the surface conductive layer are provided and a conductive film is formed in the inner via holes.

Abstract: Various aspects of the present invention provide a transfer method for peeling off an MIM structure (comprising lower electrode/dielectric layer/upper electrodes) film formed on a supporting substrate and then transferring onto a transfer substrate with sufficiently uniform and low damage. Various aspects of the present invention also provide a thin film element provided with one or more thin film components which are transferred onto a substrate by using said method.

Abstract: A circuit board includes a solder wettable surface and a metal mask configured to restrict solder from flowing outside the solder wettable surface of the circuit board.

Abstract: A microelectronic assembly includes a first surface and a first thin conductive element exposed at the first surface and having a face comprising first and second regions. A first conductive projection having a base connected to and covering the first region of the face extends to an end remote from the base. A first dielectric material layer covers the second region of the first thin element and contacts at least the base of the first conductive projection. The assembly further includes a second substrate having a second face and a second conductive projection extending away from the second face. A first fusible metal mass connects the first projection to the second projection and extends along an edge of the first projection towards the first dielectric material layer.

Abstract: A method for manufacturing a multilayer printed wiring board includes preparing a first resin insulative material having a first conductive circuit on or in the first resin insulative material, forming a second resin insulative material on the first resin insulative material and the first conductive circuit, forming on a surface of the second resin insulative material a first concave portion to be filled with a conductive material for formation of a second conductive circuit, forming on the surface of the second resin insulative material a pattern having a second concave portion and post portions to be filled with the conductive material for formation of a plane conductor, and filling the conductive material in the first concave portion and the second concave portion such that the second conductive circuit and the plane conductor are formed.

Abstract: A suspension substrate of the present invention includes an insulating layer, a spring material layer, and a plurality of wirings, wherein one wiring of the plurality of wirings includes a head-side wiring part and a plurality of division wiring parts, respectively bifurcated from the head-side wiring part. The spring material layer includes a spring-material-layer main body, a first spring-material-layer separated body and a second spring-material-layer separated body. The division wiring parts of the one wiring are respectively connected with the first spring-material-layer separated body, via a pair of conductive connection parts, respectively extending through the insulating layer. The first spring-material-layer separated body is located on one side relative to the longitudinal axis, while the second spring-material-layer separated body is located on the other side relative to the longitudinal axis.

Abstract: A circuit board provided with a first resin layer and with a first conductive layer formed on the first resin layer. The first conductive layer has a metal carbide layer containing a carbide of a transition metal selected from Group IV, Group V, or Group VI in the Periodic Table and bonded to the first resin layer. The first resin layer has a first region to which the metal carbide layer is bonded and a second region located in an inner portion of the first resin layer from the first region. The first region has a larger ratio of number of atoms of nitrogen relative to number of atoms of carbon than in the second region.

Abstract: Printed circuit board (PCB) assembly tooling and methods are provided. Particular tooling includes a first tooling fixture having a first core component receiver to receive a first portion of a magnetic core to be coupled to a first side of a PCB. The tooling also has a second tooling fixture including a second core component receiver to receive a second portion of the magnetic core to be coupled on a second side of the PCB to the first portion of the magnetic core. The tooling also has an alignment component disposed on at least one of the first tooling fixture and the second tooling fixture. The alignment component enables alignment of the first tooling fixture and the second tooling fixture. When the first tooling fixture and the second tooling fixture are aligned, the first portion of the magnetic core and the second portion of the magnetic core are aligned.

Abstract: A ceramic electronic component includes a ceramic body and an outer electrode. The ceramic body includes first and second principal surfaces, first and second lateral surfaces, and first and second end surfaces. The outer electrode is provided on the first principal surface. The outer electrode includes an underlying electrode layer containing Cu and glass, and a Cu plating layer. The underlying electrode layer is disposed on the first principal surface. The Cu plating layer is disposed on the underlying electrode layer. The Cu plating layer is thicker than the underlying electrode layer.

Abstract: There is provided a multilayer ceramic capacitor including a ceramic body including a plurality of dielectric layers and having first and second main surfaces opposing each other, first and second side surfaces opposing each other, and first and second end surfaces opposing each other, a plurality of internal electrodes having the dielectric layer interposed therebetween, electrode layers formed on the first and second end surfaces of the ceramic body and electrically connected to the plurality of internal electrodes, and an impact absorption layer formed on the electrode layer so that an edge thereof is exposed.

Abstract: An electronic device includes: a support member including a first terminal, a second terminal, and a support portion extending from the first terminal and coupling the first terminal with the second terminal; an electronic component; and a bonding member connecting the first terminal with the electronic component. In a plan view along a direction in which the first terminal and the electronic component overlap each other, a portion of the first terminal is adjacent to the support portion with a notch portion therebetween and protrudes toward the extending direction side of the support portion. The support portion is bent at a portion adjacent to the protruding portion of the first terminal along the overlapping direction.

Abstract: There is provided multilayer ceramic capacitor including, a ceramic body including a plurality of dielectric layers laminated therein, an active layer including a plurality of first and second internal electrodes alternately exposed through both end surfaces of the ceramic body, with the dielectric layers interposed therebetween, and having capacitance formed therein, an upper cover layer formed on an upper portion of the active layer, a lower cover layer formed on a lower portion of the active layer and having a thickness greater than that of the upper cover layer, first and second dummy electrode terminals provided in the lower cover layer to be alternately exposed through both end surfaces of the lower cover layer, and first and second external electrodes covering the both end surfaces of the ceramic body.

Abstract: A method of manufacturing a hollow surface mount type electronic component has a preparing step, a gluing step and a cutting step. The preparing step includes preparing a baseboard, a clapboard and a cover board, mounting multiple circuit segments and conducting points on two opposite faces of the baseboard at intervals and boring multiple through holes on the clapboard corresponding to the circuit segments. The gluing step includes mounting multiple electronic elements on the baseboard to connected with the circuit segments, gelatinizing glue on the boards to mount the clapboard between the baseboard and the cover board and pressing the boards by a pressing machine. The cutting step includes cutting the boards by a cutting machine to produce multiple single SDM electronic components.

Abstract: A printed wiring board includes an outermost interlayer resin insulation layer, n outermost conductive layer formed on the outermost interlayer resin insulation layer and including multiple alignment marks, a connection wiring structure connecting the alignment marks, and a solder-resist layer formed on the outermost interlayer resin insulation layer and the outermost conductive layer. The solder-resist layer has openings exposing the alignment marks, respectively, and each of the alignment marks has an electroless plated film formed on each of the alignment marks.

Abstract: An article for producing an integrated device includes a deformable layer and one or more components releasably attached on one surface of the deformable layer.

Abstract: A planar thermal dissipation patch comprises a polymer substrate; an adhesive layer attached under the polymer substrate; a protection sheet over the adhesive layer, the protection sheet is removed from the adhesive layer before attaching the planar thermal dissipation patch; a thermal dissipation layer formed on the polymer substrate; wherein the thermal dissipation layer is formed of CNT, conductive polymer, graphite or the combination thereof.

Abstract: A method of making an electronic device includes forming a circuit layer on a liquid crystal polymer (LCP) substrate and having at least one solder pad. The method also includes forming an LCP solder mask having at least one aperture therein alignable with the at least one solder pad. The method further includes aligning and laminating the LCP solder mask and the LCP substrate together, then positioning solder paste in the at least one aperture. At least one circuit component may then be attached to the at least one solder pad using the solder paste.

Abstract: An electronic component includes a laminated capacitor and a substrate-type terminal including a substrate main body, first and second component connection electrodes, first and second external connection electrodes, and first and second connection electrodes. The substrate main body is made of a material and has a thickness that significantly reduces or prevents vibration being transmitted to a circuit substrate on which it is mounted.

Abstract: A laminated electronic component includes a laminate including internal electrodes and dielectric layers laminated alternately and a first main surface, an external electrode that continuously covers at least one end surface of the laminate in a longitudinal direction and a portion of the first main surface adjacent to the one end surface, and a conductive elastic structure connected to the external electrode at at least corner portions of the first main surface in a portion where the external electrode covers the first main surface. The elastic structure includes a base portion connected to the external electrode to extend along the first main surface, and a branch portion branched from the base portion and extending at a position spaced from the first main surface to connect to another electrode, and having elasticity.

Abstract: In a component-embedded circuit substrate having a plurality of capacitors embedded therein, the capacitors are connected in parallel, inspection electrodes are formed, and the inspection electrodes connect to respective terminal electrodes of the capacitor through via conductors. At the terminal electrodes of the capacitor, the connection position of the via conductors for connecting the inspection electrodes differs from the connection position of via conductors for connecting respective terminal electrodes of the capacitor.

Abstract: A fabrication method for a low-cost high-frequency electronic device package having waveguide structures formed from the high frequency device to the package lead transition. The package lead transition is optimized to take advantage of waveguide interconnect structure.

Abstract: A method for manufacturing a printed circuit board includes forming an opening portion in a substrate, positioning chip capacitors in the opening portion of the substrate such that the chip capacitors are accommodated in the opening portion of the substrate, forming a buildup structure including an interlayer resin insulating layer and a conductive layer over a surface of the substrate and the chip capacitors accommodated in the opening portion of the substrate, and forming on a surface of the buildup structure bump structures positioned to mount an IC chip such that the chip capacitors in the opening portion of the substrate are positioned directly below the IC chip.

Abstract: In a particular embodiment, a device includes a substrate, a via that extends at least partially through the substrate, and a capacitor. A dielectric of the capacitor is located between the via and a plate of the capacitor, and the plate of the capacitor is external to the substrate and within the device.

Abstract: Disclosed is a fractional order capacitor comprising a dielectric nanocomposite layer of thickness t, comprising a first side, and a second side opposite the first side, a first electrode layer coupled to the first side of the dielectric nanocomposite layer, a second electrode layer coupled to the second side of the dielectric nanocomposite layer, a complex impedance phase angle dependent on at least a material weight percentage of filler material in a dielectric nanocomposite layer.