Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC component may include: a first conductive structure; a second conductive structure; and a material in contact with the first conductive structure and the second conductive structure, wherein the material has a first electrical conductivity before illumination of the material with optical radiation and a second electrical conductivity, different from the first electrical conductivity, after illumination of the material with optical radiation.

Abstract: A compact strain gage including a deformable substrate, at least one conductive pattern formed on the deformable substrate, an electrically insulating layer formed over the conductive pattern, at least one electrical connection pad formed over the electrically insulating layer and at least partially overlying the conductive pattern and at least one via extending through the electrically insulating layer and electrically connecting the conductive pattern to the at least one electrical connection pad.

Abstract: Integrated fan-out devices, wafer level packages, and methods of manufacturing the same are described herein. Die-attach pads and leveling film are used to attach a plurality of heterogeneous semiconductor dies to a substrate to align external contacts of the semiconductor dies at a first level. The leveling film may also be used during deposition of an encapsulant to at least partially fill a gap between the semiconductor dies. Once the leveling film is removed, a protection layer is formed over the semiconductor dies and within a recess of the encapsulant left behind by the leveling film during encapsulation. A redistribution layer and external connectors are formed over the protection layer to form the InFO device and an interposer may be attached to the redistribution layer to form the wafer level package.

Abstract: A surface mount technology (SMT) device can include an SMT interface on a given side of the SMT device. The SMT interface can include an interface ground plane formed of conductive material. The SMT interface can also include a plurality of signal pads formed of the conductive material. Each signal pad can be encircled by one of a plurality of isolation regions formed from a non-conductive region of the SMT interface. The SMT device is configured for mounting on a printed wiring board (PWB) that includes a board interface having substantially the same shape at the SMT interface.

Abstract: A component mount board includes a resin board, an electronic component, and a molding resin. A land conductor is provided in the resin board. The electronic component is mounted on a surface of the resin board, and includes a mounting terminal that is bonded to the land conductor. The resin board includes a body resin portion including the land conductor provided on a surface thereof, and a surface resin layer disposed on a surface of the body resin portion and made of a material of the same type as that of the body resin portion. A conductor is not provided on a surface of the surface resin layer. The surface resin layer includes a through hole at which the land conductor is exposed from the surface of the resin board. The mounting terminal is bonded to the land conductor via a bonding material filled in the through hole.

Abstract: The present invention is notably directed to a printed circuit board, or PCB. This PCB has two main surfaces, each delimited by lateral edges, as well as lateral surfaces, each meeting each of the two main surfaces at one lateral edge. The present PCB further comprises a row of solder pads, which extends along a lateral edge of the PCB. Each solder pad is formed directly at the lateral edge and/or directly on a lateral surface (meeting one of the two main surfaces at said lateral edge). I.e., each pad interrupts a lateral edge and/or an adjoining lateral surface. One or more chips, e.g., memory chips, can be mounted on such a PCB to form an IC package. The above solder pad arrangement allows particularly dense arrangements of IC packages to be obtained. The present invention is further directed to related devices and methods of fabrication thereof.

Abstract: Embodiments of an interconnect structure are provided, the interconnect structure including: a reference plane structure having a first major surface and a second major surface opposite the first major surface, the reference plane structure including a plurality of through holes from the first major surface to the second major surface; a plurality of conductive columns, each conductive column centered within a through hole; and a plurality of isolation structures, each isolation structure fills an annular region within the through hole between each conductive column and surrounding portion of the reference plane structure.

Abstract: An integrated circuit (IC) die and integrated circuit (IC) chip packages having such dies are described that leverage the symmetry of the arrangement of micro-bumps to advantageously reduce interposer cost and size requirements. In one example, an integrated circuit (IC) die is provided. The IC die includes a die body, a plurality of programmable tiles disposed in the die body, and a plurality of micro-bumps disposed in the die body. The die body includes a front face connecting a bottom exterior surface and a top exterior surface. A centerline of the die body is perpendicular to the front face and bifurcates the top exterior surface. At least two of the programmable tiles are of a common type. The micro-bumps adjacent the front face and coupled to the common type of programmable tiles have a substantially symmetrical orientation relative to a symmetry axis. The symmetry axis being one of (a) collinear with the centerline of the die body, or (b) parallel to the centerline of the die body.

Abstract: A technique relates to forming a chip assembly. Top and bottom chip stack elements containing solder pads and a solder material are provided. Soluble standoffs are applied to the bottom chip stack element. The chip stack elements are aligned to bring the top solder pad in proximity to the bottom solder pad and the temperature is raised to a temperature above the melting temperature of the solder material to form a connected chip assembly. The connected chip assembly is cooled to re-solidify the solder material and soluble standoffs are removed from the connected chip assembly.

Abstract: A semiconductor module includes: a module board, a plurality of chips mounted on the module board, and a plurality of array resistors mounted on the module board, the plurality of array resistors including at least a first array resistor.

Abstract: A flexible printed circuit (FPC) may have reduced-tolerance electrical connection pads that comprise a connection portion and an adjacent window portion, where the position of a component that is mechanically and electrically connected to the FPC is limited by the geometry of the connection portion of the respective connection pads. The window portion includes an area void of conductive material and bounded by the connection portion on one side and may be bounded by peripheral portions on the other sides, where the peripheral portions are significantly narrower than the connection portion. A portion of the peripheral portions extending from the connection portion may be tucked under a portion of the FPC cover layer to prevent peeling of the peripheral portions.

Abstract: A resin-encapsulated semiconductor device includes a semiconductor element mounted on a die pad portion, a plurality of lead portions arranged so that leading end portions thereof are opposed to the die pad portion, and thin metal wires for connecting together electrodes of the semiconductor element and the lead portions. Those members are partially encapsulated by a resin. A bottom surface part of the die pad portion and a lead bottom surface part, an outer surface part, and an upper end part of the lead portion are exposed from the encapsulation resin. After a cutout part devoid of the encapsulation resin is formed above a lead upper end part, a plating layer is formed on the lead bottom surface part and the lead upper end part.

Abstract: A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.

Abstract: A resin-encapsulated semiconductor device includes a semiconductor element mounted on a die pad portion, a plurality of lead portions arranged so that leading end portions thereof are opposed to the die pad portion, and thin metal wires connecting electrodes of the semiconductor element to the lead portions. An encapsulation resin encapsulates the die pad portion, semiconductor element and lead portions in such a manner that a bottom surface part of the die pad portion and a lead bottom surface part, lead outer surface part, and lead upper end part of the lead portions are exposed from the encapsulation resin. A plating layer is formed on the lead bottom surface parts and the lead upper end parts. The encapsulation resin has cutouts on a side surface thereof vertically above the portions of the lead upper end parts on which the plating layer is formed.

Abstract: Some implementations provide a semiconductor device that includes a first substrate, a die coupled to the first substrate, and a set of solder balls coupled to the first substrate. The set of solder balls is configured to provide an electrical connection between the die and a second substrate. The semiconductor device also includes at least one decoupling capacitor coupled to the die through the first substrate. The at least one decoupling capacitor is configured to provide an electrical connection between the die and the second substrate. The at least one decoupling capacitor is coupled to the first substrate such that the at least one decoupling capacitor is positioned between the first substrate and the second substrate. In some implementations, the second substrate is a printed circuit board (PCB). In some implementations, the first substrate is a first package substrate, and the second substrate is a second package substrate.

Abstract: A resin-encapsulated semiconductor device is manufactured by mounting semiconductor elements on respective die pad portions of a frame. Electrodes on the surface of the semiconductor elements are wire bonded to lead portions of the frame. The die pad portions, semiconductor elements and lead portions are encapsulated with resin, leaving a bottom surface part of the lead portions exposed. The lead portions are partially cut by a rotary blade from an upper side of the resin to form concave parts in the lead portions, which are wet-etched to form exposed lead upper end parts. A plated layer is formed on the lead upper end parts and the lead bottom surface parts. The remaining parts of the lead portions with the plated layer are cut to separate the resin-encapsulated semiconductor device into individual pieces.

Abstract: An electronic device includes an electronic component including a plurality of terminals and a circuit board on which the electronic component is mounted. The circuit board includes a board body, a plurality of electrode pads arranged on the board body, each of the electrode pads being connected to each of the terminals by solder, a first solder resist formed on the board body and having a plurality of first openings, each of the first openings accommodating each of the electrode pads, and a second solder resist formed on the first solder resist and having a plurality of second openings, each of the second openings being larger than each of the first openings and communicating with each of the first openings.

Abstract: Electrode protective films 13a and 13b are formed on the surface of the metal layer using imidazole preflux, as terminal electrodes 35a and 35b of an electronic component. The terminal electrodes of an electronic component on which the protective films are formed are fixed by electroconductive adhesives 33a and 33b supplied to mounting lands 40a and 40b. Thereby an electronic component mounting structure without change in resistance caused by electroconductive adhesives is provided.

Abstract: A fan out build up substrate stackable package includes an electronic component having an active surface including a bond pad. A package body encloses the electronic component, the package body having a first surface coplanar with the active surface of the electronic component. A buildup dielectric layer is applied to the active surface of the electronic component and the first surface of the package body. A circuit pattern is formed within the first buildup dielectric layer and electrically connected to the bond pad, the first circuit pattern including via capture pads. Via capture pad apertures extend through the package body and expose the via capture pads. In this manner, direct connection to the first circuit pattern, i.e., the first metal layer, of the fan out build up substrate stackable package is facilitated. Further, the fan out build up substrate stackable package is extremely thin resulting in extremely thin stacked assemblies.

Abstract: An interconnect array is described. The interconnect array comprises a pattern of adjacent interconnect tiles, each interconnect tile comprising ten interconnect locations including eight I/O signal connectivity locations forming a perimeter array having a corner I/O signal connectivity location, a center connectivity location surrounded by the eight I/O signal connectivity locations in the perimeter array being a first ground connectivity location or a power connectivity location, and a second ground connectivity location adjacent to the corner I/O signal connectivity location of the perimeter array and externally offset from the perimeter array to form an asymmetrically shaped interconnect tile. At least one interconnect tile of the pattern of adjacent interconnect tiles has a center connectivity location that is a power connectivity location.

Abstract: An electronic control unit-mounting electric junction box having a versatile structure configured to accommodate both external and built-in electronic control units. The junction box includes an external upper case that forms the mounting space of an electronic control unit by means of a recessed containing section opening to the outer surface of a case, and a built-in upper case that internally forms the mounting space of an electronic control unit by raising outward the bottom wall of the recessed containing section in the external upper case are standardized in a basic section with the position of the bottom wall excluded, and a lower case and a conducting path that are combined with the external upper case and the built-in upper case are standardized.

Abstract: The electronic component has a resin electrode which constitutes an external electrode on a face of a ceramic base body. At least a tip portion of a resin electrode region extended around another face of the body is bonded to the ceramic base body, and further a relationship between Rz1 and Rz2 satisfies the following requirement: Rz1>Rz2, Rz1>3.3 ?m, and Rz2<3.2 ?m, wherein Rz1 is a ten-point average surface roughness of a first region of a surface of the ceramic base body to which the tip portion is bonded, and Rz2 is a ten-point average surface roughness of a second region of the surface of the ceramic base body where the external electrode is not formed.

Abstract: A surface mounted electronic component is provided. The surface mounted electronic component includes a main body, a circuit element, a conductive electrode, and a virtual electrode. The circuit element is arranged in the main body. The conductive electrode is disposed on an outer surface of the main body, wherein the conductive electrode electrically is connected to the circuit element. The virtual electrode is disposed on the outer surface of the main body, wherein the virtual electrode lies near the conductive electrode. There is a distance between the virtual electrode and the conductive electrode.

Abstract: An interconnect array uses repeated application of an interconnect pattern (“tile”). The tile has eight I/O signal pins forming a perimeter array, a central pin that can be either a ground pin or an I/O power pin, and an offset ground pin. The I/O signal pins are associated with the same or multiple I/O banks. If the central pin is an I/O power pin, it is optionally associated with an I/O bank associated with one or more of the I/O signal pins.

Abstract: The package comprises a chip and a plurality of frame contact pads. The chip is attached to the frame contact pads in a die attach area with a die attach adhesive. The chips is coupled to frame contact pads outside the die attach area with connecting elements. The chip, the connecting elements and the frame contact pads outside the die attach area are anchored in an electrically insulating encapsulation. The frame contact pads each comprise a first patterned layer and a second patterned layer, which second layer has the surface that is exposed outside the encapsulation. At least a portion of the frame contact pads in the die attach area has a first patterned layer with a first pattern that comprises at least one flange/lead that is outside the second patterned layer when seen in perpendicular projection of the first layer on the second layer.

Abstract: An electronic component mounting structure includes a flexible circuit board having terminal connection patterns formed thereon and a light-emitting component provided with electrodes. The light-emitting component is placed on the flexible circuit board, and a synthetic resin casing is injection-molded to cover the light-emitting component and a portion of the flexible circuit board surrounding the light-emitting component placed thereon, whereby the electrodes of the light-emitting component and the terminal connection patterns of the flexible circuit board are connected in abutting contact with each other.

Abstract: The present invention provides a circuit board and a method for manufacturing the circuit board, the circuit board and method allowing a further shorter connection distance between electrodes of a semiconductor device, and also allowing a sufficient thickness of a solder pre-coat in a soldering process. The circuit board comprises bonding pads for being connected with bumps of a semiconductor element, which act as connection terminals, the bonding pads being arrayed in parallel lines on a surface of the circuit board, and, on the adjacent parallel lines, the bonding pads being positioned to form a zigzag pattern along the parallel lines longitudinally.

Abstract: An electronic carrier board is provided, including a carrier, at least two paired bond pads formed on the carrier, and a protective layer covering the carrier. The protective layer is formed with openings corresponding in position to the two bond pads. The openings are aligned in the same direction and expose at least a first sidewall and a second sidewall of each of the two bond pads. The first sidewall is perpendicular to an alignment direction of the bond pads and the second sidewall is parallel to the alignment direction of the bond pads. A distance between the first sidewall of at least one of the bond pads and a corresponding side of a corresponding one of the openings is at least about 50 ?m greater than a distance between the second sidewall of the at least one bond pad and a corresponding side of the corresponding opening.

Abstract: A wiring board includes a film base, a plurality of conductive wirings aligned on the film base, and protrusion electrodes formed of a plated metal in the vicinity of end portions of the conductive wirings, respectively. An outer surface at both side portions of the protrusion electrodes in cross section in a width direction of the conductive wirings defines a curve, and the protrusion electrodes in cross section in a longitudinal direction of the conductive wirings define a rectangular shape. The conductive wirings include a first conductive wiring having a wiring width of W1 and a second conductive wiring having a wiring width of W2 larger than W1, and the protrusion electrode on the first conductive wiring and the protrusion electrode on the second conductive wiring have a substantially same height.

Abstract: A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.

Abstract: In an electronic component package in which an electronic component mounted on a mounting substrate via external electrodes placed on the mounting substrate is covered by a mold resin, the electronic component has a component cover which covers elements placed on the lower face of a component substrate, and which forms cavities, and a protective member which is lower in elastic modulus than the mold resin is disposed in a portion which excludes portions joined with the external electrodes in a lower face of the component cover, and which is opposed to the cavities.

Abstract: An electronic carrier board is provided, including a carrier, at least two paired bond pads formed on the carrier, and a protective layer covering the carrier. The protective layer is formed with openings corresponding in position to the two bond pads. The openings are aligned in the same direction and expose at least a first sidewall and a fourth sidewall of each of the two bond pads. The first sidewall and the fourth sidewall are both perpendicular to an alignment direction of the bond pads. A distance between the first sidewall of at least one of the bond pads and a corresponding side of a corresponding one of the openings is at least about 50 ?m greater than a distance between the fourth sidewall of the at least one bond pad and a corresponding side of the corresponding opening.

Abstract: Provided is an electronic component including a pad provided on an active surface of a rectangular chip substrate, a resin protrusion provided along sides of the chip substrate, and a conductive portion which is electrically connected to the pad and which is formed out of a conductive film covering the surface of the resin protrusion. The resin protrusion includes a protruded body extending linearly and a plurality of the resin protrusions are provided on at least one side of the chip substrate to form a clearance in an intermediate portion of the side.

Abstract: A circuit board includes a film substrate, a plurality of wiring layers arranged in order on the film substrate, and bumps formed on the wiring layers, respectively. Each of the bumps is provided across a longitudinal direction of a corresponding one of the wiring layers so as to extend over regions on both sides of the wiring layer above the insulating substrate, and a cross sectional shape of the bump taken in the width direction of the wiring layer is such that a central portion is higher than portions on both sides of the central portion. Accordingly, the bumps formed on the wiring layers can be held with strength sufficient for practical use against the force applied in the lateral direction.

Abstract: A circuit board includes a film substrate, a plurality of wiring layers arranged in order on the film substrate, and bumps formed on the wiring layers, respectively. Each of the bumps is provided across a longitudinal direction of a corresponding one of the wiring layers so as to extend over regions on both sides of the wiring layer above the insulating substrate, and a cross sectional shape of the bump taken in the width direction of the wiring layer is such that a central portion is higher than portions on both sides of the central portion. Accordingly, the bumps formed on the wiring layers can be held with strength sufficient for practical use against the force applied in the lateral direction.

Abstract: A circuit board includes a film substrate, a plurality of wiring layers arranged in order on the film substrate, and bumps formed on the wiring layers, respectively. Each of the bumps is provided across a longitudinal direction of a corresponding one of the wiring layers so as to extend over regions on both sides of the wiring layer above the insulating substrate, and a cross sectional shape of the bump taken in the width direction of the wiring layer is such that a central portion is higher than portions on both sides of the central portion. Accordingly, the bumps formed on the wiring layers can be held with strength sufficient for practical use against the force applied in the lateral direction.

Abstract: An integrated circuit (IC) package includes a chip carrier and a chip mounted to the chip carrier. The chip carrier has a centrally located power delivery region and a peripherally located input-output (I/O) delivery region disposed in partially surrounding relationship to the power delivery region. Power and ground paths are disposed in the power delivery region and I/O signal paths are disposed in the I/O delivery region.

Abstract: To provide a printed wiring board where the impedance between pads through which differential signals pass has been set to a predetermined standard value. The printed wiring board includes a first conductor layer extending over an area excluding a hole formed for each pad group and filled with a dielectric, and a second conductor layer extending over an area containing areas facing the hole. The hole encompasses a plurality of areas facing predetermined respective pads which are adjacent to each other and which form the pad group from among the plurality of pads.