Multiple Frames Patents (Class 174/537)
  • Patent number: 9907186
    Abstract: An electronic package structure is provided, which includes: a carrier; at least one electronic component and a plurality of conductive elements disposed on the carrier; a metal frame bonded to the conductive elements; and an encapsulant formed on the carrier and the metal frame and encapsulating the electronic component and the conductive elements. The metal frame is exposed from the encapsulant to serve as an electrical contact. As such, instead of using a mold having a particular size corresponding to the electronic package structure as in the prior art, the present disclosure can use a common mold to form the encapsulant, thereby reducing the fabrication cost. The present disclosure further provides a method for fabricating the electronic package structure.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: February 27, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chih-Hsien Chiu, Chen-Wen Huang, Hsin-Lung Chung, Wen-Jung Tsai, Jia-Huei Hung, Fu-Tang Huang
  • Patent number: 9761511
    Abstract: An electronic component includes one or more circuits having electrical connections coupled therewith. The electrical connections include a lead frame as well as electrical wires coupling the circuit or circuits to respective portions of the lead frame. The electrical wires may be formed as one piece with the respective portion of the lead frame without joints therebetween, e.g., by 3D printing.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: September 12, 2017
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Federico Giovanni Ziglioli
  • Patent number: 9478517
    Abstract: In one embodiment, an electronic device package structure includes an electronic die having conductive pads on one surface. The one surface is further attached to at least one lead. A conductive layer covers at least one conductive pad and at least portion of the lead thereby electrically connecting the lead to the conductive pad.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: October 25, 2016
    Assignee: Amkor Technology, Inc.
    Inventors: Jong Sik Paek, Doo Hyun Park, Yoon Joo Kim, Seong Min Seo, Young Suk Chung
  • Patent number: 9355995
    Abstract: According to an exemplary implementation, a method includes utilizing a leadframe panel comprising a plurality of leadframe modules, each of the plurality of leadframe modules having a leadframe pad. The leadframe panel has a plurality of bars each having a plurality of grooves, where the plurality of bars connect the plurality of leadframe modules. The method further includes attaching a device to the leadframe pad. The method also includes molding the leadframe panel while leaving a bottom of the leadframe pad exposed. Furthermore, the method includes sawing through the plurality of grooves of the plurality of bars to singulate the plurality of leadframe modules into separate packaged modules.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: May 31, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Dean Fernando, Roel Barbosa
  • Patent number: 8946548
    Abstract: The present invention relates to prohibiting water ingress in enclosures designed to protect electronics or other stored objects from damage that would occur if the protected stored objects were submerged in water or other liquids. More particularly the present invention, a water ingress prevention enclosure eliminates the need for watertight doors and other sealing gaskets by utilizing an opening in the lowest portion of the enclosure to allow rising water to pressurize the ambient gas trapped in the enclosure thus forming a pressurized chamber to which liquid cannot rise. Embodiments of the invention include a system, apparatus, method and computer implemented code to enable monitoring and storage of one or more stored objects in a liquid-free environment.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: February 3, 2015
    Inventor: Dean Sanders
  • Publication number: 20150011101
    Abstract: A lead frame assembly having a lead frame made of a single layer, a housing substantially surrounding the lead frame, and a plurality of leads formed as part of the lead frame. The lead frame assembly also includes a plurality of interfaces, allowing various devices to interact with the lead frame, such as sensors, thermistors, solenoids, engine controllers, or electronic control units, or the like. The interfaces may be formed as part of the lead frame, oriented in different directions, and may be located in different planes, making the lead frame assembly suitable for applications with different packaging requirements. The interfaces may be a plurality of connectors, where one of the connectors has multiple rows of pins which are in communication with the rest of the connectors, facilitating the communication between the connector and various devices.
    Type: Application
    Filed: September 26, 2014
    Publication date: January 8, 2015
    Inventors: Donald J. Zito, Valentin M. Stefaniu, Gabriel Tirlea
  • Patent number: 8841559
    Abstract: To prevent the breakage of the joint between a ceramic substrate and a glass epoxy substrate. The copper column is formed by a wiredrawing step for drawing a copper wire formed linearly to a predetermined diameter; a cutting step for cutting the copper wire, which has been drawn in the wire drawing step, in a predetermined length; a pressing step for pressing one end of the copper wire, which has been cut in the cutting step, in a longitudinal direction to form a copper column member; and an annealing step for annealing the copper column member, which has been formed in the pressing step, by maintaining a heating period of 60 minutes or longer at 600° C. or higher. Thereby, the Vickers hardness of the copper column becomes is 55 HV or less and the copper column is softened.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: September 23, 2014
    Assignee: Senju Metal Industry Co., Ltd.
    Inventors: Yutaka Chiba, Shinichi Nomoto, Koji Watanabe
  • Patent number: 8797736
    Abstract: A casing includes a casing module and a support module. The casing module includes two side plates spaced apart from each other, a top-plate unit disposed between and perpendicular to the side plates, and a bottom plate spaced apart from and parallel to the top-plate unit. The side plates, the top-plate unit and the bottom plate define a first accommodating space for receiving a first electronic device. The support module is disposed between the top-plate unit and the bottom plate, and is removably caught in the top-plate unit to divide the first accommodating space into two second accommodating spaces for receiving two second electronic devices that differ in size from the first electronic device.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: August 5, 2014
    Assignee: Wistron Corporation
    Inventors: Chong-Xing Zhu, Te-Hsiung Hsieh
  • Patent number: 8796562
    Abstract: A combiner box includes a combiner module and an electrical connector unit disposed in a casing. The combiner module includes an insulating board, and plural first and second input electrodes disposed on opposite surfaces of the insulating board along a first direction and corresponding respectively to plural first and second input sockets of the casing. The second input sockets are disposed below and alternatingly arranged with the first input sockets along the first direction. The electrical connector unit includes plural first and second input terminals disposed in the first and second input sockets and electrically connected to the first and second input electrodes, respectively.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: August 5, 2014
    Inventor: Chi-Jen Yang
  • Patent number: 8643158
    Abstract: A semiconductor package is assembled using first and second lead frames. The first lead frame includes a die flag and the second lead frame includes lead fingers. When the first and second lead frames are mated, the lead fingers surround the die flag. Side surfaces of the die flag are partially etched to form an extended die attach surface on the die flag, and portions of the top surface of each of the lead fingers also are partially etched to form lead finger surfaces that are complementary with the etched side surfaces of the die flag. A semiconductor die is attached to the extended die attach surface and bond pads of the semiconductor die are electrically connected to the lead fingers. An encapsulating material covers the die, electrical connections, and top surfaces of the die flag and lead fingers.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: February 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Peng Liu, Qingchun He, Ping Wu
  • Publication number: 20120248590
    Abstract: A semiconductor package is assembled using first and second lead frames. The first lead frame includes a die flag and the second lead frame includes lead fingers. When the first and second lead frames are mated, the lead fingers surround the die flag. Side surfaces of the die flag are partially etched to form an extended die attach surface on the die flag, and portions of the top surface of each of the lead fingers also are partially etched to form lead finger surfaces that are complementary with the etched side surfaces of the die flag. A semiconductor die is attached to the extended die attach surface and bond pads of the semiconductor die are electrically connected to the lead fingers. An encapsulating material covers the die, electrical connections, and top surfaces of the die flag and lead fingers.
    Type: Application
    Filed: March 7, 2012
    Publication date: October 4, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Peng LIU, Qingchun He, Ping Wu
  • Patent number: 8153478
    Abstract: A method for manufacturing an integrated circuit package system includes: forming a die paddle; forming an under paddle leadframe including lower leadfingers thereon; attaching the under paddle leadframe to the die paddle with the lower leadfingers extending under the die paddle; attaching a die to the die paddle; and planarizing a bottom surface of the under paddle leadframe to separate the lower leadfingers under the die paddle.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: April 10, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Guruprasad Badakere Govindaiah, Arnel Trasporto
  • Patent number: 8027153
    Abstract: A lead frame for a quad flat no-lead package includes a plurality of units arranged in a matrix manner and each having four comers. Each of the corners extends outwards to define an attaching portion for attachment to a UV tape such that four sides of each of the units won't fly off when the sides are cut off.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: September 27, 2011
    Assignee: Lingsen Precision Industries, Ltd.
    Inventor: Feng-Chun Chung
  • Patent number: 7989931
    Abstract: An integrated circuit package system is provided including: forming a die paddle; forming an under paddle leadframe including lower leadfingers thereon; attaching the under paddle leadframe to the die paddle with the lower leadfingers extending under the die paddle; attaching a die to the die paddle; and planarizing the bottom surface of the under paddle leadframe to separate the lower leadfingers under the die paddle.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: August 2, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Guruprasad Badakere Govindaiah, Arnel Trasporto
  • Publication number: 20110180317
    Abstract: A package comprising an electronic component, a circuit substrate onto which the electronic component is mounted, and an interposer located between the electronic component and the circuit substrate, allowing them to be electrically connected with each other, wherein the interposer is composed of at least two sub-interposers, and the at least two sub-interposers lie in the same plane to be disposed only on electrode terminal-forming areas of both of the electronic component and the circuit substrate.
    Type: Application
    Filed: August 5, 2010
    Publication date: July 28, 2011
    Inventors: Eiji Takahashi, Yoshiyuki Saito
  • Publication number: 20090152002
    Abstract: An optoisolator leadframe assembly includes: an emitter leadframe part including a first rail and a plurality of emitter leadframe units, each rail including two rows of emitter leadframes, each having a die-mounting pad; and a receiver leadframe part including a second rail and a plurality of receiver leadframe units, each including two rows of receiver leadframes, each having a die-mounting pad. The die-mounting pads of the emitter leadframes of each row of each of the emitter leadframe units are respectively aligned with and spaced apart from the die-mounting pads of the receiver leadframes of an adjacent row of an adjacent one of the receiver leadframe units. Each of the emitter and receiver leadframe parts is a single piece.
    Type: Application
    Filed: May 21, 2008
    Publication date: June 18, 2009
    Inventors: Cheng-Hong Su, Chih-Hung Tzeng
  • Patent number: 7394029
    Abstract: A module includes a circuit board, a first terminal on a lower surface of the circuit board, a first electronic component on an upper surface of the circuit board, a first cover made of metal covering the first electronic component, a second electronic component on the lower surface of the circuit board, a terminal board provided under the lower surface of the circuit board, a second terminal on an upper surface of the terminal board, a third terminal provided on the lower surface of the terminal board, and a second cover made of metal covering the second electronic component. The second terminal faces the first terminal and is connected to the first terminal. The third terminal is connected to the second terminal. The terminal board has an opening therein surrounding the second electronic component. The second cover includes a top plate portion located under the second electronic component, and a side plate portion extending from the top plate portion toward the lower surface of the circuit board.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: July 1, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Junichi Kimura