Abstract: The present invention provides a semiconductor device including an insulating layer, a conductive layer bonded to one main surface of the insulating layer, a semiconductor element arranged such that the upper surface of the semiconductor element faces a direction same as the one main surface of the insulating layer, an upper electrode provided on the upper surface of the semiconductor element, a wiring member that has one end electrically bonded to the upper electrode of the semiconductor element and has another end electrically bonded to the conductive layer, and has a hollow portion, a first sealing material, and a second sealing material, in which the first sealing material seals at least part of the semiconductor element so as to be in contact with the semiconductor element, and the second sealing material seals the wiring member so as to be in contact with the wiring member.

Abstract: An embodiment of a transformer-based system or galvanic isolation device includes a first coil, a second coil aligned with the first coil across a gap, and a first capacitor coupled between the first coil and a first voltage reference. A first electrode of the first capacitor may be formed from a conductive electrode structure that is electrically isolated from the first coil, and a second electrode of the first capacitor may be formed from at least a portion of the first coil. The system or device also may include a second capacitor coupled between the second coil and a second voltage reference. The first and second coils may form portions of first and second IC die, respectively, and the system or device may also include one or more dielectric components within the gap between the IC die, where the dielectric component(s) are positioned directly between the first and second coils.

Abstract: A floating die package including a cavity formed through sublimation of a sacrificial die encapsulant and sublimation or separation of die attach materials after molding assembly. A pinhole vent in the molding structure is provided as a sublimation path to allow gases to escape, whereby the die or die stack is released from the substrate and suspended in the cavity by the bond wires only.

Abstract: A sensor package structure includes a substrate, a sensor chip disposed on the substrate, a plurality of metal wires electrically connecting the substrate and the sensor chip, a glass cover disposed on the sensor chip, and an adhesive layer connecting the glass cover to the substrate. The substrate is made of a material having a coefficient of thermal expansion (CTE) that is less than 10 ppm/° C. The glass cover includes a board body and an annular supporting body connected to the board body. The annular supporting body of the glass cover is fixed onto the substrate through the adhesive layer, so that the glass cover and the substrate jointly surround an enclosed accommodating space. The sensor chip and the metal wires are arranged in the accommodating space, and the sensing region of the sensor chip faces the light-permeable portion of the board body.

Abstract: A display includes a display substrate having a patterned edge, the patterned edge including a plurality of notches. The display further includes a plurality of display signal lines supported by the display substrate on a first side of the display substrate, and a display control circuit disposed along a second side of the display substrate, the second side being opposite the first side. The display control circuit includes a plurality of contacts. Each display signal line of the plurality of display signal lines is disposed in a respective notch of the plurality of notches to traverse the patterned edge to establish an electrical connection between each display signal line of the plurality of display signal lines and a respective contact of the plurality of contacts.

Abstract: The method comprises the steps of 1) producing first and second blanks (EB1) including reserved-space defining means (HM1, HM2), by laminating insulating and conductive inner layers (PP, CP) on copper plates forming a base (MB1), at least one electronic chip being sandwiched between the blanks, said blanks being produced such that their upper lamination surfaces have matching profiles, 2) stacking and fitting the blanks via their matching profiles, and 3) press-fitting the blanks to form a laminated sub-assembly for an integrated power electronics device. The method uses IMS-type techniques.

Abstract: A module can include a module card and first and second microelectronic elements having front surfaces facing a first surface of the module card. The module card can also have a second surface and a plurality of parallel exposed edge contacts adjacent an edge of at least one of the first and second surfaces for mating with corresponding contacts of a socket when the module is inserted in the socket. Each microelectronic element can be electrically connected to the module card. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto.

Abstract: An optical modulator includes an optical modulation element that is accommodated in a housing. A plurality of lead pins, which are electrically connected to the optical modulation element through wire bonding, are fixed to a lateral wall of the housing. Each of the plurality of lead pins includes a portion that protrudes into an inner space (inner surface side) of the housing. A resonance suppressing structure (for example, a concave portion), which is configured to suppress resonance between the lead pins, is provided in a lateral wall portion to which the plurality of lead pins are fixed.

Abstract: An apparatus includes a substrate having a recess and a first insulator submerged in the recess of the substrate. The apparatus also includes a cover having a second insulator that, together with the first insulator, defines an insulated volume. The apparatus further includes one or more components to be cooled located over the first insulator and within the insulated volume. The apparatus could also include one or more electrical conductors located over the first insulator, where at least one of the one or more components is electrically connected to the one or more electrical conductors. The one or more electrical conductors could be submerged in the recess of the substrate. The one or more electrical conductors could be thermally-insulative at cryogenic temperatures and could include carbon nanotubes. The first and second insulators could include foam or aerogel insulation.

Abstract: An optical device includes a substrate, a semiconductor chip, a resin member, and a transparent plate. The semiconductor chip is provided on the substrate, and an optically functional layer is formed in a part of a top portion of the semiconductor chip. The resin member is provided on the substrate with a top surface and an inner side surface, and has a frame shape surrounding the optically functional layer. The resin member is integrally formed from a resin material, and includes a recessed portion provided at the intersection of the top surface and the inner side surface. The transparent plate is disposed in the recessed portion. The semiconductor chip, the resin member, and the transparent plate are arranged to define airspace.

Abstract: A semiconductor device and methods of forming are provided. The method includes bonding a second die to a surface of a first die. The method includes encapsulating the second die in an isolation material, and forming a through via extending through the isolation material. The method also includes forming a first passive device in the isolation material.

Abstract: A display includes a display substrate having a patterned edge, the patterned edge including a plurality of notches. The display further includes a plurality of display signal lines supported by the display substrate on a first side of the display substrate, and a display control circuit disposed along a second side of the display substrate, the second side being opposite the first side. The display control circuit includes a plurality of contacts. Each display signal line of the plurality of display signal lines is disposed in a respective notch of the plurality of notches to traverse the patterned edge to establish an electrical connection between each display signal line of the plurality of display signal lines and a respective contact of the plurality of contacts.

Abstract: A semiconductor chip package includes a semiconductor chip disposed over a main surface of a carrier. An encapsulation body encapsulates the chip. First electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a first side face of the encapsulation body. Second electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a second side face of the encapsulation body opposite the first side face. A first group of the first electrical contact elements and a second group of the first electrical contact elements are spaced apart by a distance D that is greater than a distance P between adjacent first electrical contact elements of the first group and between adjacent first electrical contact elements of the second group. The distances D and P are measured between center axes of electrical contact elements.

Abstract: A vehicle frame is disclosed. The vehicle frame may include an extruded metal hollow columnar beam defining in cross section, four interconnected arms, each having nine sidewalls and a bulbous free end, arranged to form a cross with thirty-six corners, and configured to dissipate axial compression loads via deformation of the thirty-six sidewalls and the thirty-six corners.

Abstract: A pad structure with a contact via array for high bond structure is provided. In some embodiments, a semiconductor substrate comprises a pad opening. An interconnect structure is under the semiconductor substrate, and comprises an interlayer dielectric (ILD) layer, a wiring layer, and the contact via array. The wiring layer and the contact via array are in the ILD layer. Further, the contact via array borders the wiring layer and is between the wiring layer and the semiconductor substrate. A pad covers the contact via array in the pad opening, and protrudes into the ILD layer to contact the wiring layer on opposite sides of the contact via array. A method for manufacturing the pad structure, as well as an image sensor with the pad structure, are also provided.

Abstract: A semiconductor chip package includes a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, a chip pad, and electrical contact elements connected with the semiconductor chip and extending outwardly. The encapsulation body has six side faces and the electrical contact elements extend exclusively through two opposing side faces which have the smallest surface areas from all the side faces. The semiconductor chip is disposed on the chip pad, and a main face of the chip pad remote from the semiconductor chip is at least partially exposed to the outside.

Abstract: An electronics assembly includes a plurality of first semiconductor chips each having a first load terminal and a second load terminal, a conductor structure having a first conductor strip, a second conductor strip and a third conductor strip, a plurality of first interference-suppression capacitors arranged on the conductor structure and each having a first capacitor terminal and a second capacitor terminal, and a heat sink. The first load terminal of each first semiconductor chip is electrically connected to the first conductor strip, the second load terminal of each first semiconductor chip is electrically connected to the third conductor strip, the first capacitor terminal of each first interference-suppression capacitor is electrically connected to the first conductor strip, the second capacitor terminal of each first interference-suppression capacitor is electrically connected to the second conductor strip, and the heat sink is electrically connected to the second conductor strip.

Abstract: A fan out type multi-chip stacked package includes a chip stacked assembly having a plurality of chips vertically stacked. The electrodes of the chips and one active surface among all active surfaces are not covered by the stacked chips. A plurality of flip-chip bumps of a dummy flip chip are coupled to the electrodes of the chips. An encapsulant encapsulates the chip stacked assembly and the flip-chip bumps. The encapsulant has a planar surface. The flip-chip bumps have a plurality of bonding surfaces exposed from and coplanar to the planar surface. A redistribution layer is disposed on the planar surface and includes a plurality of fan out circuits electrically connected the bonding surfaces of the flip-chip bumps. Thus, the package has better resistance against mold flow impact to effectively reduce the risk of wire sweeping.

Abstract: A module can include a module card and first and second microelectronic elements having front surfaces facing a first surface of the module card. The module card can also have a second surface and a plurality of parallel exposed edge contacts adjacent an edge of at least one of the first and second surfaces for mating with corresponding contacts of a socket when the module is inserted in the socket. Each microelectronic element can be electrically connected to the module card. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto.

Abstract: A stacked semiconductor device structure includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a recessed surface portion bounded by opposing sidewall portions extending outward to define a recessed region. A conductive layer is disposed along at least the recessed surface portion. The second semiconductor device is disposed within the recessed region and is electrically connected to the conductive layer. In one embodiment, the stacked semiconductor device is connected to a conductive lead frame and is at least partially encapsulated by a package body.

Abstract: An electronic device has a rear plate that includes a substrate rear layer, a substrate front layer and a dielectric intermediate layer between the substrate rear and front layers. An electronic structure is on the substrate front layer and includes electronic components and electrical connections. The substrate rear layer includes a solid local region and a hollowed-out local region. The hollowed-out local region extends over all of the substrate rear layer. The substrate rear layer does not cover at least one local zone of the dielectric intermediate layer corresponding to the hollowed-out local region.

Abstract: To provide a semiconductor module capable of shortening of the manufacturing tact time, reducing the manufacturing costs, and improving assembility. A semiconductor module (30) includes substrate (31) made of metal, an insulating layer (32) formed on the substrate (31), a plurality of wiring patterns (33a to 33d) formed on the insulating layer (32), a bare-chip transistor (35) mounted on a wiring pattern (33a) via a solder (34a); and a metal plate connector (36a, 36b) jointing an electrode (S, G) of the bare-chip transistor (35) and a wiring pattern (33b, 33c) via a solder (34b, 34c). The metal plate connector (36a, 36b) has a bridge shape, and has a flat surface and a center of gravity at a middle portion of the component.

Abstract: A surge-protected coaxial termination includes a metallic outer body, a center conductor extending through a central bore of the outer body, and a spark gap created therebetween to discharge high-voltage power surges. A plurality of dielectric insulators surrounds the center conductor on opposite sides of the spark gap. High impedance inductive zones surround the spark gap to form a T-network low pass filter that nullifies the additional capacitance of the spark gap. An enlarged portion of a center conductor mitigates deleterious effects of arcing. An axial, carbon composition resistor is disposed inside the outer body, and inside the dielectric insulator to absorb the RF signal, and prevent its reflection.

Abstract: A method of making a stacked chip layout includes placing a first active circuit block over a central processing chip having a first area, the first active circuit block having a second area less than the first area. The method further includes placing a second active circuit block over the first active circuit block, the second active circuit block having a third area less than the first area, wherein the second active circuit block partially overlaps the first active circuit block and exposes a portion of the first active circuit block. The method further includes placing a third active circuit block over the second active circuit block wherein the third active circuit block partially overlaps at least one of the first active circuit block or the second active circuit block, and the third active circuit block exposes at least a portion of the first and second active circuit blocks.

Abstract: A method for fabrication of a lid for a microelectronic device is described, wherein the microelectronic device comprises of a die and a laminate. A gel is formed having a coefficient of thermal expansion (CTE) within a threshold percentage value of either a CTE of the die or a CTE of the laminate of the microelectronics device. A metal piece is inserted into the gel to form a lid.

Abstract: An exposure device includes: a substrate having a first and second surface opposed to each other, wherein a light-emitting element array is mounted on the first surface; a protective sheet covering the second surface while exposing a part of the second surface in the vicinity of an edge of the substrate to define an exposed part of the second surface; a holder that supports a condenser lens array and that supports the substrate, with a gap formed between the holder and the exposed part of the substrate, to position the substrate such that light emitted from the light-emitting element array is condensed on a predetermined irradiation location through the condenser lens array; and a thermally-conductive sealant that covers the exposed part of the second surface of the substrate and seals the gap.

Abstract: A power module, having a printed circuit board core, which contains at least one electronic power component embedded in an insulating layer, the core being arranged between two heat dissipation plates, wherein each heat dissipation plate has a metal outer layer and a metal inner layer electrically separated from said metal outer layer by a thermally conductive, electrically insulating intermediate layer, and electrode terminals of the at least one power component are guided out from the core via terminal lines, wherein the printed circuit board core on both sides of the insulating layer has a conductor layer, at least one conductor layer is structured at least in portions, and each conductor layer is connected at least in portions via a conductive, metal intermediate layer to a metal inner layer of the heat dissipation plate, contacts run from the structured conductor layer to the electrode terminals of the at least one power component, and at least one power terminal of the at least one power component is co

Abstract: A method for producing a package includes preparing a base substrate provided with a low-melting glass and a lid, defoaming the low-melting glass by heating the low-melting glass to a temperature equal to or higher than the pour point in a reduced pressure atmosphere, and joining the base substrate and the lid to each other by superimposing the base substrate and the lid on each other through the low-melting glass, and then heating the low-melting glass to a temperature equal to or higher than the pour point in a reduced pressure atmosphere.

Abstract: A technique for forming an integrated circuit die that contains an integrated sensor is provided. The integrated circuit die may be configured such that the sensor is exposed to ambient environmental conditions such that the sensor may detect ambient conditions. The integrated circuit die may be generally protected from environmental exposure by a mold resin. The mold resin may be formed in areas outside of a sensor region. Resin bleed from the mold resin into the sensor region may be prevented by the use of a resin dam that extends from the surface of the integrated circuit die. The resin dam may surround the sensor region.

Abstract: A memory combination includes a first riser board, a second riser board, and a pivotal plate. The first riser hoard includes a plurality of first memory sockets of which long axis directions are parallel to each other. The second riser board includes a plurality of second memory sockets of which long axis directions are parallel to each other. Two end of the pivotal plate are pivotally connected to the first riser board and the second riser board based on an axial direction respectively. When the first and second riser boards rotate to be perpendicular to the pivotal plate, the first memory sockets face the second riser board, and the second memory sockets face the first riser board. The axial direction is perpendicular to the long axis directions of the first memory sockets and the long axis directions of the second memory sockets.

Abstract: In ultrasonic bonding of a metal terminal to a substrate pad, a thin buffer metal layer which is formed of a soft metal or a highly slidable metal is interposed between a terminal edge and a pad so as to prevent direct contact between an end of the terminal and the pad upon bonding. This makes it possible to prevent abrasion and a crack in the pad at the end of the terminal caused by pressure and an ultrasonic wave upon the ultrasonic bonding. This makes it possible to realize a compact bonded structure with high reliability.

Abstract: The embodiments described herein provide for a packaging configuration that provides leads or connections for a packaging substrate from opposing surfaces of a package. Through silicon vias (TSV) are provided in order to accommodate additional input/output (I/O) pins that smaller dies are supporting. Various combinations of packages are enabled through the embodiments provided.

Abstract: An electrical connection includes a first wire bonded to adjacent bond pads proximate to an edge of a die and a second wire having one end bonded to a die bond pad distal to the die edge and a second end bonded to a lead finger of a lead frame or a connection pad of a substrate. The second wire crosses and is supported by the first wire. The first wire acts as a brace that prevents the second wire from touching the edge of the die. The first wire also prevents the second wire from excessive lateral movement during encapsulation.

Abstract: A semiconductor device includes a substrate, a first pad that is formed above the substrate, a second pad that is formed above the substrate, an external terminal that is connected with the second pad, and a circuit that judges whether or not the first pad is connected with the external terminal, wherein a distance between the first pad and a side of the substrate opposed to the external terminal is different from a distance between the second pad and the side.

Abstract: A composite substrate made of a circuit board mounted on a lead frame is used for an electronic system package. High heat generated electronic components are adapted to mount on the lead frame and relatively low heat generated electronic components are adapted to mount on the circuit board. Metal lines are used for electrical coupling between the circuitry of the IC chip and the circuit board. An electronic system with the composite substrate gains both advantages—good circuitry arrangement capability from the circuit board and good heat distribution from the lead frame.

Abstract: An integrated circuit leaded stacked package system includes forming a no-lead integrated circuit package having a mold cap, and attaching a mold cap of an extended-lead integrated circuit package facing the mold cap of the no-lead integrated circuit package.

Abstract: Circuit modules including identification codes and a method of managing them are provided. A module substrate includes signal input output terminals and outer ground terminals provided at the peripheral portions of a surface which becomes a mounting surface when the circuit module is completed. An inner-ground-terminal formation area surrounded by the signal input output terminals and the outer ground terminals includes a plurality of inner ground terminals arranged in a matrix of rows and columns. One of the edge portions is a direction identification area. The inner ground terminal is not provided in the direction identification area, and a first identification code having information about the position of the module substrate is provided in the direction identification area.

Abstract: A packaged semiconductor is disclosed. The packaged semiconductor comprises a conductive integral frame that includes an inner portion and a ring portion encircling the inner portion, a semiconductor die that is mounted to a first surface of the inner portion of the conductive frame, and a casing that supports the conductive frame and covers the semiconductor die. Sections of the conductive frame that connect the inner portion to the ring portion are removed after the casing is applied to the conductive frame.

Abstract: A semiconductor device includes a substrate, a first pad, a second pad, and a third pad that are placed along one side of a perimeter of the substrate, a circuit that is formed above the substrate, and that is coupled to the first pad, a first external terminal that is coupled to the second pad, and a second external terminal that is coupled to the third pad, wherein the circuit generates a signal indicative of a connection configuration between the first pad and the first external terminal, wherein the third pad is placed adjacent to one of the first pad and the second pad, wherein, in a direction parallel to the one side of the perimeter of the substrate, the first pad, the second pad and the third pad have a first width, a second width and a third width, respectively, and wherein each of the first width of the first pad and the second width of the second pad is smaller than the third width of the third pad.

Abstract: An electronic component storing package which generates a large quantity of heat during operation and an electronic apparatus storing such an electronic component are provided. In the electronic component storing package and the electronic apparatus, a heat dissipating member (1) is used which comprising at least five layers including first metal layers (11) having good thermal conductivity and second metal layers (12) having a smaller coefficient of thermal expansion and less thickness compared with the first metal layers (11), the first metal layers (11) and second metal layers (12) being alternately stacked, the first metal layers uppermost and lowermost layers of the layers, a thickness of at least one internally-arranged first metal layer (11a) being thicker than that of the lowermost and uppermost layers.

Abstract: A semiconductor device includes a substrate, a first internal terminal, a second internal terminal, a third internal terminal, and a fourth internal terminal which are placed along perimeter of the substrate, a circuit formed above the substrate and coupled to the first internal terminal, a first external terminal coupled to the second internal terminal, a second external terminal coupled to the third internal terminal, and a third external terminal coupled to the fourth internal terminal and placed beside one side of the substrate where the second external terminal is located, wherein the circuit generates a signal indicative of a connection state between the first internal terminal and the first external terminal, and wherein the first internal terminal and the second internal terminal are arranged to form two rows in a direction perpendicular to one side of the substrate beside which the first external terminal is placed.

Abstract: An electrical device has a housing and a housing surface, at least one electrical conductor accommodated in said housing and interrupting said housing surface in sections so that said housing surface is interrupted, a conductive body which covers said conductor on said interrupted housing surface, and at least two spacers which keep said conductive body apart from said at least one conductor.

Abstract: The present invention provides a circuit board and a method for manufacturing the circuit board, the circuit board and method allowing a further shorter connection distance between electrodes of a semiconductor device, and also allowing a sufficient thickness of a solder pre-coat in a soldering process. The circuit board comprises bonding pads for being connected with bumps of a semiconductor element, which act as connection terminals, the bonding pads being arrayed in parallel lines on a surface of the circuit board, and, on the adjacent parallel lines, the bonding pads being positioned to form a zigzag pattern along the parallel lines longitudinally.

Abstract: The present invention is characterized by a structure having a substrate 1, and metallization layers 2 formed on the substrate 1, on which a Sn solder film 3 and an Ag film 4 are formed. The Ag film 4 is a metal free from oxidization at room temperature in the atmosphere. In a wet process, since only an exposed side of the Sn solder film 3 is oxidized by the cell reaction of Ag and Sn, an upper surface of the Ag film 4 on the solder film, which would otherwise affect the connection, is not oxidized. Since the Ag film 4 melts into the Sn solder simultaneously with melting of the Sn solder film 3, the Ag film 4 does not hinder the connection.

Abstract: A semiconductor device according to the present invention includes first through fourth internal terminals placed along the perimeter of a substrate, a circuit coupled to the first internal terminal, a first external terminal coupled to the second internal terminal, a second external terminal coupled to the third internal terminal, and a third external terminal coupled to the fourth internal terminal. The circuit outputs a signal indicative of a connection state the first internal terminal and the first external terminal. A distance between centers of the first and second internal terminals is L1 in a direction parallel to one side of the substrate beside which the first external terminal is placed. A distance between centers of the third and fourth internal terminals is L2 in a direction parallel to one side of the substrate beside which the second and third external terminals are placed. The distance L1 is set smaller than the distance L2.

Abstract: A housing for an electronic circuit is provided with a single-part seal for sealing a clearance space between a floor plate and a cover, through which exposed electrical conductors are led, which connect the circuit on the inside of the housing to the surroundings. The floor plate, the cover and the conductors are made of the same kind of material, e.g., a metal. The floor plate and the cover are made of aluminum and the conductors of copper.

Abstract: An electronic circuit formed by removing only a baseboard from an electronic module. The electronic circuit may be formed by providing a baseboard made of a water-soluble material, applying a water-soluble polymer as an insulating material to the baseboard, and forming an electronic module by mounting electronic parts to wires formed on the baseboard. The formation of the electronic circuit may also include removing the baseboard from the electronic module by dissolving the baseboard in water and deforming and resin-encapsulating the electronic module, which includes the electronic parts and wires in the state of lacking the baseboard.

Abstract: A circuit substrate includes a first rigid substrate having a plurality of land portions located at a predetermined interval on one surface, a second rigid substrate having a plurality of second land portions located at a predetermined interval on one surface and a flexible wiring board sandwiched by the first and second rigid substrates and which has a plurality of third land portions corresponding to the first land portions on one surface and a plurality of fourth land portions corresponding to the second land portions on the other surface. In this circuit substrate, the second and fourth land portions are displaced from each other relative to the first and third land portions and at least part of the first and third land portions and at least part of the second and fourth land portions are electrically connected to each other, respectively.

Abstract: A multi-chip device which includes a plurality of integrated circuit die disposed one over another. Each integrated circuit die includes one or a plurality of bond pads. One or a plurality of conductors are disposed to electrically couple the bond pads of vertically adjacent integrated circuit die. Each conductor is designed, calculated, specified and/or predetermined to have a length so as to behave as a segment in a multi-drop transmission line. The multi-drop transmission line may be terminated at one end or utilized in a flow-through approach. In one embodiment, an integrated circuit die may be horizontally offset with respect to a vertically adjacent integrated circuit die to expose the periphery region. In another embodiment, each integrated circuit die may be stacked and aligned in a vertical column. In this embodiment, a spacer such as a thermally conductive spacer is disposed between each integrated circuit die in the stack.