Organic Patents (Class 204/192.36)
  • Patent number: 11211548
    Abstract: This spin current magnetization reversal element includes a magnetoresistance effect element having a first ferromagnetic metal layer having a fixed magnetization direction, a second ferromagnetic metal layer having a variable magnetization direction, and a non-magnetic layer sandwiched between the first ferromagnetic metal layer and the second ferromagnetic metal layer, and spin-orbit torque wiring which extends in a first direction that intersects the stacking direction of the magnetoresistance effect element, and contacts the surface of the magnetoresistance elect element on the side facing the second ferromagnetic metal layer, wherein at least one surface of the second ferromagnetic metal layer in the stacking direction has an inclined surface that is inclined in the first direction, and the direction of magnetization of the second ferromagnetic metal layer is inclined due to the inclined surface.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: December 28, 2021
    Assignee: TDK CORPORATION
    Inventors: Tomoyuki Sasaki, Tatsuo Shibata, Tohru Oikawa
  • Patent number: 10825576
    Abstract: The present invention relates to an apparatus for the generation, the distribution and/or the usage of electrical energy. The apparatus comprises a housing enclosing an insulating space and an electrically conductive part arranged in the insulating space, said insulating space containing a dielectric insulation medium, at least a portion of which being in the form of an insulation gas comprising an organofluorine compound. According to the invention, at least some of the components of the apparatus that are directly exposed to the insulation gas are made of a material which remains unaltered during exposure to the insulation gas for a period of more than 1 year at operational conditions and/or have a surface, at least a portion of which is devoid of any nucleophilic group reactive towards the organofluorine compound and/or reactive towards any degradation product thereof at operational conditions.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: November 3, 2020
    Assignee: ABB POWER GRIDS SWITZERLAND AG
    Inventors: Anna Di-Gianni, Bernhard vonAllmen, Denis Tehlar, Navid Mahdizadeh, Thomas Alfred Paul
  • Patent number: 10644239
    Abstract: The method for producing an OLED micro-display on a silicon wafer uses a collimating shadow mask formed on a silicon substrate. The mask is fabricated by depositing a material layer on the front side and on the back side of the substrate and etching a portion of the layer on the back side of the substrate to a reduced thickness of at least 20 microns. At least one opening is created in the etched portion of the substrate. The substrate beneath the opening is removed to create the mask. The mask is situated at a location spaced from the surface of the silicon wafer and exposed to a linear evaporation source. Organic layers are then deposited on the silicon wafer in a location aligned with the mask opening.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: May 5, 2020
    Assignee: eMagin Corporation
    Inventors: Amalkumar Ghosh, Fridrich Vazan
  • Patent number: 10297449
    Abstract: A method for manufacturing thin film transistor, a method for manufacturing array substrate, an array substrate and a display device are provided. The method for manufacturing thin film transistor includes forming an intermediate layer on a substrate, patterning the intermediate layer to form an intermediate layer reserved region and an intermediate layer unreserved region, where the intermediate layer unreserved region corresponds to a pattern of a first structure layer, forming, on the substrate with a pattern of the intermediate layer, a material layer from which the first structure layer is formed, and removing the intermediate layer, and forming the pattern of the first structure layer through a portion of the material layer remaining on the substrate.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: May 21, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zijin Lin, Haisheng Zhao, Xiaoguang Pei, Zhilong Peng, Dongjiang Sun
  • Patent number: 10269632
    Abstract: A method of forming a semiconductor device is provided. Metallic interconnects are formed in a dielectric layer of the semiconductor device. A hard mask is used to avoid usual problems faced by manufacturers, such as possibility of bridging different conductive elements and via patterning problems when there are overlays between vias and trenches. The hard mask is etched multiple times to extend via landing windows, while keeping distance between the conductive elements to avoid the bridging problem.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ming-Hui Chu, Chih-Yuan Ting, Jyu-Horng Shieh
  • Patent number: 9741614
    Abstract: A method of forming trenches and a via by self-aligned double patterning includes providing a dielectric layer covered by an SiOC layer, a TiN layer and a SiON layer from top to bottom. At least two mandrels are formed on the SiOC layer. Later, two spacers are formed respectively at two sidewalls of each mandrel. Subsequently, the mandrels are removed. The SiOC layer and the TiN layer are patterned by using the spacers to form numerous recesses. The spacers are then removed. A mask layer with a via pattern is formed to cover the SiOC layer. A via is formed in the dielectric layer by taking the mask layer as a mask. After that, the mask layer is removed. Finally, numerous trenches are formed in the dielectric layer by taking the SiOC layer and the TiN layer as a mask.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: August 22, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Patent number: 9716035
    Abstract: An embodiment semiconductor device includes a substrate and a dielectric layer over the substrate. The dielectric layer includes a first conductive line and a second conductive line. The second conductive line comprises a different conductive material than the first conductive line.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: July 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-I Yang, Yung-Chih Wang, Cheng-Chi Chuang, Chia-Tien Wu, Tien-Lu Lin
  • Patent number: 9646854
    Abstract: Embodiments describe the selective electroless plating of dielectric layers. According to an embodiment, a dielectric layer is patterned to form one or more patterned surfaces. A seed layer is then selectively formed along the patterned surfaces of the dielectric layer. An electroless plating process is used to deposit metal only on the patterned surfaces of the dielectric layer. According to an embodiment, the dielectric layer is doped with an activator precursor. Laser assisted local activation is performed on the patterned surfaces of the dielectric layer in order to selectively form a seed layer only on the patterned surfaces of the dielectric layer by reducing the activator precursor to an oxidation state of zero. According to an additional embodiment, a seed layer is selectively formed on the patterned surfaces of the dielectric layer with a colloidal or ionic seeding solution.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: May 9, 2017
    Assignee: Intel Corporation
    Inventors: Yonggang Yong Li, Aritra Dhar, Dilan Seneviratne, Jon M. Williams
  • Patent number: 9599896
    Abstract: In an embodiment a radical inhibitor is included within a photoresist in order to reduce the amount of cross-linking that occurs during subsequent processing, such as an ion implantation process, that would otherwise form a crust within the photoresist. The crust can be removed in a separate process, such as a dry etch with an oxidative or reductive etchant. Alternatively, the crust may be treated to make it more hydrophyilic such that it can be removed simultaneously with the photoresist.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chih Chen, Cheng-Han Wu, Ching-Yu Chang
  • Patent number: 9564344
    Abstract: Improved methods for stripping photoresist and removing ion implant related residues from a work piece surface are provided. According to various embodiments, plasma is generated using elemental hydrogen, a fluorine-containing gas and a protectant gas. The plasma-activated gases reacts with the high-dose implant resist, removing both the crust and bulk resist layers, while simultaneously protecting exposed portions of the work piece surface. The work piece surface is substantially residue free with low silicon loss.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: February 7, 2017
    Assignee: Novellus Systems, Inc.
    Inventors: David Cheung, Haoquan Fang, Jack Kuo, Ilia Kalinovski, Zhao Li, Guhua Yao, Anirban Guha, Kirk J. Ostrowski
  • Patent number: 9162427
    Abstract: There are provided a method for manufacturing a surface-modified fluororesin film capable of long-term inventory storage, a method for manufacturing a rubber composite composed of the surface-modified fluororesin film and rubber bonded together, and a rubber product for medical use made of the rubber composite. The method for manufacturing a surface-modified fluororesin film comprises the step of performing surface roughening on a fluororesin film RF by applying an ion beam from an anode layer ion source to the surface of the fluororesin film RF. A rubber is placed over the roughened surface of the thusly produced surface-modified fluororesin film, and, through vulcanization molding process, the surface-modified fluororesin film and the tuber can be firmly bonded to each other.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: October 20, 2015
    Assignee: SUMITOMO RUBBER INDUSTRIES, LTD.
    Inventors: Hiroaki Nakano, Eiji Yao
  • Publication number: 20150075973
    Abstract: The invention relates to a method of pre-cleaning a semiconductor structure and to associated modular semiconductor process tools. The method includes the steps of: (i) providing a semiconductor structure having an exposed dielectric layer of an organic dielectric material, wherein the dielectric layer has one or more features formed therein which expose one or more electrically conductive structures to be pre-cleaned, in which the electrically conductive structures each include a metal layer, optionally with a barrier layer formed thereon, and the surface area of the exposed dielectric layer is greater than the surface area of the electrically conductive structures exposed by the dielectric layer; and (ii) pre-cleaning the semiconductor structure by performing an Ar/H2 sputter etch to remove material from the exposed electrically conductive structures and to remove organic dielectric material from the exposed dielectric layer.
    Type: Application
    Filed: September 11, 2014
    Publication date: March 19, 2015
    Inventors: ALEX THEODOSIOU, STEVE BURGESS
  • Patent number: 7875199
    Abstract: The method for generating radicals comprises: feeding F2 gas or a mixed gas of F2 gas and an inert gas into a chamber of which the inside is provided with a carbon material, supplying a carbon atom from the carbon material by applying a target bias voltage to the carbon material, and thereby generating high density radicals, wherein the ratio of CF3 radical, CF2 radical and CF radical is arbitrarily regulated by controlling the target bias voltage applied to the carbon material while measuring the infrared absorption spectrum of radicals generated inside the chamber.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: January 25, 2011
    Assignee: Showa Denko K.K.
    Inventors: Toshio Goto, Masaru Hori, Mikio Nagai
  • Publication number: 20100230385
    Abstract: A method (and apparatus) of imprint lithography, includes imprinting, via a patterned mask, a pattern into a resist layer on a substrate, and overlaying a cladding layer over the imprinted resist layer. A portion of the cladding layer is used as a hard mask for a subsequent processing.
    Type: Application
    Filed: May 26, 2010
    Publication date: September 16, 2010
    Applicant: International Business Machines Corporation
    Inventors: Matthew E. Colburn, Theodore G. Van Kessel, Yves C. Martin, Dirk Pfeiffer
  • Patent number: 7005239
    Abstract: A method of forming a metal line includes the steps of forming a metal layer on a substrate in a chamber while maintaining a chamber pressure for a plasma to be equal to or smaller than 0.8 Pa, and coating a photoresist on the metal layer.
    Type: Grant
    Filed: December 16, 2002
    Date of Patent: February 28, 2006
    Assignee: LG.Philips LCD Co., Ltd.
    Inventor: Hu Kag Lee
  • Patent number: 6868856
    Abstract: Methods and apparatus for cleaning semiconductor processing equipment. The apparatus include both local and remote gas dissociators coupled to a semiconductor processing chamber to be cleaned. The methods include introducing a precursor gas into the remote dissociator where the gas is dissociated and introducing a portion of the dissociated gas into the chamber. Another portion of the dissociated gas which re-associates before introduction into the chamber is also introduced into the chamber where it is again dissociated. The dissociated gas combines with contaminants in the chamber and is exhausted from the chamber along with the contaminants.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: March 22, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Thomas Nowak, Ian Latchford, Tsutomu Tanaka, Bok Heon Kim, Ping Xu, Jason Foster, Heath B. DeShong, Martin Seamons
  • Patent number: 6746960
    Abstract: Techniques are used to detect and identify analytes. Techniques are used to fabricate and manufacture sensors to detect analytes. An analyte (1810) is sensed by sensors (1820) that output electrical signals in response to the analyte. The electrical signals are preprocessed (1830) by filtering and amplification. In an embodiment, this preprocessing includes adapting the sensor and electronics to the environment in which the analyte exists. The electrical signals are further processed (1840) to classify and identify the analyte, which may be by a neural network.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: June 8, 2004
    Assignee: California Institute of Technology
    Inventor: Rodney M. Goodman
  • Publication number: 20040079632
    Abstract: A method of depositing a film on a substrate disposed in a substrate processing chamber. In one embodiment the method includes depositing a first portion of the film to at partially fill a gap formed between to adjacent features formed on the substrate. The first portion of film is deposited using a high density plasma formed from a first gaseous mixture flown into the process chamber. The film deposition process is then stopped before or shortly after the entry of the gap pinches off and the film is etched to widen entry to the gap using a two step etching process that includes a first physical etch step and a subsequent chemical etch step. The physical etch step sputter etches the first portion of film by forming a plasma from a sputtering agent introduced into the processing chamber and biasing the plasma towards the substrate. After the physical etching step, the film is chemically etched by forming a plasma from a reactive etchant gas introduced into the processing chamber.
    Type: Application
    Filed: October 23, 2002
    Publication date: April 29, 2004
    Applicant: Applied Materials, Inc.
    Inventors: Farhan Ahmad, Michael Awdshiew, Alok Jain, Bikram Kapoor
  • Publication number: 20030121772
    Abstract: A method of forming a metal line includes the steps of forming a metal layer on a substrate in a chamber while maintaining a chamber pressure for a plasma to be equal to or smaller than 0.8 Pa, and coating a photoresist on the metal layer.
    Type: Application
    Filed: December 16, 2002
    Publication date: July 3, 2003
    Applicant: LG.Philips LCD. Co., Ltd
    Inventor: Hu Kag Lee
  • Patent number: 6451373
    Abstract: A method of coating an implantable prosthesis by applying a composition including a therapeutic substance and a fluid to the prosthesis and removing the fluid is disclosed. The fluid is not capable of significantly dissolving the therapeutic substance. A second fluid in which the therapeutic substance is soluble may be further included in the composition. Methods of providing the composition and a roughened polymeric primer layer are also disclosed.
    Type: Grant
    Filed: August 4, 2000
    Date of Patent: September 17, 2002
    Assignee: Advanced Cardiovascular Systems, Inc.
    Inventors: Syed F. A. Hossainy, Debbie Sanders-Millare, Steven Z. Wu
  • Patent number: 6409891
    Abstract: Cryofilm/organic contaminants are removed from cryogenically cooled surfaces such as spacecraft cryo-telescope mirrors by sputtering and chemical reaction with a low energy plasma having an average ion energy of not more than about 30 eV, and preferably in the approximate range of 5-20 eV. When the reactive plasma's freezing point is higher than the temperature of the surface to be cleaned, the cryofilm and embedded hydrocarbons are first removed with a non-reactive plasma having a freezing point less than the surface temperature, the reactive plasma is then used to remove residual organic contaminants left on the surface by chemical reaction, and finally another inert plasma is applied to remove reactive plasma frozen to the surface; the two inert plasmas are preferably formed from the same gas.
    Type: Grant
    Filed: April 29, 1994
    Date of Patent: June 25, 2002
    Assignee: Hughes Electronics Corporation
    Inventors: Barret Lippey, Darrell A. Gleichauf, Weldon S. Williamson
  • Patent number: 6338776
    Abstract: The present invention is directed to allowing a work piece to stabilize in regard to temperature and humidity/water content prior to precision operations so as to minimize any problems resulting from dimensional changes.
    Type: Grant
    Filed: February 24, 2000
    Date of Patent: January 15, 2002
    Assignee: Honeywell International Inc.
    Inventor: Richard J. Pommer
  • Publication number: 20020000370
    Abstract: The use of ion beam processing in preparation of a substrate's surfaces, particularly a polyimide film such as Upilex®-SS, prior to depositing a metal on the substrate surfaces. In one aspect, the ion beam processing can be used to remove relatively unique forms of surface contaminants without requiring additional cleaning by traditional methods such as chemical or plasma cleaning. In another aspect, the ion beam processing utilizing an anode layer ion source can be used to prepare polyimide films prior to metal deposition to produce substrates having surprisingly good peel strengths. In still another aspect, ion beam processing can be used to minimize differences in surface characteristics between opposite sides of a substrate.
    Type: Application
    Filed: August 4, 1999
    Publication date: January 3, 2002
    Inventors: RICHARD J. POMMER, GLEN ROETERS, STEPHEN M. AVERY