Abstract: Methods for producing flexible circuits can include creating treating a surface of the flexible circuit with at least one of an atmospheric plasma and a beam of ions. The atmospheric plasma is formed by directing a flow of gas between an electrode and the surface of the flexible circuit and generating a voltage between the electrode and the flexible circuit to create a plasma from the gas. A mean ion energy of the ions in the ion beam ranges from about 500 electron volts to about 1,500 electron volts.

Abstract: A plasma processing apparatus includes: a placement table serving as a lower electrode and configured to place thereon a workpiece to be subjected to a plasma processing; a DC power supply configured to alternately generate a positive DC voltage and a negative DC voltage to be applied to the placement table; and a controller configured to control an overall operation of the plasma processing apparatus. The controller is configured to: measure a voltage of the workpiece placed on the placement table; calculate, based on the measured voltage of the workpiece, a potential difference between the placement table and the workpiece in a period during which the negative DC voltage is applied to the placement table; and control the DC power supply such that a value of the negative DC voltage applied to the placement table is shifted by a shift amount that decreases the calculated potential difference.

Abstract: A linear compressor includes a cylinder that defines a compression space of a refrigerant and has a cylindrical shape, and a piston disposed in the cylinder and reciprocating along an axis of the cylinder. The cylinder includes a gas inlet on an outer circumferential surface and a supply port radially passing through the cylinder and communicating with the gas inlet. The gas inlet includes a first gas inlet and a second gas inlet disposed behind the first gas inlet, and the supply port includes a first supply port communicating with the first gas inlet and a second supply port disposed behind the first supply port and communicating with the second gas inlet. A flow rate passing through the first supply port is different from a flow rate passing through the second supply port.

Abstract: A method of milling a sample that includes a first layer formed over a second layer, where the first and second layers are different materials, the method comprising: milling the region of the sample by scanning a focused ion beam over the region a plurality of iterations in which, for each iteration, the focused ion beam removes material from the sample generating byproducts from the milled region; detecting, during the milling, the partial pressures of one or more byproducts with a residual gas analyzer positioned to have a direct line of sight to the milled region; generating, in real-time, an output detection signal from the residual gas analyzer indicative of an amount of the one or more byproducts detected; and stopping the milling based on the output signal.

Abstract: One or more aspects of the disclosure pertain to an article including an optical film structure disposed on an inorganic oxide substrate, which may include a strengthened or non-strengthened substrate that may be amorphous or crystalline, such that the article exhibits scratch resistance and retains the same or improved optical properties as the inorganic oxide substrate, without the optical film structure disposed thereon. In one or more embodiments, the article exhibits an average transmittance of 85% or more, over the visible spectrum (e.g., 380 nm-780 nm). Embodiments of the optical film structure include aluminum-containing oxides, aluminum-containing oxy-nitrides, aluminum-containing nitrides (e.g., AlN) and combinations thereof. The optical film structures disclosed herein also include a transparent dielectric including oxides such as silicon oxide, germanium oxide, aluminum oxide and a combination thereof. Methods of forming such articles are also provided.

Abstract: Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.

Abstract: A substrate processing apparatus includes a processing chamber; a susceptor provided in the processing chamber, wherein the susceptor is configured to support a substrate; a first plasma generator disposed on one side of the processing chamber; and a second plasma generator disposed on another side of the processing chamber, wherein the second plasma generator is configured to generate plasma by simultaneously supplying a sinusoidal wave signal and a non-sinusoidal wave signal to the susceptor. By using a substrate processing apparatus, a signal source device, and a method of processing a material layer according to the inventive concept, a smooth etched surface may be obtained for a crystalline material layer without a risk of device damage by RDC.

Abstract: A bipolar junction transistor (LBJT) device that includes a base region of a first III-V semiconductor material having A first band gap; and emitter and collector regions present on opposing sides of the base region, wherein the emitter and collector regions are comprised of a second III-V semiconductor material having a wider band gap than the first III-V semiconductor material. A dielectric region is present underlying the base region, emitter region and the collect region. The dielectric region has an inverted apex geometry. The sidewalls of dielectric region that extend to the apex of the inverted apex geometry are present on facets of a supporting substrate III-V semiconductor material having a {110} crystalline orientation.

Abstract: A bipolar junction transistor (LBJT) device that includes a base region of a first III-V semiconductor material having A first band gap; and emitter and collector regions present on opposing sides of the base region, wherein the emitter and collector regions are comprised of a second III-V semiconductor material having a wider band gap than the first III-V semiconductor material. A dielectric region is present underlying the base region, emitter region and the collect region. The dielectric region has an inverted apex geometry. The sidewalls of dielectric region that extend to the apex of the inverted apex geometry are present on facets of a supporting substrate III-V semiconductor material having a {110} crystalline orientation.

Abstract: Methods and systems for organic vapor jet deposition are provided, where an exhaust is disposed between adjacent nozzles. The exhaust may reduce pressure buildup in the nozzles and between the nozzles and the substrate, leading to improved deposition profiles, resolution, and improved nozzle-to-nozzle uniformity. The exhaust may be in fluid communication with an ambient vacuum, or may be directly connected to a vacuum source.

Abstract: Methods of cleaning a PVD chamber component, for example, process kit components are disclosed. The method comprises at least one of directing a jet of pressurized fluid at a surface of the PVD chamber component, directing pressurized carbon dioxide at the surface of the PVD chamber component, placing the PVD chamber component in a liquid and producing ultrasonic waves in the liquid to further remove contaminants from the surface of the PVD chamber component, using a plasma to clean the surface of the PVD chamber component, subjecting the PVD chamber component to a thermal cycle by heating up to a peak temperature of at least 50° C.

Abstract: A plasma etching method using a Faraday cage which is capable of inhibiting the formation of a needle-like structure and forming a pattern portion having a depth gradient on an etching base.

Abstract: A method of cleaning an extreme ultraviolet lithography collector includes applying a cleaning composition to a surface of the extreme ultraviolet lithography collector having debris on the surface of the collector in an extreme ultraviolet radiation source chamber. The cleaning composition includes: a major solvent having Hansen solubility parameters of 25>?d>15, 25>?p>10, and 30>?h>6; and an acid having an acid dissociation constant, pKa, of ?15<pKa<4. The debris is removed from the surface of the collector and the cleaning composition is removed from the extreme ultraviolet radiation source chamber.

Abstract: A treatment device for treating a lens included in an operational device, is disclosed. The Device may include a first segmented electrode, comprising at least two segments electrically isolated from one another, located in proximity to a first surface of the lens, wherein the first surface is to be treated by the treatment device; at least one second electrode; a distributor electrically associated with the first segmented electrode and with the at least one second electrode, and configured to distribute RF energy from a single RF generator to each of the segments of the segmented electrode separately; an RF generator for separately providing RF energy to the segments of the at least one first electrode and the at least one second electrode in an amount sufficient to generate plasma on at least a portion of the first surface of the lens, and a controller functionally associated with the distributor.

Abstract: A component carrier with a stack including at least one electrically insulating layer structure and at least one electrically insulating structure has a tapering blind hole formed in the stack and an electrically conductive plating layer extending along at least part of a horizontal surface of the stack outside of the blind hole and along at least part of a surface of the blind hole. A minimum thickness of the plating layer at a bottom of the blind hole is at least 8 ?m.

Abstract: A method for the large-scale production of PCBs including a continuous selective adhesion process for creating printed circuit traces providing input to a production line. A roll of printed circuit traces is produced using rolls of flexible substrate, conductive layer, and conductive layer support by applying adhesive between the rolls of flexible substrate and conductive layer, bringing the rolls together, transferring a circuit pattern onto the flexible substrate, curing the adhesive through non-opaque areas of the circuit pattern, and separating the non-bonded areas. The resulting printed circuit traces are applied from the roll to mounts, and circuit components are applied from a roll to the traces as the mounts move along the line. Additional rolls of printed circuit traces and circuit components may be incorporated, and multi-layer PCBs may be produced. As part of the production line, the finished PCBs may be applied to flat or contoured products.

Abstract: An etching apparatus includes a chamber capable of being evacuated, a first electrode provided in the chamber and including a tray support portion configured to support a tray which can hold a plurality of substrates and load/unload the substrates into/from the chamber, and a voltage applying unit configured to apply a voltage to the first electrode. A dielectric plate is attached to a portion, of an obverse surface of the first electrode, which faces an outer edge portion of a non-target surface of the substrate.

Abstract: An etching method capable of controlling the etching rate of a silicon nitride layer and the etching rate of a silicon oxide layer to be approximately equal to each other. A body to be treated including a laminated film (5) having silicon oxide layers (2) and silicon nitride layers (3) laminated on top of each other is treated with an etching gas containing a halocarbon compound containing carbon, bromine, and fluorine. Then, the silicon oxide layer (2) and the silicon nitride layer (3) are etched at approximately equal etching rates.

Abstract: A shower plate for a plasma deposition apparatus, the shower plate including: a plurality of apertures each extending from a rear surface of the shower plate to a front surface for passing a carrier gas therethrough in this direction to a chamber, a plurality of first apertures each extending from a first connecting aperture to an inner part of the front surface for passing gas therethrough in this direction to the chamber, and a plurality of second apertures each extending from a second connecting aperture to an outer part of the front surface for passing gas therethrough in this direction to the chamber, wherein the first connecting aperture connects the first apertures to at least one first aperture extending from a sidewall side of the shower plate and the second connecting aperture connects the second apertures to at least one second aperture extending from the sidewall side.

Abstract: A method for producing an implant blank (100), in particular a dental implant blank from a starting body, said implant blank (100) comprising at least one first area, which is a surface area (102), and a second area, which is a core area (101), wherein the surface area (102) has at least one bioactive surface material (502) and extends from at least one first surface (103) in the direction of the core area (101), and the core area (101) has at least one carrier material that can be subjected to mechanical load. The starting body has a porosity for controlling a targeted distribution of the bioactive surface material (502) within the starting body and is loaded with a solution (500) of the bioactive surface material (502) in a first step, which is a loading step.

Abstract: A method of manufacturing an organic light-emitting display apparatus including forming a lift-off layer on a substrate including a first electrode, the lift-off layer including a fluoropolymer; sequentially forming a barrier layer and a photoresist on the lift-off layer, the barrier layer including an inorganic material; patterning the photoresist and the barrier layer to remove a first portion of the photoresist corresponding to the first electrode such that a second portion other than the first portion remains; etching a portion of the lift-off layer corresponding to the first portion to expose the first electrode; forming an organic functional layer and an auxiliary electrode over the first electrode and the second portion of the photoresist, the organic functional layer including an emission layer; and removing the lift-off layer, the barrier layer, the photoresist, the organic functional layer, and the auxiliary electrode remaining on the second portion.

Abstract: A printed circuit board includes an insulating material with a bump pad buried in one surface, an adhesive layer stacked on the one surface of the insulating material, an insulating layer stacked on the adhesive layer, and a cavity passing through both of the adhesive layer and the insulating layer to expose the bump pad, wherein the cavity has a cross-sectional area decreasing in a direction toward the insulating material.

Abstract: Techniques for improving reliability in Cu interconnects using Cu intermetallics are provided. In one aspect, a method of forming a Cu interconnect in a dielectric over a Cu line includes the steps of: forming at least one via in the dielectric over the Cu line; depositing a metal layer onto the dielectric and lining the via such that the metal layer is in contact with the Cu line at the bottom of the via, wherein the metal layer comprises at least one metal that can react with Cu to form a Cu intermetallic; annealing the metal layer and the Cu line under conditions sufficient to form a Cu intermetallic barrier at the bottom of the via; and plating Cu into the via to form the Cu interconnect, wherein the Cu interconnect is separated from the Cu line by the Cu intermetallic barrier. A device structure is also provided.

Abstract: A magnetically enhanced HDP-CVD plasma source includes a hollow cathode target and an anode. The anode and cathode form a gap. A cathode target magnet assembly forms magnetic field lines that are substantially perpendicular to a cathode target surface. The gap magnet assembly forms a cusp magnetic field in the gap that is coupled with the cathode target magnetic field. The magnetic field lines cross a pole piece electrode positioned in the gap. This pole piece is isolated from ground and can be connected with a voltage power supply. The pole piece can have a negative, positive, or floating electric potential. The plasma source can be configured to generate volume discharge. The gap size prohibits generation of plasma discharge in the gap. By controlling the duration, value and a sign of the electric potential on the pole piece, the plasma ionization can be controlled. The magnetically enhanced HDP-CVD source can also be used for chemically enhanced ionized physical vapor deposition (CE-IPVD).

Abstract: A process is provided in which a patterned layer, an intervening layer and a first layer to be etched according to the pattern of the patterned layer are formed. The intervening layer may be a thermal decomposition layer that may be removed by a heat based removal process. After etching the first layer, the use of a heat based removal process may allow the intervening layer to be removed from the substrate without altering the first layer. In one embodiment, the first layer may be a memorization layer and the process may be a multiple patterning process.

Abstract: A magnetically enhanced low temperature high density plasma chemical vapor deposition (LT-HDP-CVD) source has a hollow cathode target and an anode, which form a gap. A cathode target magnet assembly forms magnetic field lines substantially perpendicular to the cathode surface. A gap magnet assembly forms a magnetic field in the gap that is coupled with the cathode target magnetic field. The magnetic field lines cross the pole piece electrode positioned in the gap. The pole piece is isolated from ground and can be connected to a voltage power supply. The pole piece can have negative, positive, floating, or RF electrical potentials. By controlling the duration, value, and sign of the electric potential on the pole piece, plasma ionization can be controlled. Feed gas flows through the gap between the hollow cathode and anode. The cathode can be connected to a pulse power or RF power supply, or cathode can be connected to both power supplies. The cathode target and substrate can be inductively grounded.

Abstract: A fuel cell separator includes a metal substrate having a surface; an ion penetration layer including carbon diffusion-inhibiting ions extending from the surface of the metal substrate into the metal substrate; and a carbon coating layer disposed on the surface of the metal substrate.

Abstract: A method for manufacturing a semiconductor structure includes depositing a wafer in a processing chamber. Plasma is formed in the processing chamber to process the wafer. A plasma concentration over a peripheral region of the wafer is detected. A plasma distribution over the peripheral region of the wafer is adjusted according to the detected plasma concentration.

Abstract: A process for preparing a body having an osseointegrative topography formed on its surface. The process includes the steps of providing a primary body made of a titanium-zirconium alloy containing 13 to 17 wt-% of zirconium, sandblasting the primary body, and etching the sandblasted primary body with an etching solution including hydrochloric acid, sulfuric acid and water at a temperature of above 80° C. to obtain the body, said etching being performed for a duration of 350 seconds at least.

Abstract: A process is provided in which low-k layers are protected from damage by the use of thermal decomposition materials. In one embodiment, the low-k layers may be low-k dielectric layers utilized in BEOL process steps. The thermal decomposition materials may be utilized to replace organic layers that typically require ashing processes to remove. By removing the need for certain ashing steps, the exposure of the low-k dielectric layer to ashing processes may be lessened. In another embodiment, the low-k layers may be protected by plugging openings in the low-k layer with the thermal decomposition material before a subsequent process step that may damage the low-k layer is performed. The thermal decomposition materials may be removed by a thermal anneal process step that does not damage the low-k layers.

Abstract: A wind speed measuring device includes a constant temperature heat generating device that generates heat at a predetermined set temperature. The constant temperature heat generating device includes a power source, a heat generating element, a switching element, a comparator element, a first negative characteristic thermistor element, and a plurality of resistance elements. The heat generating element and the first negative characteristic thermistor element define a wind speed sensor. The switching element repeats turning on and off to make the heat generating element generate heat at a predetermined set temperature. A pulse voltage is applied from the power source to the heat generating element. A wind speed of a wind contacted with the wind speed sensor is calculated based on a wave form of the applied pulse voltage.

Abstract: Techniques for improving reliability in Cu interconnects using Cu intermetallics are provided. In one aspect, a method of forming a Cu interconnect in a dielectric over a Cu line includes the steps of: forming at least one via in the dielectric over the Cu line; depositing a metal layer onto the dielectric and lining the via such that the metal layer is in contact with the Cu line at the bottom of the via, wherein the metal layer comprises at least one metal that can react with Cu to form a Cu intermetallic; annealing the metal layer and the Cu line under conditions sufficient to form a Cu intermetallic barrier at the bottom of the via; and plating Cu into the via to form the Cu interconnect, wherein the Cu interconnect is separated from the Cu line by the Cu intermetallic barrier. A device structure is also provided.

Abstract: The disclosure provides a polysilicon etching method, including the following steps: ionizing oxygen and/or ozone and fluorine-based gas to obtain a first etching gas having a plasma state, and etching a polysilicon coated by a photoresist with the first etching gas for a preset time; and ionizing the fluorine-based gas to obtain a second etching gas having a plasma state, and etching the polysilicon by the second etching gas until the polysilicon etching is completed. The disclosure can make the line width of the polysilicon smaller, reach the requirement of the preset line width, and can improve the angle of polysilicon to make the angle of polysilicon smaller and also make the loss of polysilicon line width smaller.

Abstract: Disclosed is an inductively-coupled plasma-generating device including: a first power supply for supplying high frequency power; a second power supply for supplying low frequency power; a single coil-based plasma source including at least two antennas which comprise a first antenna having one end as a grounded end and the other end, wherein the first power supply is connected to the first antenna at a point thereof adjacent to the grounded end to receive the high frequency power; and a second antenna surrounded by the first antenna, wherein the second antenna has one end connected to the first antenna and the other end as a low frequency power receiving end connected to the second power supply; and a gas supply for supplying a gas, wherein the gas is excited into plasma by the single coil-based plasma source.

Abstract: A method of manufacturing a semiconductor device includes forming a mask layer including aluminum or an aluminum compound on a layer to be etched comprising at least one first metal selected from tungsten, tantalum, zirconium, hafnium, molybdenum, niobium, ruthenium, osmium, rhenium, and iridium. The method of manufacturing a semiconductor device further includes patterning the mask layer, and etching the layer to be etched by using the patterned mask layer to form a hole or a groove in the layer to be etched.

Abstract: A vacuum transfer module, to which a load-lock module and a plurality of processing modules for processing substrate in a vacuum atmosphere are connected, has therein a substrate transfer unit for transferring the substrate between the load-lock module and the plurality of processing modules. The vacuum transfer module includes: a housing in which a vacuum atmosphere is generated; and a plurality of adaptor attaching portions to which one of a first adaptor for connecting the load-lock module and a second adaptor for connecting the plurality of processing modules is attached, provided at a sidewall of the housing. The adaptor attaching portions are common for the first adaptor and the second adaptor.

Abstract: A chemical processing system and a method of using the chemical processing system to treat a substrate with a mono-energetic space-charge neutralized neutral beam-activated chemical process is described. The chemical processing system comprises a first plasma chamber for forming a first plasma at a first plasma potential, and a second plasma chamber for forming a second plasma at a second plasma potential greater than the first plasma potential, wherein the second plasma is formed using electron flux from the first plasma. Further, the chemical processing system comprises a substrate holder configured to position a substrate in the second plasma chamber.

Abstract: A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes (1) providing a substrate, (2) depositing a first electrode layer over the substrate, (3) depositing a magnetic tunneling junction (MTJ) layer on the first electrode layer, (4) depositing a second electrode layer on the MTJ layer, (5) patterning the first electrode layer, the MTJ layer and the second electrode layer to form a first electrode, an MTJ and a second electrode, (6) forming a first dielectric layer over the first electrode, the MTJ, and the second electrode, (7) removing a portion of the first dielectric layer, (8) forming a second dielectric layer over the first electrode, the MTJ, the second electrode, and an unremoved portion of the first dielectric layer. A semiconductor structure is also disclosed.

Abstract: A method for manufacturing conductive lines is provided. A first metal layer is formed over a carrier substrate. A second metal layer is formed over the first metal layer. A plurality of first conductive lines is formed on the second metal layer. A protective layer is formed on opposite sidewalls of the first conductive lines. An exposed portion of the second metal layer is removed to expose a portion of the first metal layer. The exposed portion of the first metal layer is removed, and the protective layer is removed.

Abstract: A bipolar junction transistor (LBJT) device that includes a base region of a first III-V semiconductor material having A first band gap; and emitter and collector regions present on opposing sides of the base region, wherein the emitter and collector regions are comprised of a second III-V semiconductor material having a wider band gap than the first III-V semiconductor material. A dielectric region is present underlying the base region, emitter region and the collect region. The dielectric region has an inverted apex geometry. The sidewalls of dielectric region that extend to the apex of the inverted apex geometry are present on facets of a supporting substrate III-V semiconductor material having a {110} crystalline orientation.

Abstract: A photodetection device and a method for manufacturing the device, the device including a substrate and an array of diodes, the substrate including an absorption layer including a first type of doping, and each diode including, in the absorption layer, a collection region including a second type of doping opposite to the first type. The device further includes, under the surface of the substrate, a conductive mesh including at least one conductive channel inserted between the collection regions of two adjacent diodes, the at least one conductive channel including the first type of doping and a higher doping density than the absorption layer. The doping density of the at least one conductive channel is the result of a diffusion of metal in the absorption layer from a metal mesh provided on the surface of the substrate.

Abstract: A plasma processing apparatus for reactive ion etching a wafer includes a wafer chuck within a chamber and an electrode for creating a plasma within the chamber above the wafer chuck. There is provided on the wafer chuck a semiconductor wafer having a p? layer and an n+ layer. Both p? and n+ layers have exposed peripheral edges. Also provided is an anode comprising the plasma, a cathode comprising the wafer chuck, and a gate comprising the peripheral edge of the n+ layer. A coating layer is formed on a portion of the peripheral edge of the n+ layer. The coating layer reduces charge flow to a portion of the semiconductor wafer below the coating layer.

Abstract: Embodiments for processing a substrate in a pulsed plasma chamber are provided. A processing apparatus with two chambers, separated by a plate fluidly connecting the chambers, includes a continuous wave (CW) controller, a pulse controller, and a system controller. The CW controller sets the voltage and the frequency for a first radio frequency (RF) power source coupled to a top electrode. The pulse controller is operable to set voltage, frequency, ON-period duration, and OFF-period duration for a pulsed RF signal generated by a second RF power source coupled to the bottom electrode. The system controller is operable to set parameters to regulate the flow of species between the chambers to assist in the negative-ion etching, to neutralize excessive positive charge on the wafer surface during afterglow in the OFF period, and to assist in the re-striking of the bottom plasma during the ON period.

Abstract: A plasma processing tool for fabricating a semiconductor device on a semiconductor wafer includes an optical window disposed on a plasma chamber, remotely from a plasma region. The window is thermally connected to an electrical heater element capable of maintaining the window at a temperature of at least 30° C. A heater controller provides electrical power to the heater element. During operation of the plasma processing tool, the heater controller provides power to the heater element so as to maintain the window at a temperature of at least 30° C. during at least a portion of a plasma process step in which by-products are produced in the plasma chamber.

Abstract: A method of manufacturing a semiconductor device includes depositing a first passivation layer over a substrate, depositing a conductive material over the first passivation layer, patterning the conductive material to form a redistribution layer (RDL) structure, and depositing a second passivation layer configured to change a shape of a top portion of the RDL structure.

Abstract: A method for manufacturing an opening structure is provided. The method may include: forming a patterned mask over a first side of a carrier; forming material over the first side of the carrier covering at least a portion of the carrier; forming a first opening in the carrier from a second side of the carrier opposite the first side of the carrier to at least partially expose a surface of the patterned mask; and forming a second opening in the material from the second side of the carrier using the patterned mask as a mask.

Abstract: A method of forming a semiconductor device includes forming a tungsten layer over a semiconductor substrate in a first chamber, transferring the substrate over which the tungsten layer is formed from the first chamber to a second chamber without exposing into an atmosphere including oxygen, and forming a silicon nitride layer on the tungsten layer in the second chamber.

Abstract: A method of manufacturing an organic light-emitting display apparatus including forming a lift-off layer on a substrate including a first electrode, the lift-off layer including a fluoropolymer; sequentially forming a barrier layer and a photoresist on the lift-off layer, the barrier layer including an inorganic material; patterning the photoresist and the barrier layer to remove a first portion of the photoresist corresponding to the first electrode such that a second portion other than the first portion remains; etching a portion of the lift-off layer corresponding to the first portion to expose the first electrode; forming an organic functional layer and an auxiliary electrode over the first electrode and the second portion of the photoresist, the organic functional layer including an emission layer; and removing the lift-off layer, the barrier layer, the photoresist, the organic functional layer, and the auxiliary electrode remaining on the second portion.

Abstract: An object of the present invention is to improve the operating characteristics of a semiconductor device. A semiconductor device has a contact plug that is formed over a semiconductor substrate, a metal wiring that is coupled to the upper surface of the contact plug, and a slit that is formed in the metal wiring. Further, the contact plug is formed at an end of the metal wiring, and the slit is formed at a position apart from the contact plug in an X direction in a planar view. A distance between an edge of the upper surface at the end of the metal wiring and the upper surface of the slit in the X direction is equal to or larger than and twice or smaller than a first plug diameter of the upper surface of the contact plug in the X direction.