Nonelectrolytic Coating By Vacuum Or Vapor Deposition Patents (Class 205/186)
  • Patent number: 11453823
    Abstract: The disclosure relates to a method for manufacturing a transfer film including an electrode layer, the method comprising: an electrode layer formation step of forming an electrode layer on a carrier member by using a conductive material; a placement step of placing the carrier member on at least one side of an insulating resin layer respectively; a bonding step of bonding the carrier member and the insulating resin layer together by applying pressure thereto; and a transfer step of removing the carrier member to transfer the electrode layer on the insulating resin layer.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: September 27, 2022
    Assignee: InkTee Co., Ltd.
    Inventors: Kwang-Choon Chung, Byung Woong Moon, Su Han Kim, Jae Rin Kim
  • Patent number: 11417498
    Abstract: The invention relates to a method of manufacturing a charged particle detector, comprising the steps of providing a sensor device, such as an Active Pixel Sensor (APS). Said sensor device at least comprises a substrate layer and a sensitive layer. The method further comprises the step of providing a mechanical supporting layer and connecting said mechanical supporting layer to said sensor device. After connection, the sensitive layer is situated in between said substrate layer and said mechanical supporting layer. By connecting the mechanical supporting layer, it is possible to thin said substrate layer for forming said charged particle detector. The mechanical supporting layer forms part of the manufactured detector. The detector can be used in a charged particle microscope, such as a Transmission Electron Microscope for direct electron detection.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: August 16, 2022
    Assignee: FEI Company
    Inventors: Bart Jozef Janssen, Pleun Dona
  • Patent number: 10515913
    Abstract: A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and forms a first portion of an interconnect structure. A second conductive material having a second hardness different from the first hardness is disposed within the recess or opening in a second preselected pattern and forms a second portion of the interconnect structure.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: December 24, 2019
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Rajesh Katkar, Cyprian Emeka Uzoh
  • Publication number: 20150010772
    Abstract: This disclosure relates metalized fluoroelastomer materials such as films. The fluoroelastomer materials bear a conductive metal layer bound to the fluoroelastomer material through a thin layer of titanium.
    Type: Application
    Filed: December 26, 2012
    Publication date: January 8, 2015
    Applicant: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Gene B. Nesmith, Steven Y. Yu
  • Publication number: 20140311966
    Abstract: The invention provides a method for producing a modified surface (5) comprising: patterning a surface (7) by forming thereon a porous molecular network (9) defined by non-covalent interactions between constituent molecules; and depositing in said porous network (9) and on said patterned surface (11) molecules (13) so as to form a self-assembled monolayer (15), wherein both said patterning and said depositing are effected by contact with liquids.
    Type: Application
    Filed: June 27, 2014
    Publication date: October 23, 2014
    Inventors: Manfred Buck, Rafael Madueno, Christophe Silien, Minna Tuulia Räisänen
  • Patent number: 8721864
    Abstract: A metal covered polyimide composite comprising a tie-coat layer and a metal seed layer formed on a surface of a polyimide film by electroless plating or a drying method is provided. A copper layer or a copper alloy layer is formed thereon by electroplating. The copper plated layer or copper alloy plated layer includes three layers to one layer of the copper layer or copper alloy layer. The metal covered polyimide composite effectively prevents peeling in a non-adhesive flexible laminate (especially a two-layer flexible laminate), and more particularly, effectively inhibits peeling from the interface of a copper layer and tin plating. A method of producing the composite and apparatus for producing the composite are also provided.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: May 13, 2014
    Assignee: JX Nippon Mining & Metals Corporation
    Inventors: Michiya Kohiki, Naonori Michishita, Nobuhito Makino
  • Publication number: 20140048420
    Abstract: A method for fabricating one-dimensional metallic nanostructures comprises steps: sputtering a conductive film on a flexible substrate to form a conductive substrate; placing the conductive substrate in an electrolytic solution, and undertaking electrochemical deposition to form one-dimensional metallic nanostructures corresponding to the conductive film on the conductive substrate. The method fabricates high-surface-area one-dimensional metallic nanostructures on a flexible substrate, exempted from the high price of the photolithographic method, the complicated process of the hard template method, the varied characteristic and non-uniform coating of the seed-mediated growth method.
    Type: Application
    Filed: October 25, 2012
    Publication date: February 20, 2014
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Yu-Liang CHEN, Nai-Ying CHIEN, Hsin-Tien CHIU, Chi-Young LEE
  • Publication number: 20140011047
    Abstract: A two-layered copper-clad laminate material, in which one surface or both surfaces of a polyimide film having a thickness of 12.5 to 50 ?m is subjected to a modification treatment by means of a glow discharge plasma treatment in an oxygen gas atmosphere, and a copper layer having a thickness of 1 to 5 ?m is formed by means of sputtering or electroplating on one surface or both surfaces of the polyimide film after the modification treatment; characterized in that the integrated intensity ratio of a C1S peak at 287 to 290 eV to a C1S peak at 283 to 287 eV, obtained by analyzing the photoelectron spectroscopy (XPS) spectra of the surface of the polyimide film after the plasma treatment, is within the range of 0.03 to 0.11.
    Type: Application
    Filed: January 25, 2012
    Publication date: January 9, 2014
    Applicant: JX NIPPON MINING & METALS CORPORATION
    Inventors: Hajime Inazumi, Kazuhiko Sakaguchi, Shinichi Sasaki
  • Patent number: 8568899
    Abstract: Provided is a metal covered polyimide composite comprising a tie-coat layer and a metal seed layer formed on a surface of a polyimide film by electroless plating or a drying method, and a copper layer or a copper alloy layer formed thereon by electroplating, wherein the copper plated layer or copper alloy plated layer comprises three layers to one layer of the copper layer or copper alloy layer, and there is a concentrated portion of impurities at the boundary of the copper layer or copper alloy layer when the copper layer or copper alloy layer is three layers to two layers, and there is no concentrated portion of impurities when the copper layer or copper alloy layer is a single layer. Additionally provided are a method of producing the composite and a method of producing an electronic circuit board.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: October 29, 2013
    Assignee: JX Nippon Mining & Metals Corporation
    Inventors: Michiya Kohiki, Naonori Michishita, Nobuhito Makino
  • Patent number: 8470450
    Abstract: Provided is a method of producing a two-layered copper-clad laminate with improved folding endurance, wherein the two-layered copper-clad laminate retains folding endurance of 150 times or more measured with a folding endurance test based on JIS C6471 by subjecting the laminate in which a copper layer is formed on a polyimide film through sputtering and plate processing to heat treatment at a temperature of 100° C. or more but not exceeding 175° C. Specifically, provided are a method of producing a two-layered copper-clad laminate (two-layered CCL material) in which a copper layer is formed on a polyimide film through sputtering and plate processing, wherein the rupture of the outer lead part of a circuit can be prevented due to the improvement in folding endurance; and a two-layered copper-clad laminate obtained from the foregoing method.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: June 25, 2013
    Assignee: JX Nippon Mining & Metals Corporation
    Inventor: Mikio Hanafusa
  • Publication number: 20130146468
    Abstract: Methods for depositing ruthenium-containing films are disclosed herein. In some embodiments, a method of depositing a ruthenium-containing film on a substrate may include depositing a ruthenium-containing film on a substrate using a ruthenium-containing precursor, the deposited ruthenium-containing film having carbon incorporated therein; and exposing the deposited ruthenium-containing layer to a hydrogen-containing gas to remove at least some of the carbon from the deposited ruthenium-containing film. In some embodiments, the hydrogen-containing gas exposed ruthenium-containing film may be subsequently exposed to an oxygen-containing gas to at least one of remove at least some carbon from or add oxygen to the ruthenium-containing film. In some embodiments, the deposition and exposure to the hydrogen-containing gas and optionally, the oxygen-containing gas may be repeated to deposit the ruthenium-containing film to a desired thickness.
    Type: Application
    Filed: December 8, 2011
    Publication date: June 13, 2013
    Applicant: APPLIED MATERIALS, INC.
    Inventors: HOON KIM, SANG HYEOB LEE, WEI TI LEE, SESHADRI GANGULI, HYOUNG-CHAN HA, SANG HO YU
  • Patent number: 8419918
    Abstract: A method of surface modifying a polyimide film, a method of manufacturing a flexible copper clad laminate using the same, and a flexible copper clad laminate (FCCL) having a two-layer structure manufactured thereby. The method of surface modifying a polyimide film is conducted by modifying the surface of a polyimide film through a first plasma treatment, dipping the polyimide film into a solution containing an ethyleneimine-based silane coupling agent prepared by mixing the compound of Formula 1 and the compound of Formula 2 at a molar ratio of with 0.25˜1, and then modifying the surface of the polyimide film through a second plasma treatment. The method of surface modifying a polyimide film is advantageous because it may be substituted for a conventional surface treatment processes using ion beams.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: April 16, 2013
    Assignee: Korea Research Institute of Chemical Technology
    Inventors: Young-Taik Hong, Hyung Dae Kang, Seog Je Kim, Jae Heung Lee
  • Publication number: 20120177945
    Abstract: The present invention relates to a whisker-free coating structure and a method for fabricating the same. The whisker-free coating structure comprises a substrate, a tungsten doped copper layer and a lead-free tin layer, wherein the tungsten doped copper layer and the lead-free tin layer are formed on the substrate in turns; So that, the whisker growth in the lead-free tin layers can be effectively suppressed by this whisker-free coating structure.
    Type: Application
    Filed: March 9, 2012
    Publication date: July 12, 2012
    Applicant: National Taiwan University of Science and Technology
    Inventors: Yee-Wen Yen, Jinn P. Chu, Chon-Hsin Lin, Chun-Lei Hsu, Chao-Kang Li
  • Publication number: 20120164328
    Abstract: A substrate is transferred to a processing container, and a film formation raw material containing cobalt amidinate and a reducing agent containing a carbonic acid in a vapor phase are introduced into the processing container, thereby a Co film is formed on the substrate.
    Type: Application
    Filed: August 26, 2010
    Publication date: June 28, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Yasuhiko Kojima, Shuji Azumo
  • Patent number: 8187722
    Abstract: An object of the present invention is to provide a copper foil with carrier sheet which permits releasing of the carrier sheet from the copper foil layer even when hot pressing at a temperature exceeding 300° C. is applied in the production of a printed wiring board. In order to achieve the object, a copper foil with physically releasable carrier sheet having a copper foil layer on the surface of the carrier sheet through a bonding interface layer, characterized in that the bonding interface layer is composed of a metal layer and a carbon layer. It is preferable for the bonding interface layer to be composed of a metal layer of 1 nm to 50 nm thick and a carbon layer of 1 nm to 20 nm thick.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: May 29, 2012
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventors: Seiji Nagatani, Hiroshi Watanabe, Kazufumi Izumida
  • Publication number: 20120129004
    Abstract: A housing includes a magnesium or magnesium alloy substrate, a first metal layer formed on the substrate by physical vapor deposition, and a second metal layer formed on the first metal layer by electroplating. The first metal layer is comprised of one or more metals selected from the group consisting of zinc, iron, copper, and nickel.
    Type: Application
    Filed: April 21, 2011
    Publication date: May 24, 2012
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
    Inventors: HSIN-PEI CHANG, WEN-RONG CHEN, HUANN-WU CHIANG, CHENG-SHI CHEN, MAN-XI ZHANG
  • Publication number: 20120085656
    Abstract: The present invention discloses a color filter by copper and silver film, comprising: a lower copper layer; a lower silver layer formed on the lower copper layer; a medium formed on the lower silver layer; an upper copper layer formed on the medium; and an upper silver layer formed on the upper copper layer.
    Type: Application
    Filed: December 15, 2011
    Publication date: April 12, 2012
    Inventors: Sen-Huang Huang, Chin-Poh Pang, Hsin-Hui Hsu
  • Publication number: 20110297551
    Abstract: A method for fabricating an electronic component according to an Embodiment, includes a seed film forming process and an electro-plating process. In the seed film forming process, a seed film is formed above a substrate. In the electro-plating process, electro-plating is performed by soaking the seed film in a plating solution in a plating bath to which the plating solution being bubbled by a nitrogen gas is supplied, using the seed film as a cathode.
    Type: Application
    Filed: March 17, 2011
    Publication date: December 8, 2011
    Inventors: Toshiyuki MORITA, Satoshi Wakatsuki
  • Patent number: 8048280
    Abstract: Several techniques are described for reducing or mitigating the formation of seams and/or voids in electroplating the interior regions of microscopic recessed features. Cathodic polarization is used to mitigate the deleterious effects of introducing a substrate plated with a seed layer into an electroplating solution. Also described are diffusion-controlled electroplating techniques to provide for bottom-up filling of trenches and vias, avoiding thereby sidewalls growing together to create seams/voids. A preliminary plating step is also described that plates a thin film of conductor on the interior surfaces of features leading to adequate electrical conductivity to the feature bottom, facilitating bottom-up filling.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: November 1, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Vijay Bhaskaran, Evan E. Patton, Robert L. Jackson, Jonathan Reid
  • Publication number: 20110174630
    Abstract: A film formation method includes preparing a substrate formed a Co film as a seed layer on a surface of the substrate, applying a negative voltage to the substrate such that a surface potential of Co is lower than an oxidation potential of the Co, and in a state when the negative voltage is applied to the substrate, dipping the Co film in a plating solution mainly containing copper sulfate solution, thereby a Cu film is formed on the Co film of the substrate by electroplating.
    Type: Application
    Filed: August 27, 2010
    Publication date: July 21, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Yasuhiko Kojima, Shuji Azumo
  • Publication number: 20100297461
    Abstract: The present invention discloses a color filter by copper and silver film, comprising: a lower copper layer; a lower silver layer formed on the lower copper layer; a medium formed on the lower silver layer; an upper copper layer formed on the medium; and an upper silver layer formed on the upper copper layer.
    Type: Application
    Filed: May 22, 2009
    Publication date: November 25, 2010
    Inventors: Sen-Huang Huang, Chin-Poh Pang, Hsin-Hui Hsu
  • Publication number: 20090263237
    Abstract: Turbine components with different types of coatings on different parts thereof are described. The coatings are chosen such that they are especially adapted to the thermal and corrosive conditions being present on the parts of the component during use. A method to coat a turbine component is also described.
    Type: Application
    Filed: June 8, 2006
    Publication date: October 22, 2009
    Inventors: Paul Box, Mick Whitehurst
  • Publication number: 20090246554
    Abstract: A metal conductor layer is provided on at least one surface of a heat resistant base. The heat resistant base is peelable from the metal conductor layer. The heat resistant base is preferably a metal foil or a non-thermoplastic polyimide resin film. The metal conductor layer preferably includes a vapor deposition metal layer and/or a plating metal layer. The metal conductor layer preferably includes a metal layer (I) formed in an interface with the heat resistant base by vapor deposition, and at least one metal layer (II) formed on the metal layer (I) by vapor deposition or electroplating. At least one insulative film layer of a non-thermoplastic polyimide resin may be provided on the metal conductor layer.
    Type: Application
    Filed: May 9, 2008
    Publication date: October 1, 2009
    Inventors: Mikio Furukawa, Seiji Sejima, Yoshiaki Echigo
  • Publication number: 20090053426
    Abstract: Embodiments of the invention provide processes for depositing a cobalt layer on a barrier layer and subsequently depositing a conductive material, such as copper or a copper alloy, thereon. In one embodiment, a method for depositing materials on a substrate surface is provided which includes forming a barrier layer on a substrate, exposing the substrate to dicobalt hexacarbonyl butylacetylene (CCTBA) and hydrogen to form a cobalt layer on the barrier layer during a vapor deposition process (e.g., CVD or ALD), and depositing a conductive material over the cobalt layer. In some examples, the barrier layer and/or the cobalt layer may be exposed to a gas or a reagent during a treatment process, such as a thermal process, an in situ plasma process, or a remote plasma process.
    Type: Application
    Filed: August 29, 2008
    Publication date: February 26, 2009
    Inventors: JIANG LU, Hyoung-Chan Ha, Paul Ma, Seshadri Ganguli, Joseph F. Aubuchon, Sang Ho Yu, Murali K. Narasimhan
  • Publication number: 20080237053
    Abstract: An interconnection structure comprising a substrate having a dielectric layer with a via opening therein; wherein the opening has an underlayer of cobalt and/or nickel therein, barrier layer of an alloy of cobalt and/or nickel; and tungsten is provided.
    Type: Application
    Filed: May 27, 2008
    Publication date: October 2, 2008
    Applicant: International Business Machines Corporation
    Inventors: Panayotis Andricacos, Steven H. Boettcher, Sandra G. Malhotra, Milan Paunovic, Craig Ransom
  • Patent number: 7316783
    Abstract: A method of wiring formation includes forming a feeder film partially on a substrate, forming on the substrate a plating base film via a physical film making method so that the plate base film partially overlaps the feeder film, forming a plated wiring on the plating base film using an electrolytic plating, and selectively removing at least an area of the feeder film which is exposed from the plated wiring, using a wet etching process.
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: January 8, 2008
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoshiyuki Tonami, Yoshihiro Koshido
  • Patent number: 7214305
    Abstract: Disclosed is a method of manufacturing an electronic device, comprising forming a concave portion on the surface of a base member, forming an electrically conductive seed layer on that surface of the base member on which a plated film is to be formed, and applying an electrolytic plating treatment with the seed layer used as a common electrode under the condition that a substance for accelerating the electrolytic plating is allowed to be present in the concave portion of the base member in an amount larger than that on the surface of the base member to form a plated film.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: May 8, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuo Matsuda, Hisashi Kaneko
  • Patent number: 7211333
    Abstract: The present invention is to provide a resin-forming mold having high releasability and permitting a production without increasing production costs. The resin-forming mold can be used to produce a resin-molded product having minute uneven portions on a front face thereof, such as a surface light source device-use light guide for a liquid crystal display, an aspherical micro-lens, micro-Fresnel lens and an optical disk. In the stamper (resin-forming mold) 10 provided with an electroformed layer 11 and a conductive film 12 formed on the electroformed layer 11, the front face layer 12c of the conductive film 12 is formed of aluminum and a back face 12d is formed of nickel as an electroconductive metal. In addition, the constituent composition of the aluminum and the nickel continuously changes from the front face 12c toward the back face 12d. The front face 12c may be formed of aluminum and oxygen. The aluminum may combine with the oxygen to form an oxide of aluminum.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: May 1, 2007
    Assignee: Kuraray Co., Ltd.
    Inventors: Yukihiro Yanagawa, Takumi Yagi, Masaru Karai
  • Patent number: 7150819
    Abstract: A material for magnetic pole for attaining a writing head generating an intense recording magnetic field, and a structure and a manufacturing method therefor. The thin film magnetic head includes a magnetic pole layer having a plated magnetic layer containing Co, Ni and Fe formed on a plated underlayer of a sputtered magnetic layer containing Co, Ni and Fe. The CoNiFe magnetic layer having a composition: 40 wt %?Co?70 wt %, 10 wt %?Ni?25 wt % and 10 wt %?Fe?30 wt % and a peak intensity ratio in the X-ray diffraction of I(200)/I(111)?0.5 and I(110)/I(111)?1 (defining peak intensities for the face-centered cubic fcc (111) face, fcc (200) face and the body-centered cubic bcc (119) face as: I(111), I(200), I(110)).
    Type: Grant
    Filed: March 9, 2004
    Date of Patent: December 19, 2006
    Assignee: Hitachi Global Storage Technologies Japan, Ltd.
    Inventors: Kazue Kudo, Yasuyuki Okada, Nobuo Yoshida, Moriaki Fuyama, Noriyuki Saiki, Gen Oikawa, Takashi Kawabe, Makoto Morijiri
  • Patent number: 6946065
    Abstract: Several techniques are described for reducing or mitigating the formation of seams and/or voids in electroplating the interior regions of microscopic recessed features. Cathodic polarization is used to mitigate the deleterious effects of introducing a substrate plated with a seed layer into an electroplating solution. Also described are diffusion-controlled electroplating techniques to provide for bottom-up filling of trenches and vias, avoiding thereby sidewalls growing together to create seams/voids. A preliminary plating step is also described that plates a thin film of conductor on the interior surfaces of features leading to adequate electrical conductivity to the feature bottom, facilitating bottom-up filling.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: September 20, 2005
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Vijay Bhaskaran, Evan E. Patton, Robert L. Jackson, Jonathan Reid
  • Patent number: 6899796
    Abstract: A two-step method of filling copper into a high-aspect ratio via or dual-damascene structure. The first step sputters at a low temperature of no more than 100° C. and with at least portions of high wafer bias, thereby filling a lower half of the hole. The initial copper sputtering is preferably performed through multiple cycles of low-level and high-level pedestal bias to deposit copper on exposed corners and to sputter resulting overhangs from the corners while depositing deep in the hole. The second step may include either electrochemical plating or sputtering performed at a higher temperature, e.g., at least 200° C. and with lower wafer bias to complete the hole filling. In another aspect of the invention, diffusion promoting gas such as hydrogen is added to the copper sputter plasma.
    Type: Grant
    Filed: May 1, 2003
    Date of Patent: May 31, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Wei D. Wang, Anantha K. Subramani, Jianming Fu, Praburam Gopalraja, Jick M. Yu, Fusen Chen
  • Patent number: 6893550
    Abstract: The present invention relates to a copper electroplating bath composition and method of using it for microelectronic device fabrication. In particular, the present invention relates to copper electroplating in the fabrication of interconnect structures in semiconductor devices. By use of the inventive copper electroplating bath composition, the incidence of voids in the interconnect structures is reduced.
    Type: Grant
    Filed: October 3, 2001
    Date of Patent: May 17, 2005
    Assignee: Intel Corporation
    Inventors: Valery Dubin, Kimin Hong, Nate Baxter
  • Patent number: 6893541
    Abstract: A DC magnetron sputter reactor for sputtering copper, its method of use, and shields and other parts promoting self-ionized plasma (SIP) sputtering, preferably at pressures below 5 milliTorr, preferably below 1 milliTorr. Also, a method of coating copper into a narrow and deep via or trench using SIP for a first copper layer. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. The SIP copper layer can act as a seed and nucleation layer for hole filling with conventional sputtering (PVD) or with electrochemical plating (ECP). For very high aspect-ratio holes, a copper seed layer is deposited by chemical vapor deposition (CVD) over the SIP copper nucleation layer, and PVD or ECP completes the hole filling. The copper seed layer may be deposited by a combination of SIP and high-density plasma sputtering. For very narrow holes, the CVD copper layer may fill the hole.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: May 17, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Tony P. Chiang, Yu D. Cong, Peijun Ding, Jianming Fu, Howard H. Tang, Anish Tolia
  • Patent number: 6872295
    Abstract: The present invention is related to a method for the preparation of a composition for electroplating a copper-containing layer on a substrate. This method makes use of an aqueous solution that has at least: a source of copper Cu(II) ions, an additive to adjust the pH to a predetermined value, and a complexing agent for complexing Cu(II) ions. The complexing agent has the chemical formula: COOR1—COHR2R3 in which R1 is an organic group covalently bound to the carboxylate group (COO), R2 is either hydrogen or an organic group, and R3 is either hydrogen or an organic group. The solution has no reducing agent. The method involves providing electrons from a source not in direct contact with the solution, through transport means that provides the contact between said source and said solution. The present invention is also related to a process for forming a copper-containing layer on a substrate in an electroplating bath prepared according to the foregoing method.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: March 29, 2005
    Assignee: Interuniversitair Microelektronica Centrum (IMEC)
    Inventors: Roger Palmans, Yuri Lantasov
  • Patent number: 6855376
    Abstract: Carbon nanotubes are directly grown on a substrate surface having three metal layers thereon by a thermal chemical vapor deposition at low-temperature, which can be used as an electron emission source for field emission displays. The three layers include a layer of an active metal catalyst sandwiched between a thick metal support layer formed on the substrate and a bonding metal layer. The active metal catalyst is iron, cobalt, nickel or an alloy thereof; the metal support and the bonding metal independently are Au, Ag, Cu, Pd, Pt or an alloy thereof; and they can be formed by sputtering, chemical vapor deposition, physical vapor deposition, screen printing or electroplating.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: February 15, 2005
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Liang Hwang, Jack Ting, Jih-Shun Chiang, Chuan Chuang
  • Patent number: 6811670
    Abstract: A method for forming electroplating cathode contacts around the periphery of a semiconductor wafer including forming an insulating layer over a conductive layer extending at least around the periphery of a semiconductor wafer substrate; etching a plurality of openings around a peripheral portion of the semiconductor wafer substrate through the insulating layer to extend through a thickness of the insulating layer in closed communication with the conductive layer said conductive area in electrical communication with a central portion of the semiconductor wafer substrate; filling the plurality of openings with metal to form electrically conductive pathways; planarizing the electrically conductive pathway surfaces; and, forming a metal layer over the electrically conductive pathway surfaces to form a plurality of contact pads for contacting a cathode for carrying out an electroplating process.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: November 2, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 6808641
    Abstract: A method of wiring formation includes forming a feeder film partially on a substrate, forming on the substrate a plating base film via a physical film making method so that the plate base film partially overlaps the feeder film, forming a plated wiring on the plating base film using an electrolytic plating, and selectively removing at least an area of the feeder film which is exposed from the plated wiring, using a wet etching process.
    Type: Grant
    Filed: January 17, 2001
    Date of Patent: October 26, 2004
    Assignee: Murata Manufacturing Co., Ltd
    Inventors: Yoshiyuki Tonami, Yoshihiro Koshido
  • Patent number: 6793796
    Abstract: Electroplating methods using an electroplating bath containing metal ions and a suppressor additive, an accelerator additive, and a leveler additive, together with controlling the current density applied to a substrate, avoid defects in plated films on substrates having features with a range of aspect ratios, while providing good filling and thickness distribution. The methods include, in succession, applying DC cathodic current densities optimized to form a conformal thin film on a seed layer, to provide bottom-up filling, preferentially on features having the largest aspect ratios, and to provide conformal plating of all features and adjacent field regions. Including a leveling agent in the electroplating bath produces films with better quality after subsequent processing.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: September 21, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, David Smith, Steven T. Mayer, Jon Henri, Sesha Varadarajan
  • Patent number: 6773572
    Abstract: A method of metal layer formation which can satisfactorily eliminate the problems caused by plating solution infiltration and is sufficiently effective in reducing the permittivity of an insulating layer; and a metal foil-based layered product obtainable by the method. The method is for forming a metal layer on a surface of a porous resin layer and includes: a step in which a porous resin layer having a dense layer as a surface part thereof is used as the porous resin layer and a thin metal film is formed on the surface of the dense layer by a dry process; and a step in which a metal film is formed on the surface of the thin metal film by plating.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: August 10, 2004
    Assignee: Nitto Denko Corporation
    Inventors: Toshiyuki Kawashima, Nobuharu Tahara, Kenichi Ikeda
  • Patent number: 6767589
    Abstract: A composite flywheel rotor includes an annular rim mounted on a hub for high speed rotation in an evacuated flywheel enclosure. A smooth epoxy layer is applied to the rim and is cleaned or maintained clean in preparation for a metal coating on the rim. The rim may be baked in a vacuum furnace to drive off the volitiles and water vapor, and a thin metal coating is applied over the entire rim to retard outgassing from the resin in the flywheel composite rim. The metal coating on flywheel rim is preferably aluminum because aluminum adheres well to epoxy and is economical. The metal coating is deposited on the flywheel rim by physical vapor deposition and may be built up after an initial PVD coating by electroplating. A tough protective polymer is applied over the metal coating to protect metal coating from mechanical damage during handling.
    Type: Grant
    Filed: October 12, 2000
    Date of Patent: July 27, 2004
    Assignee: Toray Composites (America), Inc.
    Inventor: Christopher W. Gabrys
  • Publication number: 20040031693
    Abstract: A process for metallization of a workpiece, such as a semiconductor workpiece. In an embodiment, an alkaline electrolytic copper bath is used to electroplate copper onto a seed layer, electroplate copper directly onto a barrier layer material, or enhance an ultra-thin copper seed layer which has been deposited on the barrier layer using a deposition process such as PVD. The resulting copper layer provides an excellent conformal copper coating that fills trenches, vias, and other microstructures in the workpiece. When used for seed layer enhancement, the resulting copper seed layer provide an excellent conformal copper coating that allows the microstructures to be filled with a copper layer having good uniformity using electrochemical deposition techniques. Further, copper layers that are electroplated in the disclosed manner exhibit low sheet resistance and are readily annealed at low temperatures.
    Type: Application
    Filed: February 27, 2003
    Publication date: February 19, 2004
    Inventors: Linlin Chen, Gregory J. Wilson, Paul R. McHugh, Robert A. Weaver, Thomas L. Ritzdorf
  • Patent number: 6689413
    Abstract: Ultra smooth as-deposited composite nickel coatings for use in an information storage system are provided. The composite nickel coatings include an electrolessly deposited nickel layer formed on a sputter deposited nickel layer. The composite nickel coatings have an as-deposited surface roughness of less than about 10 Å. Embodiments include formation of the composite nickel coating on a disk, followed by deposition of an underlayer and magnetic layer thereon to form a magnetic recording medium.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: February 10, 2004
    Assignee: Seagate Technology LLC
    Inventors: Connie C. Liu, Linda L. Zhong, Ian J. Beresford, Lin Huang, Joseph Leigh, David E. Brown
  • Patent number: 6613603
    Abstract: A photovoltaic device is provided which comprises a back reflection layer, a zinc oxide layer and a semiconductor layer stacked in this order on a substrate, wherein the zinc oxide layer contains a carbohydrate. The content of the carbohydrate is preferably in the range of from 1 &mgr;g/cm3 to 100 mg/cm3. Thereby, the zinc oxide layer can be formed without abnormal growth to have a rough surface to achieve sufficient optical confinement effect, and the photovoltaic device is improved in the durability and the photoelectric conversion efficiency.
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: September 2, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masafumi Sano
  • Patent number: 6610191
    Abstract: The present invention provides plating solutions, particularly metal plating solutions, designed to provide uniform coatings on substrates and to provide substantially defect free filling of small features, e.g., micron scale features and smaller, formed on substrates with none or low supporting electrolyte, i.e., which include no acid, low acid, no base, or no conducting salts, and/or high metal ion, e.g., copper, concentration. Additionally, the plating solutions may contain small amounts of additives which enhance the plated film quality and performance by serving as brighteners, levelers, surfactants, grain refiners, stress reducers, etc.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: August 26, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Uziel Landau, John J. D'Urso, David B. Rear
  • Publication number: 20030141194
    Abstract: A process for applying a metallization interconnect structure to a semiconductor workpiece having a barrier layer deposited on a surface thereof is set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer having a thickness of less than or equal to about 500 Angstroms. The ultra-thin seed layer is then enhanced by depositing additional metal thereon to provide an enhanced seed layer.
    Type: Application
    Filed: February 3, 2003
    Publication date: July 31, 2003
    Inventor: LinLin Chen
  • Publication number: 20030129104
    Abstract: An arrangement and method orients the magnetization direction of magnetic layers on a plate shaped substrate on a mounting. The mounting defines a positioning plane for the substrate and a magnet arrangement is on one side of the positioning plane. The magnet arrangement has at least three electromagnets whose dipole axes are at least approximately parallel to the positioning plane and, viewed perpendicularly to the positioning plane, define a closed surface.
    Type: Application
    Filed: January 3, 2003
    Publication date: July 10, 2003
    Inventor: Wolfram Maass
  • Patent number: 6562219
    Abstract: A method for the formation of copper wiring films includes the steps of forming a first copper film by a CVD method on a diffusion barrier film, which diffusion barrier film has been formed on a semiconductor substrate and in which a concavity has been established; heating the first copper film to a temperature within the range from 200 to 500° C.; and subsequently forming a second copper film on the first copper film by a plating method using the first copper film as an electrode.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: May 13, 2003
    Assignee: Anelva Corporation
    Inventors: Akiko Kobayashi, Atsushi Sekiguchi, Tomoaki Koide, Minjuan Zhang, Hideki Sunayama, Shiqin Xiao, Kaoru Suzuki
  • Patent number: 6562715
    Abstract: A barrier layer structure and a method of forming the structure. The barrier layer structure comprises a bilayer, with a first layer formed by chemical vapor deposition and a second layer formed by physical vapor deposition. The first barrier layer comprises a metal or a metal nitride and the second barrier layer comprises a metal or a metal nitride. The barrier bilayer is applicable to copper metallization.
    Type: Grant
    Filed: August 9, 2000
    Date of Patent: May 13, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Ling Chen, Christophe Marcadal
  • Publication number: 20030010645
    Abstract: A damascene process for introducing copper into metallization layers in microelectronic structures includes a step of forming an enhancement layer of a metal alloy, such as a copper alloy or Co—W—P, over the barrier layer, using PVD, CVD or electrochemical deposition prior to electrochemically depositing copper metallization. The enhancement layer has a thickness from 10&mgr; to 100&mgr; and conformally covers the discontinuities, seams and grain boundary defects in the barrier layer. The enhancement layer provides a conductive surface onto which a metal layer, such as copper metallization, may be applied with electrochemical deposition. Alternatively, a seed layer may be deposited over the enhancement layer prior to copper metallization.
    Type: Application
    Filed: June 14, 2002
    Publication date: January 16, 2003
    Applicant: Mattson Technology, Inc.
    Inventors: Chiu H. Ting, Igor Ivanov
  • Patent number: 6506293
    Abstract: A process for the application of a metal film on a polymer surface of a subject, to which, after nucleation with a catalytically active platinum metal and/or a platinum metal compound, a coating metal is precipitated autocatalytically from an aqueous solution without any external current supply, before at least another layer is applied, preferably electrolytically under external current supply, to this preliminary coating. To achieve favorable construction features, it is suggested that centers of a Lewis acid or Lewis base are enriched first on the polymer surface to be coated by a vacuum plasma treatment via a plasma gas adapted to the polymer used, before the polymer surface is nucleated under vacuum with the platinum metal and/or the platinum metal compound by another plasma gas containing an evaporated platinum metal and/or a platinum metal compound for nucleophilic and/or electrophilic reaction on the Lewis acids and/or Lewis bases.
    Type: Grant
    Filed: February 8, 2001
    Date of Patent: January 14, 2003
    Assignee: Atotech Deutschland GmbH
    Inventor: Thomas Rumpf