Abstract: Systems and methods to remove or lessen the size of metal particles that have formed on, and to limit the rate at which metal particles form or grow on, workpiece surface influencing devices used during electrodeposition are presented. According to an exemplary method, the workpiece surface influencing device is occasionally placed in contact with a conditioning substrate coated with an inert material, and the bias applied to the electrodeposition system is reversed. According to another exemplary method, the workpiece surface influencing device is conditioned using mechanical contact members, such as brushes, and conditioning of the workpiece surface influencing device occurs, for example, through physical brushing of the workpiece surface influencing device with the brushes. According to a further exemplary method, the workpiece surface influencing device is rotated in different direction during electrodeposition.

Abstract: A process for applying a metallization interconnect structure to a semiconductor workpiece having a barrier layer deposited on a surface thereof is set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer having a thickness of less than or equal to about 500 Angstroms. The ultra-thin seed layer is then enhanced by depositing additional metal thereon to provide an enhanced seed layer. The enhanced seed layer has a thickness at all points on sidewalls of substantially all recessed features distributed within the workpiece that is equal to or greater than about 10% of the nominal seed layer thickness over an exteriorly disposed surface of the workpiece.

Abstract: A material includes a layer with a plurality of self-assembled structures comprising compositions. The structures are localized in separate islands covering a portion of the layer in an integrated assembly. In some embodiments, the compositions include nanoparticles. In particular, some embodiments pertain to a material with a self-assembled formation of inorganic particles with an average diameter less than about 100 nm. The structures can be used as devices within an integrated article. The method for producing the articles comprise a localization process defining boundaries of the devices and a self-assembly process within the identified boundaries.

Abstract: A process for forming an interface (106) between a plated and a non-plated area (102, 104) on the surface of a plastic component (100) is disclosed. First, an anti-plating layer (110) is formed over the surface of the plastic component. Thereafter, a low-power laser beam (10) is used to remove a portion of the anti-plating layer and to form an interface between the plated area and the non-plated area. A seeding layer (120) is formed on the plated area so that the plated area is electrically conductive. Finally, a metallic layer (130) is electrically plated over the seeding layer. The metallic layer connects with the anti-plating layer via the interface. The cost of producing the anti-plating layer is low. Moreover, since the laser etching operation is able to produce a high-quality interface boundary between the plated and the non-plated area, yield of the process is improved.

Abstract: An inexpensive process for depositing an electrically conductive material on selected surfaces of a dielectric substrate may be advantageously employed in the manufacture of printed wiring boards having high quality, high density, fine-line circuitry, thereby allowing miniaturization of electronic components and/or increased interconnect capacity. The process may also be used for providing conductive pathways between opposite sides of a dielectric substrate and in decorative metallization applications.

Abstract: A method of forming an oxide free copper interconnect, comprising the following steps. A substrate is provided and a patterned dielectric layer is formed over the substrate. The patterned dielectric layer having an opening exposing a portion of the substrate. The opening having exposed sidewalls. A copper seed layer is formed over the sidewalls of the opening. The copper seed layer is subjected to an electrochemical technique to eliminate any copper oxide formed over the copper seed layer. A bulk copper layer is electrochemically plated over the copper-oxide-free copper seed layer, filling the opening and forming the oxide-free copper interconnect.

Abstract: A method of preparing high capacity hydrous ruthenium oxide micro-ultracapacitors. A laser direct-write process deposits a film of hydrous ruthenium oxide in sulfuric acid under ambient temperature and atmospheric conditions. A dual laser process combining infrared and ultraviolet light is used for fabricating a complete wet electrochemical cell in a single processing step. Ultraviolet laser micromachining is used to tailor the shape and size of the deposited material into planar electrodes. The micro-ultracapacitors have improved size, weight, and cost efficiency and exhibit high specific power and high specific energy.

Abstract: An active part of a sensor is formed, for example, by micro-machined silicon wafers bearing electronic elements, electrical conductors, connection pads, and pins. The pads are electrically connected to the pin ends by conductive elements. Then the wafer and the pin ends are plunged into an electrolytic bath to make an electrolytic deposit of conductive metal on the pin ends, the pads, and the conductive elements that connect them. Finally, this metal is oxidized or nitrized to form an insulating coat on the pin ends, the pads, and the conductive elements that connect them. Such a sensor may find particular application as a sensor designed to work in harsh environments.

Abstract: An apparatus which can control thickness uniformity during deposition of conductive material from an electrolyte onto a surface of a semiconductor substrate is provided. The apparatus has an anode which can be contacted by the electrolyte during deposition of the conductive material, a cathode assembly including a carrier adapted to carry the substrate for movement during deposition, and a conductive element permitting electrolyte flow therethrough. A mask lies over the conductive element and has openings permitting electrolyte flow. The openings define active regions of the conductive element by which a rate of conductive material deposition onto the surface can be varied. A power source can provide a potential between the anode and the cathode assembly so as to produce the deposition. A deposition process is also disclosed, and uniform electroetching of conductive material on the semiconductor substrate surface can additionally be performed.

Abstract: A method for surface treatment of a metal base includes the steps of: (a) anodizing the base to obtain a first layer of oxidation film on a surface of the base; (b) removing or covering a first area of the oxidation film; and (c) anodizing the base to obtain a second layer of oxidation film. A second area of the oxidation film is thus formed on the base which is different from the first area of the oxidation film. The second area is either higher or lower than the first area, therefore an anaglyphic decorative effect is obtained on the surface of the base.

Abstract: A method for in-situ cleaning an electrodeposition surface following an electroplating process including providing a first electrode assembly and a second electrode assembly; applying a first current density across the first electrode assembly and the second electrode assembly for carrying out the electrodeposition process; carrying out the electrodeposition process to electrodeposit a metal onto an electrodeposition surface of the second electrode assembly; and, applying a second current density having a second polarity reversed with reference to the first polarity across the first electrode assembly and the second electrode assembly the second current density having a relatively lower current density compared to the first current density.

Abstract: An electrochemical processing method is provided for forming a current carrying device for semiconductor chip packaging and similar applications. The method comprises selecting sections of a substrate to carry current wherein a selected section is at least partly covered with a voltage switchable dielectric material, rendering the voltage switchable dielectric material conductive, and electrochemically forming a current carrying material directly on the voltage switchable dielectric material. The voltage switchable dielectric material can have a characteristic voltage, such that when a voltage having a magnitude exceeding the characteristic voltage is applied to the voltage switchable dielectric material, the voltage switchable dielectric material switches from a dielectric material to a conductive material. When conductive, the voltage switchable dielectric material is amenable to electrochemical processing such as electroplating.

Abstract: A method is disclosed for electrolytically forming conductor structures from highly pure copper on surfaces of semiconductor substrates, which surfaces are provided with recesses, when producing integrated circuits. The method includes the steps of coating the surfaces of the semiconductor substrates with a full-surface basic metal layer in order to achieve sufficient conductance for the electrolytic depositions, depositing full-surface deposition of copper layers of uniform layer thickness on the basic metal layer by an electrolytic metal deposition method, and structuring the copper layer.

Abstract: A method of manufacturing a decorative plate (1) includes the steps of: preparing a metal substrate and covering selected areas (11, 16) of the substrate with a protective film; anodizing the substrate; and removing the protective film to expose metallic surfaces in the selected areas of the substrate.

Abstract: A method of plating for filling via holes, in which each via hole is formed in an insulation layer covering a substrate so as to expose, at its bottom, part of a conductor layer located on the substrate. A copper film is formed on the top surface of the insulation layer covering the substrate, and the side walls and bottoms of the respective via holes. A strike plating of copper is provided on the copper film, and the substrate is immersed in an aqueous solution containing a plating promoter to thereby deposit the plating promoter on the surface of the copper strike. The plating promoter is removed from the copper strike plating located on the top surface insulation layer while leaving the plating promoter on the side walls and bottoms of the respective via holes. The substrate is subsequently electroplated with copper to fill the via holes.

Abstract: A method of forming a solid inter-layer conductive rod. A printed circuit board comprising an insulating core layer, a first conductive layer and a second conductive layer is provided. The insulating core layer is sandwiched between the first conductive layer and the second conductive layer. A first opening that exposes a portion of the insulating core layer is formed in the first conductive layer. The exposed insulating core layer is removed by laser drilling to form a second opening that exposes a portion of the second conductive layer. An electroplating process is conducted using the second conductive layer as a negative electrode so that conductive material solidly fills the first opening and the second opening to form a solid conductive rod.

Abstract: The present invention provides a method of plating an electrical contact on an integrated circuit (IC) substrate manufactured from a rigid double-sided or multi-layered printed wiring board core with dielectric layers on both sides of the core. The method may include forming electrically connected plating layers on first and second opposing sides of a substrate and electroplating a contact layer over each of the plating layers using the plating layers. The method further includes removing a portion of the plating layers from the first and second opposing sides while leaving the plating layers under the contact layer.

Abstract: The present invention is directed to a method of etching anode foil in a non-uniform manner which increases the overall capacitance gain of the foil while retaining foil strength. In particular, by using a mask to protect a mesh grid of the foil from further etching, a previously etched foil can be further etched, prior to the widening step. Alternatively, the mask may be used in the initial etch, eliminating the need for the second process. In effect the foil may be etched to a higher degree in select regions, leaving a web of more lightly etched foil defined by the mask to retain strength. According to the present invention, the foil is placed between two masks with a grid of openings which expose the foil in these areas to the etching solution. The exposed area can be as little as 10% of the total foil to as much as 95% of the total foil, preferably 30% to 70% of the total foil area.

Abstract: Disclosed herewithin is an apparatus for fabricating a stent which involves processing a tubular member whereby no connection points to join the edges of a flat pattern are necessary. The process includes the steps of: a) preparing the surface of a tubular member, b) coating the outside surface of the tubular member with a photo-sensitive resist material, c) placing the tubular member in an apparatus designed to simultaneously rotate the tubular member while passing a specially configured photographic frame negative between a light source and the tubular member, d) exposing the tubular member to a photoresist developer, e) rinsing the excess developer and uncured resist from the exposed tubular member, f) sealing the inner lumen of the tubular member, and g) treating the tubular member with a chemical or electro-chemical process to remove uncovered metal. By modifying the photographic negative, this process can be employed to fabricate a virtually unlimited number of stent designs and configurations.

Abstract: The present invention relates to an apparatus having a nanodevice for controlling the flow of charged particles in an electrolyte. Such apparatus comprises an electrolytic bath container divided by a polymeric foil into a first and a second compartment, wherein each compartment comprises an electrode connected to a voltage supply. Further the apparatus comprises at least one asymmetric pore forming a via hole through said foil, wherein said pore provides a narrow opening of a diameter in the range of several nanometers down to about one nanometer on a front side of said foil and a wide opening in the range of several ten nanometers up to several hundred nanometers on a back side of said foil.

Abstract: Metal articles having a durable visible marking on a smooth Type III hard anodized surface particularly useful for shock absorber tubes are produced by applying an alkaline solution to the anodized surface for not less than about 15 seconds at temperature of 100°-140° F.; applying a pattern of lacquer based solvent ink to said surface; and sealing the applied pattern by applying a liquid selected from the group consisting of nickel acetate, cobalt acetate and boiling water to said pattern.

Abstract: A method for improving an electrodeposited metal film uniformity and preventing metal deposition and peeling of deposited metal from an electrode during an electrodeposition and electropolishing process including providing a first anode electrode assembly and a semiconductor wafer plating surface disposed in an electrolyte bath including a plating metal for deposition onto the semiconductor wafer plating surface; providing at least one additional anode electrode assembly including the plating metal disposed peripheral to the first anode electrode assembly for selectively applying the cathodic electrical potential during an electropolishing process; and, periodically alternating between an electrodeposition process and electropolishing process with respect to the semiconductor wafer plating surface such that the plating metal is preferentially plated onto the at least one additional electrode assembly.

Abstract: A method to mark an aluminum object (1) includes the steps of: providing an aluminum substrate (10); anodizing and coloring the aluminum substrate; providing a mask (2) with a pattern (25) in the same shape as a mark (15) to be formed on the aluminum object; irradiating a portion of the anodized surface (12) of the aluminum substrate with an ultraviolet beam through the pattern until the desired mark is formed on the anodized surface. The color of the mark is lighter than the anodized surface of the aluminum object, or gradually changes to the color of the anodized surface of the aluminum object.

Abstract: An electrochemical fabrication process produces three-dimensional structures (e.g. components or devices) from a plurality of layers of deposited materials wherein the formation of at least some portions of some layers are produced by operations that remove material or condition selected surfaces of a deposited material. In some embodiments, removal or conditioning operations are varied between layers or between different portions of a layer such that different surface qualities are obtained. In other embodiments varying surface quality may be obtained without varying removal or conditioning operations but instead by relying on differential interaction between removal or conditioning operations and different materials encountered by these operations.

Abstract: A method for reducing or avoiding semiconductor wafer peripheral defects and contamination during and following electrodeposition including providing a wafer chuck assembly sealably attached to a back side of a semiconductor wafer leaving an exposed peripheral portion of the back side of the semiconductor wafer the backside parallel to a front side of the semiconductor wafer comprising a process surface; contacting at least the semiconductor process surface with a process solution; and, simultaneously directing a pressurized flow of gas onto the exposed peripheral portion such that the pressurized flow of gas covers the exposed peripheral portion including being radially directed outward toward the periphery of the semiconductor wafer.

Abstract: A process for applying a metallization interconnect structure to a semiconductor workpiece having a barrier layer deposited on a surface thereof is set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer having a thickness of less than or equal to about 500 Angstroms. The ultra-thin seed layer is then enhanced by depositing additional metal thereon to provide an enhanced seed layer. The enhanced seed layer has a thickness at all points on sidewalls of substantially all recessed features distributed within the workpiece that is equal to or greater than about 10% of the nominal seed layer thickness over an exteriorly disposed surface of the workpiece.

Abstract: In accordance with one embodiment of the invention, a process for applying a metal to a workpiece is set forth. The workpiece initially includes a seed layer deposited on at least a portion of a surface thereof that is generally unsuitable for bulk electrochemical deposition. The process starts with this workpiece and repairs the seed layer by depositing a metal using a first electrochemical deposition process to provide a repaired seed layer that is suitable for subsequent bulk electrochemical deposition. After the seed layer has been repaired, a bulk metal deposition over the repaired seed layer is executed by electrochemically depositing a bulk amount of a metal onto the repaired seed layer using a second electrochemical deposition process. The processing parameters of the second electrochemical deposition process are different from processing parameters used in the first electrochemical deposition process. A corresponding apparatus is also set forth.

Abstract: A method and apparatus is disclosed for sequential processing of integrated circuits, particularly for conductively passivating a contact pad with a material which resists formation of resistive oxides. In particular, a tank is divided into three compartments, each holding a different solution: a lower compartment and two upper compartments divided by a barrier, which extends across and partway down the tank. The solutions have different densities and therefore separate into different layers. In the illustrated embodiment, integrated circuits with patterned contact pads are passed through one of the upper compartments, in which oxide is removed from the contact pads. Continuing downward into the lower compartment and laterally beneath the barrier, a protective layer is selectively formed on the insulating layer surrounding the contact pads. As the integrated circuits are moved upwardly into the second upper compartment, a conducting monomer selectively forms on the contact pads prior to any exposure to air.

Abstract: The invention concerns a method for making safety labels which consists in producing a base deposit on the film (100), then in defining a label shape (101). It further consists in producing (102) a printed window preferably by photogravure with cells bordered by a stripe forming the window outline; printing (103) the printing window on the base deposit with a passivation coating, and developing the window (104) by a physico-chemical operation.

Abstract: Nitride layer formation includes a method wherein a material is electrodeposited on a substrate and converted, at least in part, to a layer comprising nitrogen and the electrodeposited material. The electrodepositing may occur substantially selective on a conductive portion of the substrate. Also, the converting may comprise exposing the electrodeposited material to a nitrogen-comprising plasma. Chromium nitride and chromium oxynitride are examples of nitrogen-comprising materials. Copper or gold wiring of an integrated circuit are examples of a substrate. The processing temperature during the electrodepositing and the converting may be selected not to exceed 500° C. The thickness and composition of the nitride layer may be effective to limit diffusion of the wiring through the nitride layer. A diffusion barrier forming method may include forming a patterned layer of integrated circuit copper wiring over a substrate.

Abstract: A technique for forming functionalized particles, where such particles are readily formed into periodic structures. A layer of particles is formed on a substrate, a first material is deposited over at least a portion of each of the particles, and then a functionalizing agent is attached to the first material. The functionalized particles are then capable of being formed into an ordered structure, by selection of appropriate complementary functionalizing agents on a substrate and/or on other particles and/or on other regions of the same particles.

Abstract: An advanced back-end-of-line (BEOL) integration scheme for semiconductor devices using very low-k dielectric materials is disclosed. The disclosed method for forming a metal interconnect structure in a semiconductor integrated circuit device comprises forming the metal interconnects using a through-mask plating (TMP) process, and encapsulating the interconnects with a barrier layer by selectively depositing a barrier layer material using an electroless liner plating process or by non-selectively depositing a blanket insulator diffusion barrier layer using PVD or CVD techniques.

Abstract: The present invention is to provide a method of selective electroplating comprises a substrate. The substrate may include printed circuir board or other plating metal article on printed circuit board surface specified region. Then, a wet film formed on the substrate by screen-printing, wherein the wet film is photo-sensitivty. Next, it is hardening the wet film, and then exposing the wet film. Next, it is developing the wet film to expose some region for forming metal on the substrate. A metal layer formed on the substrate. Finally, it is stripping the wet film.

Abstract: A multi-stage cooler is formed from monolithically integrated thermionic and thermoelectric coolers, wherein the thermionic and thermoelectric coolers each have a separate electrical connection and a common ground, thereby forming a three terminal device. The thermionic cooler is comprised of a superlattice barrier surrounded by cathode and anode layers grown onto an appropriate substrate, one or more metal contacts with a finite surface area deposited on top of the cathode layer, and one or more mesas of different areas formed by etching around the contacts to the anode layer. The thermoelectric cooler is defined by metal contacts deposited on the anode layer or the substrate itself. A backside metal is deposited on the substrate for connecting to the common ground.

Abstract: An anode of a cell for the electrowinning of aluminium comprises a nickel-iron alloy substrate having an openly porous nickel metal rich outer portion whose surface is electrochemically active. The outer portion is optionally covered with an external integral nickel-iron oxide containing surface layer which adheres to the nickel metal rich outer portion of the nickel-iron alloy and which in use is pervious to molten electrolyte. During use, the nickel metal rich outer portion contains cavities some or all of which are partly or completely filled with iron and nickel compounds, in particular oxides, fluorides and oxyfluorides.

Abstract: An object of the present invention is to provide a copper foil having excellent adhesion to an etching resist layer, without performing physical polishing such as buffing in pre-treatment of an etching process to form a circuit from the copper foil. To attain the object, in electroforming, a titanium material having a grain size number of 6.0 or more is employed as a copper deposition surface of the rotating drum cathode, and glue and/or gelatin is added in an amount of 0.2-20 mg/l to a copper sulfate solution, thereby producing a drum foil. An electrodeposited copper foil obtained from the drum foil, wherein 20% or more of the crystals present in a shiny side surface of the electrodeposited copper foil have a twin-crystal structure, is used for producing copper-clad laminates.

Abstract: A damascene process for introducing copper into metallization layers in microelectronic structures includes a step of forming an enhancement layer of a metal alloy, such as a copper alloy or Co—W—P, over the barrier layer, using PVD, CVD or electrochemical deposition prior to electrochemically depositing copper metallization. The enhancement layer has a thickness from 10&mgr; to 100&mgr; and conformally covers the discontinuities, seams and grain boundary defects in the barrier layer. The enhancement layer provides a conductive surface onto which a metal layer, such as copper metallization, may be applied with electrochemical deposition. Alternatively, a seed layer may be deposited over the enhancement layer prior to copper metallization.

Abstract: A method for creating a material library of surface areas having different properties in which a substrate is coated. The substrate is subjected to a combined pretreatment procedure.

Abstract: A process is provided for coating metallic workpieces with a bearing material, wherein the workpiece first receives a hard chromium plating having a pearl or columnar structure type surface. A predominantly silver layer is then galvanically deposited, which fills in and smooths the pearl or columnar structure type surface of the hard chromium plating. Optionally, additional hard chromium platings and predominantly silver-containing layers may be applied, preferably galvanically. The predominantly silver layer may advantageously contain a graphite component.

Abstract: A method of forming a copper layer with increased electromigration resistance. A doped copper layer is formed by controlling the incorporation of a non-metallic dopant during copper electroplating.

Abstract: Nitride layer formation includes a method where a material is electrodeposited on a substrate and converted, at least in part, to a layer comprising nitrogen and the electrodeposited material. The electrodepositing may occur substantially selective on a conductive portion of the substrate. Also, the converting may comprise exposing the electrodeposited material to a nitrogen-comprising plasma. Chromium nitride and chromium oxynitride are examples of nitrogen-comprising materials. Copper or gold wiring of an integrated circuit are examples of a substrate. The chromium may be converted to a chromium-nitride-comprising diffusion barrier using a nitrogen-comprising plasma.

Abstract: A porous layer is formed on an Si substrate using an anodizing apparatus having a conductive partition inserted between a cathode and an anode. First, the cathode and Si substrate are brought into electrical contact through a first electrolyte, and the conductive partition and Si substrate are brought into electrical contact through a second electrolyte. A current is flowed between the cathode and the anode to form a porous layer on the Si substrate. As the first electrolyte, an electrolyte capable of forming a porous structure on the Si substrate is used. As the second electrolyte, an electrolyte substantially incapable of forming a porous structure on the conductive partition is used.

Abstract: An inkjet printer nozzle plate having a non-wetting surface of uniform thickness and an orifice wall of tapered contour, and method of making the nozzle plate. In the method a metal masking layer is deposited on a glass substrate, the masking layer having an opening therethrough for passage of light only through the opening. Next, a negative photoresist layer is deposited on the masking layer, the negative photoresist layer being capable of photochemically reacting with the light. A light source passes light through the substrate, so that the light also passes only through the opening in the form of a tapered light cone. This tapered light cone will define the tapered contour of a nozzle plate orifice wall to be formed. The negative photoresist layer photochemically reacts with the light only in the light cone to define a light-exposed region of hardened negative photoresist.

Abstract: The present invention deposits a conductive material from an electrolyte solution to a predetermined area of a wafer and thereafter electropolishes the wafer. The steps that are used when making this application include applying the conductive material to the predetermined area of the wafer using an electrolyte solution disposed on a surface of the wafer, when the wafer is disposed between a cathode and an anode, and preventing accumulation of the conductive material to areas other than the predetermined area by mechanically polishing the other areas while conductive material is being applied. Thereafter, electropolishing of the previously applied conductive material takes place by applying a second potential difference having a polarity opposite the first potential difference that was used when applying the conductive material. While applying the second potential difference, polishing of the conductive layer with the previously accumulated conductive material disposed thereover is performed.

Abstract: A resin plate having wiring pattern recesses and via through holes is made. All of the surfaces of the resin plate including inner walls of said wiring pattern recesses and via through holes are coated with a metal film. An electroplating is applied using the metal film as a power-supply layer to fill a plated metal into the wiring pattern recesses and via through holes. The metal film formed on the resin plate except for the inner walls of the wiring pattern recesses and via through holes is removed, so that wiring pattern and via are exposed on a surface the same as that of the resin plate.

Abstract: A method is described for electroplating a metal structure in a feature formed in a substrate. A seed layer of the metal is deposited on the top surface and on the bottom and sidewalls of the feature. The seed layer is then selectively removed from the top surface, so that only a portion of the seed layer remains in the feature on at least the bottom thereof. The metal is then electroplated using this portion of the seed layer, so that the metal fills the feature. The removal of the seed layer from the top surface causes no electroplating to occur on the top surface.

Abstract: A method and apparatus for electrochemically depositing a metal into a high aspect ratio structure on a substrate are provided. In one aspect, a method is provided for processing a substrate including positioning a substrate having a first conductive material disposed thereon in a processing chamber containing an electrochemical bath, depositing a second conductive material on the first conductive material as the conductive material is contacted with the electrochemical bath by applying a plating bias to the substrate while immersing the substrate into the electrochemical bath, and depositing a third conductive material in situ on the second conductive material by an electrochemical deposition technique to fill the feature. The bias may include a charge density between about 20 mA*sec/cm2 and about 160 mA*sec/cm2. The electrochemical deposition technique may include a pulse modulation technique.

Abstract: A substrate plating apparatus forms an interconnection layer on an interconnection region composed of a fine groove and/or a fine hole defined in a substrate. The substrate plating apparatus includes a plating unit for forming a plated layer on a surface of the substrate including the interconnection region, a chemical mechanical polishing unit for chemically mechanically polishing the substrate to remove the plated layer from the surface of the substrate leaving a portion of the plated layer in the interconnection region, a cleaning unit for cleaning the substrate after the plated layer is formed or the substrate is chemically mechanically polished, a drying unit for drying the substrate after the substrate is cleaned, and a substrate transfer unit for transferring the substrate to and from each of the first plating unit, the first chemical mechanical polishing unit, the cleaning unit, and the drying unit.

Abstract: The present invention is directed to an improved electroplating method, chemistry, and production worthy apparatus for depositing noble metals (e.g., platinum) and their alloys onto the surface of the workpiece, such as a semiconductor wafer, pursuant to manufacturing a microelectronic device, circuit, and/or component. The reliability of the noble metal material deposited using the disclosed method, chemistry, and/or apparatus is significantly better than the reliability of noble metal structures deposited using the teachings of the prior art. This is largely attributable to the low stress of films that are deposited using the teachings disclosed herein. The metals, which can be deposited, include gold, silver, platinum, palladium, ruthenium, iridium, rhodium, osmium and alloys containing these metals.

Abstract: A method of producing Y-junction carbon nanotubes. An alumina template with branched growth channels is produced after which individual Y-junction carbon nanotubes are grown directly by pyrolysis of acetylene using cobalt catalysis. The use of a branched growth channel allows the natural simultaneous formation of a very large number of individual but well-aligned three-port Y-junction carbon nanotubes with excellent uniformity and control over the length (up to several tens &mgr;m) and diameter (15-100 nm) of the “stem” and “branches” separately. These Y-junctions offer the nanoelectronics community a new base material for molecular scale electronic devices including for example transistors and rectifiers.