Using Mask Patents (Class 205/666)
  • Patent number: 5565084
    Abstract: Disclosed are electropolishing methods for etching a substrate in self alignment. A hole is formed in a substrate in self alignment by using an electropolishing system, wherein a reaction tube, an etchant solution, an electrode, a constant current source and the silicon substrate, said etchant solution being contained in a space confined by the reaction tube and the substrate, which is attached to one end of the reaction tube in such a way that the bottom of the substrate may be toward the interior of the space, said constant current source being connected with a metal layer formed on the substrate and the electrode. The substrate is made to be porous by flowing a constant current and etched by the action of the etchant solution while breaking the current. In addition to being economical, the methods can determine the position and size of the hole accurately and precisely. Further, neither chemical damage nor mechanical impact is generated on the substrate.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 15, 1996
    Assignee: Qnix Computer Co., Ltd.
    Inventors: Ho J. Lee, Hi D. Lee, Jae D. Lee, Jun B. Yoon, Chul H. Han, Choong K. Kim, Doo W. Seo
  • Patent number: 5556530
    Abstract: An array of electrodes for use in a flat panel display includes a plurality of electron emitters formed of polycrystalline or single crystalline silicon which has been selectively etched to form pores in the emitters. The electrode array is then electroplated in a methane plasma to deposit a carbon compound such as silicon carbide on the surfaces of the emitters and in the pores of the emitters. Each emitter has a generally flat electron emitting surface which facilitates a longer life for the electrode array, the porous structure of the emitters increasing the electron emission efficiency of the emitters in relatively low electric fields. The electrode array can be integral with a support substrate by anisotropically etching the substrate to form the emitters. A layered interconnect structure can be formed on a surface of the silicon substrate for providing the interconnect structure for the electrode array.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: September 17, 1996
    Assignee: Walter J. Finklestein
    Inventors: Walter Finkelstein, John H. Hall