Forming Or Treating Lead Frame Or Beam Lead Patents (Class 216/14)
  • Patent number: 11006528
    Abstract: A method of making a device patterned with one or more electrically conductive features includes depositing a conductive material layer over an electrically insulating surface of a substrate, depositing an anti-corrosive material layer over the conductive material layer, and depositing an etch-resist material layer over the anti-corrosive material layer. The etch-resist material layer may be deposited over the anti-corrosive material layer, and the anti-corrosive material layer forming a bi-component etch mask in a pattern resulting in covered portions of the conductive material layer and exposed portions of the conductive material layer, the covered portions being positioned at locations corresponding to one or more conductive features of the device. A wet-etch process is performed to remove the exposed portions of the conductive material layer from the electrically insulating substrate, and the bi-component etch mask is removed to expose the remaining conductive material.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: May 11, 2021
    Assignee: KATEEVA, INC.
    Inventors: Nava Shpaisman, Moshe Frenkel
  • Patent number: 10928624
    Abstract: A microelectromechanical system (MEMS) structure includes at least first and second metal vias. Each of the first and second metal vias includes a respective planar metal layer having a first thickness and a respective post formed from the planar metal layer. The post has a sidewall, and the sidewall has a second thickness greater than 14% of the first thickness.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: February 23, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Jose A. Martinez
  • Patent number: 10654707
    Abstract: The present disclosure, in some embodiments, relates to a method for manufacturing a MEMS apparatus. The method may be performed by forming an anti-stiction layer on one or more respective surfaces of a handle substrate and a MEMS substrate. The anti-stiction layer is patterned, therein defining a patterned anti-stiction layer that uncovers one or more predetermined locations associated with a bonding of the handle substrate to the MEMS substrate. The handle substrate is bonded to the MEMS substrate at the one or more predetermined locations.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuei-Sung Chang, Fei-Lung Lai, Shang-Ying Tsai, Cheng Yu Hsieh
  • Patent number: 10468399
    Abstract: A multi-cavity package includes a single metal flange having first and second opposing main surfaces, a circuit board attached to the first main surface of the single metal flange, the circuit board having a plurality of openings which expose different regions of the first main surface of the single metal flange, and a plurality of semiconductor dies each of which is disposed in one of the openings in the circuit board and attached to the first main surface of the single metal flange. The circuit board includes a plurality of metal traces for electrically interconnecting the semiconductor dies to form a circuit. A corresponding method of manufacturing is also provided.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: November 5, 2019
    Assignee: CREE, INC.
    Inventors: Saurabh Goel, Alexander Komposch, Cynthia Blair, Cristian Gozzi
  • Patent number: 10304817
    Abstract: A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: May 28, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen
  • Patent number: 10262974
    Abstract: A link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor devices. In an embodiment the package is an integrated fan out package. The link device may be bonded on either side of the package, and the package may optionally comprise through package vias. The link device may also be an integrated passive device that includes resistors, inductor, and capacitor components.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: April 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chao-Yang Yeh, Ming-Tsun Lin, Hau Tao
  • Patent number: 10163737
    Abstract: A semiconductor device has a first interconnect structure formed over the carrier. A semiconductor die is disposed over the first interconnect structure after testing the first interconnect structure to be known good. The semiconductor die in a known good die. A vertical interconnect structure, such as a bump or stud bump, is formed over the first interconnect structure. A discrete semiconductor device is disposed over the first interconnect structure or the second interconnect structure. An encapsulant is deposited over the semiconductor die, first interconnect structure, and vertical interconnect structure. A portion of the encapsulant is removed to expose the vertical interconnect structure. A second interconnect structure is formed over the encapsulant and electrically connected to the vertical interconnect structure. The first interconnect structure or the second interconnect structure includes an insulating layer with an embedded glass cloth, glass cross, filler, or fiber.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: December 25, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen
  • Patent number: 10149391
    Abstract: Systems and techniques are provided for trench cutting with laser machining. A laminate material including a conductive layer and a non-conductive layer may be cut with a first cut using a UV-laser. The cutting of a second cut, using the UV-laser, may be started at a top electrode of the non-conductive layer based on the location of the first cut, wherein the second cut is wider than the first cut. The cutting of the second cut may be stopped partially though the non-conductive layer. The stopping of the cutting of the second cut partially though the non-conductive layer may include stopping the cutting of the second cut before cutting a bottom electrode of the non-conductive layer.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: December 4, 2018
    Assignee: uBeam Inc.
    Inventors: Nicholas Lavada Nemeth, Adam Stephen Elhadad, Andrew Joyce, Sean Taffler
  • Patent number: 9741688
    Abstract: A link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor devices. In an embodiment the package is an integrated fan out package. The link device may be bonded on either side of the package, and the package may optionally comprise through package vias. The link device may also be an integrated passive device that includes resistors, inductor, and capacitor components.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 22, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Yang Yeh, Ming-Tsun Lin, Hau Tao
  • Patent number: 9537065
    Abstract: Improves light extraction efficiency. A light emitting device 1 using a white resin molding package 5 integrally molded with lead frames 3, 4 constituting an electrode corresponding to one or a plurality of light emitting element 2 and white resin, wherein an area in a plane view of a white resin surface on a reflective surface that is level with amounting surface of the light emitting element 2 is configured to be larger than total area in a plane view occupied by surfaces of the lead frames 3, 4 and the light emitting element. Further, a step section is formed on the surfaces of lead frames 3, 4, white resin is filled in the step section, and the area of white resin surface on a reflective surface where the light emitting element 2 is mounted is increased.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: January 3, 2017
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshiki Sota, Masayuki Ohta, Kazuo Tamaki, Shinji Yamaguchi, Shin Itoh, Tomoshi Kimura, Masaki Tatsumi
  • Patent number: 9373605
    Abstract: Die packages and method of manufacturing the same are disclosed. In an embodiment, a method of manufacturing a die package may include forming an encapsulated via structure including at least one via, a polymer layer encapsulating the at least one via, and a first molding compound encapsulating the polymer layer; placing the encapsulated via structure and a first die stack over a carrier, the at least one via having a first end proximal the carrier and a second end distal the carrier; encapsulating the first die stack and the encapsulated via structure in a second molding compound; and forming a first redistribution layer (RDL) over the second molding compound, the first RDL electrically connecting the at least one via.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: June 21, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chen-Hua Yu
  • Patent number: 9332651
    Abstract: The invention provides is a process for producing a structure (22) with a metal film, including the steps of preparing a mother die (10) in which a first metal film (16) is formed on the surface of a base (12) on which a concave and convex pattern (14) is formed, forming a second metal film (18) on the first metal film (16), adhering a support member (20) to the second metal film (18), and separating the second metal film (18) to which the concave and convex pattern has been transferred to the second metal film (18) together with the support member from the first metal film (16). Preferably, the first metal film (16) is a film containing Cr and Al, and the second metal film (18) is a film containing at least one metal selected from the group consisting of Au, Ag, Cu, Al, and Pt.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: May 3, 2016
    Assignee: TOKYO UNIVERSITY OF SCIENCE FOUNDATION
    Inventor: Jun Taniguchi
  • Patent number: 9105620
    Abstract: A system and method of manufacture of an integrated circuit packaging system includes: a leadframe with a conductive layer on a leadframe active side for protecting a lead pad and a routable trace, the leadframe having an overmold recess at a leadframe inactive side; an overmold layer in the overmold recess, the overmold layer exposed between the lead pad and the routable trace for forming the lead pad and routable trace; an encapsulation directly on the conductive layer, the lead pad, the routable trace, and the overmold layer; and an external interconnect at the leadframe inactive side.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: August 11, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua, Asri Yusof
  • Publication number: 20150138298
    Abstract: According to the present disclosure, a manufacturing method of a fine wiring pattern is disclosed. The manufacturing method includes preparing a support member, forming a first layer on the support member by thick-film printing, and forming a second layer including Ag on the first layer by the thick-film printing. The method also includes forming a predetermined fine wiring pattern by performing an etching process upon the first layer and the second layer.
    Type: Application
    Filed: January 30, 2015
    Publication date: May 21, 2015
    Inventors: Shinobu Obata, Koji Nishi, Takafumi Katsuno, Masumi Okumura, Nobuhito Kinoshita
  • Patent number: 9031684
    Abstract: A method and system for integrated circuit fabrication is disclosed. In an example, the method includes determining a first process parameter of a wafer and a second process parameter of the wafer, the first process parameter and the second process parameter corresponding to different wafer characteristics; determining a variation of a device parameter of the wafer based on the first process parameter and the second process parameter; constructing a model for the device parameter as a function of the first process parameter and the second process parameter based on the determined variation of the device parameter of the wafer; and performing a fabrication process based on the model.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Han Cheng, Chin-Hsiang Lin, Chi-Ming Yang, Chun-Lin Chang, Chih-Hong Hwang
  • Publication number: 20150114925
    Abstract: Resilient electrical interposers that may be utilized to form a plurality of electrical connections between a first device and a second device, as well as systems that may utilize the resilient electrical interposers and methods of use and/or fabrication thereof. The resilient electrical interposers may include a resilient dielectric body with a plurality of electrical conduits contained therein. The plurality of electrical conduits may be configured to provide a plurality of electrical connections between a first surface of the electrical interposer and/or the resilient dielectric body and a second, opposed, surface of the electrical interposer and/or the resilient dielectric body. The systems and methods disclosed herein may provide for improved vertical compliance, improved contact force control, and/or improved dimensional stability of the resilient electrical interposers.
    Type: Application
    Filed: January 8, 2015
    Publication date: April 30, 2015
    Inventors: Kenneth R. Smith, Mike Jolley, Eric Strid, Peter Hanaway, K. Reed Gleason, Koby L. Duckworth
  • Publication number: 20150108626
    Abstract: A multilevel leadframe for an integrated circuit package is provided that has a plurality of lead lines formed in a first level and bond pads formed in a second level. A first set of bond pads is arranged in a first row and are separated from an adjacent bond pad by a bond pad clearance distance. A second set of bond pads is arranged in second row adjacent the first row of bond pads. Each bond pad in the second row may be connected to one of the plurality of lead lines on the first level that is routed between adjacent bond pads in the first row. Since the bond pads in the first row are on a different level then the lead lines, the bond pads may be spaced close together.
    Type: Application
    Filed: December 23, 2014
    Publication date: April 23, 2015
    Inventors: Lee Han Meng@ Eugene Lee, You Chye How
  • Publication number: 20140353003
    Abstract: A touch-screen conductive film includes a transparent substrate, a conductive layer and a lead electrode. The transparent substrate includes a first area, and a second area disposed surrounding the first area; the conductive layer is disposed on the first area of the transparent substrate; the lead electrode is disposed on the second area of the transparent substrate. Since the conductive layer and the lead electrode are directly set on the transparent substrate, the touch-screen conductive film is of simple structure and low cost, furthermore, the thickness of the touch-screen conductive film is reduced. In addition, the present invention also provides a method for manufacturing a touch-screen conductive film.
    Type: Application
    Filed: April 29, 2014
    Publication date: December 4, 2014
    Applicants: NANCHANG O-FILM TECH CO., LTD., SUZHOU O-FILM TECH CO., LTD., SHENZHEN O-FILM TECH CO., LTD.
    Inventors: YING GU, Guanglong Xie, Yunhua Zhao, Fanchu Zeng
  • Patent number: 8858808
    Abstract: A method of thin printed circuit board wet process consistency on the same carrier, and more particularly to a printed circuit board in the developing, copper plating, stripping, etching and other wet processes uses the same frame as a carrier from the beginning to the end of the wet process, such that the thin printed circuit board is conducted a continuous and automatic wet process to avoid disassembly, storage and transportation between each process. Moreover, when using the flame, the thin printed circuit board is smooth and flattening in the wet process for avoiding “water effect,” the effective area is not exposed to any mechanical members for preventing scratches, and there are point contacts between the thin printed circuit board and the frame for preventing chemical residue. Accordingly, the present invention can not only enhance the yield of the thin printed circuit board but also shorten the production time.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: October 14, 2014
    Assignee: Kinsus Interconnect Technology Corp.
    Inventor: Cheng-Hsiung Yang
  • Patent number: 8859077
    Abstract: A plurality of openings are formed in a resin insulation layer on a bottom surface side of a wiring laminate portion which constitutes a multilayer wiring substrate. A plurality of motherboard connection terminals are disposed to correspond to the openings. The motherboard connection terminals are primarily comprised of a copper layer, and peripheral portions of terminal outer surfaces thereof are covered by the outermost resin insulation layer. A dissimilar metal layer made of at least one metal which is lower in etching rate than copper is formed between an inner main surface of the outermost resin insulation layer and peripheral portions of the terminal outer surfaces.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: October 14, 2014
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Shinnosuke Maeda, Tetsuo Suzuki, Satoshi Hirano
  • Patent number: 8846421
    Abstract: A method of manufacturing a lead frame for a light-emitting device package and a light-emitting device package are provided. The method of manufacturing a lead frame for a light-emitting device package includes: preparing a base substrate for the lead frame; forming diffusion roughness on the base substrate; and forming a reflective plating layer on the diffusion roughness formed base substrate.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: September 30, 2014
    Assignee: MDS Co. Ltd.
    Inventors: Jin-Woo Lee, Jae-Hoon Jang, Dong-Hoon Lee, Jae-Ha Kim
  • Publication number: 20140203418
    Abstract: A method of manufacturing a lead frame, comprising the steps of: providing an electrically-conductive base material having first and second planar sides; forming a patterned conductive layer on the first planar side of the base material; etching the second planar side of the base material at portions with respect to exposed portions on the first planar side of the base material comprising the patterned conductive layer, to form partially-etched portions on the second planar side of the base material; providing a non-conductive filling material over the second planar side of the base material, wherein the filling material fills spaces inside the partially-etched portions on the second planar side of the base material to form adjacent portions of the filling material and a plurality of conductive portions on the second planar side of the base material; and etching the exposed portions of the first planar side of the base material comprising the patterned conductive layer to form partially-etched portions on the
    Type: Application
    Filed: January 17, 2014
    Publication date: July 24, 2014
    Inventors: Dawei XING, Jie LIU, Hong Wei GUAN, Yue Gen YU, Seow Kiang KHOO
  • Publication number: 20140202736
    Abstract: Disclosed is a method of manufacturing a lead frame, which comprises the steps of: providing an electrically-conductive base material having first and second planar sides; forming a plurality of conductive contact points on the first planar side of the base material; providing a non-conductive filling material over the first planar side of the base material so that the filling material fills spaces in-between the plurality of contact points to a form a layer comprising the filling material and the plurality of contact points; and etching the second planar side of the base material to expose a pattern of the filling material from the second planar side of the base material and to thereby form a plurality of isolated conductive regions on the second planar side of the base material, each isolated conductive region being connected with at least a respective one of the plurality of contact points on the first planar side of the base material. A lead frame structure is also disclosed.
    Type: Application
    Filed: January 23, 2013
    Publication date: July 24, 2014
    Inventors: Dawei XING, Jie LIU, Hong Wei GUAN, Yue Gen YU, Seow Kiang KHOO
  • Publication number: 20140145565
    Abstract: An electronic assembly group comprising a printed circuit board structure in a multilayer configuration that has at least two electrically conductive layers. The electronic assembly group also comprises an additional passive component that is connected to the two electrically conductive layers, each of which has at least one segment that extends beyond the multilayer structure to form connection regions, the passive component making contact directly at the connection regions.
    Type: Application
    Filed: February 3, 2014
    Publication date: May 29, 2014
    Inventors: Thomas GOTTWALD, Christian ROSSLE
  • Publication number: 20140035095
    Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.
    Type: Application
    Filed: December 20, 2012
    Publication date: February 6, 2014
    Applicant: Media Tek Inc.
    Inventors: Tzu-Hung LIN, Wen-Sung HSU, Ta-Jen YU, Andrew C. CHANG
  • Publication number: 20140021162
    Abstract: A manufacturing method of a lead frame substrate includes: applying a photosensitive resist or a dry film to first and second surfaces of a metal plate; pattern-exposing the photosensitive resist or the dry film, and then developing the first surface and the second surface to form on the first surface a first resist pattern for forming a connection post and to form on the second surface a second resist pattern for forming a wiring pattern; etching the first surface partway down the metal plate to form the connection post; filling the first surface with a pre-molding resin to a thickness with which the etched surface is buried; removing the pre-molding resin uniformly in a thickness direction of the pre-molding resin until a bottom surface of the connection post is exposed; and etching the second surface to form a wiring pattern.
    Type: Application
    Filed: September 26, 2013
    Publication date: January 23, 2014
    Applicant: TOPPAN PRINTING CO., LTD.
    Inventors: Susumu Maniwa, Takehito Tsukamoto, Junko Toda
  • Publication number: 20130345780
    Abstract: Thin-film multi-electrode arrays (MEA) having one or more electrically conductive beams conformally encapsulated in a seamless block of electrically insulating material, and methods of fabricating such MEAs using reproducible, microfabrication processes. One or more electrically conductive traces are formed on scaffold material that is subsequently removed to suspend the traces over a substrate by support portions of the trace beam in contact with the substrate. By encapsulating the suspended traces, either individually or together, with a single continuous layer of an electrically insulating material, a seamless block of electrically insulating material is formed that conforms to the shape of the trace beam structure, including any trace backings which provide suspension support. Electrical contacts, electrodes, or leads of the traces are exposed from the encapsulated trace beam structure by removing the substrate.
    Type: Application
    Filed: March 11, 2013
    Publication date: December 26, 2013
    Inventors: Phillipe J. Tabada, Kedar G. Shah, Vanessa Tolosa, Satinderall S. Pannu, Angela Tooker, Terri Delima, Heeral Sheth, Sarah Felix
  • Patent number: 8535546
    Abstract: In order to provide a method of manufacturing a multilayer wiring substrate, a base member having a copper foil separably laminated thereon is prepared, and a solder resist layer is formed on the copper foil. Openings are formed in the solder resist layer, and a metal conductor portion is formed in each of the openings. By means of sputtering, a dissimilar metal layer is formed over the surface of the metal conductor portion and the entire surface of the solder resist layer. Copper electroplating is performed so as to form connection terminals and a conductor layer on the dissimilar metal layer. After a build-up step, the base material is removed, whereby the copper foil is exposed, and the exposed copper foil and the metal conductor portion are removed through etching, whereby the surfaces of the external connection terminals are exposed from the openings.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: September 17, 2013
    Assignee: NGK Spark Plug Co., Ltd.
    Inventor: Shinnosuke Maeda
  • Publication number: 20130112652
    Abstract: A manufacturing method of a semiconductor element substrate including: forming a first photoresist pattern on a first surface of a metallic plate, to form a semiconductor element mounting part, a semiconductor element electrode connection terminal, a wiring, an outer frame part, and a slit; forming a second photoresist pattern on the second surface of the metallic plate; forming the slit by half etching to connect the metallic chip with a four corners of the outer frame part; forming a plurality of concaved parts on the second surface of the metallic plate; forming a resin layer by injecting a resin to the plurality of concaved parts; and etching the first surface of the metallic plate and forming the semiconductor element electrode connection terminal and the outer frame.
    Type: Application
    Filed: October 31, 2012
    Publication date: May 9, 2013
    Applicant: TOPPAN PRINTING CO., LTD.
    Inventor: TOPPAN PRINTING CO., LTD.
  • Publication number: 20120228660
    Abstract: A method of manufacturing a lead frame for a light-emitting device package and a light-emitting device package are provided. The method of manufacturing a lead frame for a light-emitting device package includes: preparing a base substrate for the lead frame; forming diffusion roughness on the base substrate; and forming a reflective plating layer on the diffusion roughness formed base substrate. A lead frame for a light-emitting device and a light-emitting device package having a wide viewing angle and a wide radiation width by surface processing are provided.
    Type: Application
    Filed: March 9, 2012
    Publication date: September 13, 2012
    Applicant: SAMSUNG TECHWIN CO., LTD.
    Inventors: Jin-Woo LEE, Jae-Hoon JANG, Dong-Hoon LEE, Jae-Ha KIM
  • Publication number: 20120094438
    Abstract: A frame includes heat slug pads coupled together in a N×M matrix such that singulation of the heat slug pads consists of one or more parallel passes across the frame. Each heat slug pad has a top exposed surface and a bottom interfacing surface. The bottom interfacing surface typically interfaces with a package. In some embodiments, the top exposed surface is modified. Alternatively, the bottom interfacing surface is modified. Alternatively, both surfaces are modified. A modified top exposed surface can include a pattern to increase the top exposed surface area. A modified bottom interfacing surface can include a pattern to increase the bottom interfacing surface area, provide reference points, or both. Alternatively or in addition to, the modified bottom interfacing surface can be plated to increase the bottom interfacing surface area. A patterned surface can be obtained via a stamping process or an etching process.
    Type: Application
    Filed: December 21, 2011
    Publication date: April 19, 2012
    Applicant: UTAC THAI LIMITED
    Inventor: Saravuth Sirinorakul
  • Patent number: 8153478
    Abstract: A method for manufacturing an integrated circuit package system includes: forming a die paddle; forming an under paddle leadframe including lower leadfingers thereon; attaching the under paddle leadframe to the die paddle with the lower leadfingers extending under the die paddle; attaching a die to the die paddle; and planarizing a bottom surface of the under paddle leadframe to separate the lower leadfingers under the die paddle.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: April 10, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Guruprasad Badakere Govindaiah, Arnel Trasporto
  • Publication number: 20120061809
    Abstract: Provided is a manufacturing method of a substrate for a semiconductor element, the manufacturing method including the steps of: providing a first photosensitive resin layer at a first surface of a metal plate; providing a second photosensitive resin layer at a second surface of the metal plate different from the first surface; forming a first etching mask for forming a connection post on the first surface of the metal plate; forming a second etching mask for forming a wiring post on the second surface of the metal plate; forming the connection post by performing an etching on the first surface of the metal plate from a first surface side to a midway of the metal plate; applying a premold resin in liquid form to the first surface of the metal plate which underwent the etching on the first surface; forming a premold resin layer by solidifying the premold resin in liquid form being applied; and forming a wiring pattern by performing an etching on the second surface of the metal plate from a second surface side.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 15, 2012
    Applicant: TOPPAN PRINTING CO., LTD
    Inventors: Junko TODA, Susumu Maniwa, Yasuhiro Sakai, Takehito Tsukamoto
  • Patent number: 8114713
    Abstract: A lead frame includes a base material having a front surface for mounting of a semiconductor chip and a back surface for connection with an external board, and an Ni layer having a thick section and thin section. The thick section is formed on the back surface of the base material, whereas the thin section is formed on all or a part of the front surface of the base material. It is preferable that the thick section has a thickness ranging from 2.5 to 5 ?m, and the thin section is 0.5-2 ?m thinner than the thick section. The lead frame can be manufactured with improved productivity by forming an Ni layer on both front and back surfaces of the base material, and then etching only the Ni layer formed on the front surface of the base material.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: February 14, 2012
    Assignee: Sumitomo Metal Mining Co., Ltd.
    Inventor: Juntaro Mikami
  • Publication number: 20120018867
    Abstract: Provided is a manufacturing method of a semiconductor element substrate including: a step of forming a first photoresist pattern on a first surface of a metallic plate, to form a semiconductor element mounting part, a semiconductor element electrode connection terminal, a wiring, an outer frame part, and a slit; a step of forming a second photoresist pattern on the second surface of the metallic plate; a step of forming the slit by half etching to connect the metallic chip with a four corners of the outer frame part; a step of forming a plurality of concaved parts on the second surface of the metallic plate; a step of forming a resin layer by injecting a resin to the plurality of concaved parts; and a step of etching the first surface of the metallic plate and forming the semiconductor element electrode connection terminal and the outer frame.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 26, 2012
    Applicant: TOPPAN PRINTING CO., LTD.
    Inventors: Junko Toda, Susumu Maniwa, Takehito Tsukamoto
  • Publication number: 20120018860
    Abstract: Provided is a manufacturing method of a substrate for a semiconductor element including the steps of: providing a first photosensitive resin layer on a first surface of a metal plate; providing a second photosensitive resin layer on a second surface different from the first surface of the metal plate; forming a first etching mask for forming a connection post on the first surface of the metal plate; forming a second etching mask for forming a wiring pattern on the second surface of the metal plate; forming the connection post by performing an etching from the first surface to a midway of the metal plate; filling in a premold resin to a portion of the first surface where the connection post does not exist; processing so that a height of the connection post of the first surface is lower than a height of the premold resin surrounding the connection post; and forming the wiring pattern by performing an etching on the second surface.
    Type: Application
    Filed: September 30, 2011
    Publication date: January 26, 2012
    Applicant: TOPPAN PRINTING CO., LTD.
    Inventors: Susumu MANIWA, Takehito Tsukamoto, Junko Toda
  • Patent number: 8088692
    Abstract: A method for fabricating a multilayer microstructure with balancing residual stress capability includes forming a multilayer microstructure on a silicon substrate and conducting a step of isotropic plasma etching. The multilayer microstructure includes a first metal layer and a second metal layer patterned and aligned symmetrically to form etching through holes; a metal via layer surrounding each etching through hole; and an insulating layer filling each etching through hole and disposed between the substrate and the first metal layer. The step of isotropic chemical plasma etching removes the insulating layer in each etching through hole, the insulating layer between the substrate and the metal layer and a portion of the substrate to form a suspended multilayer microstructure on the substrate, during which a chamber pressure larger than vacuum and maintains a ratio between a lateral etching rate and a vertical etching rate between 0.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: January 3, 2012
    Assignee: National Tsing Hua University
    Inventors: Ying-Jui Huang, Hwai-Pwu Chou
  • Publication number: 20110309484
    Abstract: A semiconductor package includes a lead frame, a first chip, a second chip, a plurality of bonding wires and a mold compound. The lead frame includes a pad portion at a center of the frame and a plurality of lead portions. The pad portion and the plurality of lead portions collectively define a receiving portion. The first chip is securely received in the receiving portion. The second chip is mechanically attached to the first chip. The plurality of bonding wires electrically connect the second chip to the plurality of lead portions. The mold compound encapsulates the lead frame, the first chip, the second chip and the plurality of bonding wires to form the semiconductor package.
    Type: Application
    Filed: March 23, 2011
    Publication date: December 22, 2011
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., AMBIT MICROSYSTEMS (ZHONGSHAN) LTD.
    Inventor: WANG-LAI YANG
  • Publication number: 20110284495
    Abstract: Various structures and fabrication methods for leadless plastic chip carrier (QFN) packages which utilize carriers in strip format, wherein the leads (or terminals) are formed to be electrically isolated from one another within each unit and in which the units are formed to be electrically isolated from one another within the strip using chemical etching techniques.
    Type: Application
    Filed: September 20, 2007
    Publication date: November 24, 2011
    Applicant: ASAT LIMITED
    Inventors: Tung Lok Li, Kwok Cheung Tsang, Kin Pui Kwan
  • Publication number: 20110272793
    Abstract: In a lead frame for a semiconductor apparatus 10, including plural terminals 13, one portions of the terminals 13 being sealed with a resin, a resin-sealed portion 16 of the terminal 13 has a polygonal columnar shape that is pentagonal or more or a deformed columnar shape having at least one notch or groove part extending vertically in a periphery. This resin-sealed portion 16 is formed by etching processing or press processing, and an exposed portion 18 of lower half of the terminal 13 is formed by the etching processing.
    Type: Application
    Filed: November 24, 2009
    Publication date: November 10, 2011
    Applicant: MITSUI HIGH-TEC, INC.,
    Inventors: Koji SHIMIZU, Hiroaki YATSUKAWA
  • Publication number: 20110226729
    Abstract: A method of manufacturing a flex circuit is disclosed for a disk drive comprising a disk, a head actuated radially over the disk, and control circuitry. The flex circuit is for electrically coupling the head to the control circuitry and comprises a substrate. An electrical coating applied to a first side of the substrate is etched to form a first electrical lead. The first side of the substrate is irradiated with radiation such that the first electrical lead masks the radiation from passing through the substrate to prevent curing of a photoresist applied to the second side of the substrate to form an uncured photoresist and a cured photoresist on the second side of the substrate. The uncured photoresist is removed from the second side of the substrate to form a groove, and the groove is filled with electrically conductive material to form the second electrical lead.
    Type: Application
    Filed: May 30, 2011
    Publication date: September 22, 2011
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: DENNIS W. HOGG
  • Publication number: 20110227208
    Abstract: The present invention relates to structure and manufacture method for multi-row lead frame and semiconductor package, the method characterized by forming a pad portion on a metal material (first step); performing a surface plating process or organic material coating following the first pattern formation (second step); forming a second pattern on the metal material (third step); and packaging a semiconductor chip following the second pattern formation (fourth step), whereby an under-cut phenomenon is minimized by applying a gradual etching.
    Type: Application
    Filed: September 25, 2009
    Publication date: September 22, 2011
    Inventors: Ji Yun Kim, Hyun Sub Shin, Sung Won Lee, Hyung Eui Lee, Yeong Uk Seo, Sung Wuk Ryu, Hyuk Soo Lee
  • Publication number: 20110200788
    Abstract: A plurality of openings are formed in a resin insulation layer on a bottom surface side of a wiring laminate portion which constitutes a multilayer wiring substrate. A plurality of motherboard connection terminals are disposed to correspond to the openings. The motherboard connection terminals are primarily comprised of a copper layer, and peripheral portions of terminal outer surfaces thereof are covered by the outermost resin insulation layer. A dissimilar metal layer made of at least one metal which is lower in etching rate than copper is formed between an inner main surface of the outermost resin insulation layer and peripheral portions of the terminal outer surfaces.
    Type: Application
    Filed: February 16, 2011
    Publication date: August 18, 2011
    Applicant: NGK SPARK PLUG CO., LTD.
    Inventors: Shinnosuke MAEDA, Tetsuo SUZUKI, Satoshi HIRANO
  • Patent number: 7998790
    Abstract: A method of manufacture of an integrated circuit die packaging system includes: providing a lead frame having a die attach paddle, an isolated pad, and a connector; attaching an integrated circuit die to the die attach paddle and the connector; forming an encapsulation over the integrated circuit die, the connector, the die attach paddle, and the isolated pad; and singulating the connector and the die attach paddle whereby the isolated pads are electrically isolated.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: August 16, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay, Jose Alvin Caparas
  • Patent number: 7993972
    Abstract: A method of manufacturing a semiconductor device includes providing a wafer for supporting the semiconductor device. An insulation layer is disposed over a top surface of the wafer. The method includes forming a first interconnect structure over the top surface of the wafer with temperatures in excess of 200° C., forming a metal pillar over the wafer in electrical contact with the first interconnect structure, connecting a semiconductor component to the first interconnect structure, and forming encapsulant over the semiconductor component. The encapsulant is etched to expose a portion of the metal pillar. A buffer layer is optionally formed over the encapsulant. The method includes forming a second interconnect structure over the encapsulant in electrical contact with the metal pillar with temperatures below 200° C., and removing a portion of a backside of the wafer opposite the top surface of the wafer.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: August 9, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Haijing Cao
  • Publication number: 20110189848
    Abstract: Described is a method of forming a solder deposit on a substrate comprising the following steps i) provide a substrate including a surface bearing electrical circuitry that includes at least one contact area, ii) form a solder mask layer that is placed on the substrate surface and patterned to expose the at least one contact area, iii) contact the entire substrate area including the solder mask layer and the at least one contact area with a solution suitable to provide a conductive layer on the substrate surface, iv) electroplate a solder deposit layer containing a tin or tin alloy onto the conductive layer and v) etch away an amount of the solder deposit layer containing tin or tin alloy sufficient to remove the solder deposit layer from the solder mask layer area leaving a solder material layer on the at least one contact area.
    Type: Application
    Filed: October 7, 2009
    Publication date: August 4, 2011
    Inventors: Ingo Ewert, Sven Lamprecht, Kai-Jens Matejat, Thomas Pliet
  • Patent number: 7989931
    Abstract: An integrated circuit package system is provided including: forming a die paddle; forming an under paddle leadframe including lower leadfingers thereon; attaching the under paddle leadframe to the die paddle with the lower leadfingers extending under the die paddle; attaching a die to the die paddle; and planarizing the bottom surface of the under paddle leadframe to separate the lower leadfingers under the die paddle.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: August 2, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Guruprasad Badakere Govindaiah, Arnel Trasporto
  • Publication number: 20110169153
    Abstract: A method includes: forming a photoresist pattern to form each of a semiconductor element mounting section on which a semiconductor element is mounted, semiconductor element electrode connection terminals for connection with electrodes of the semiconductor element, and a first outer frame section on a first surface of a metal plate; forming a photoresist pattern to form each of external connection terminals, a second outer frame section, and grooves in at least a part of the second outer frame section on a second surface of the metal plate; etching a metal plate exposing section, in which the metal plate of the second surface is exposed, to form holes that do not pass through the metal plate exposing section and grooves that run from an inside to an outside of the second outer frame section; coating a pre-mold resin on the holes and the grooves, and heating the pre-mold resin under pressure using a flat-bed press to form a resin layer; and etching the first surface to form the semiconductor element mounting se
    Type: Application
    Filed: March 17, 2011
    Publication date: July 14, 2011
    Applicant: TOPPAN PRINTING CO., LTD.
    Inventors: Takehito Tsukamoto, Susumu Maniwa, Junko Toda
  • Publication number: 20110163435
    Abstract: A lead frame substrate, includes: a metal plate having first and second surfaces; a semiconductor element mounting section, semiconductor element electrode connection terminals, and a first outer frame section formed on the first surface; external connection terminals formed on the second surface and electrically connected with the semiconductor element electrode connection terminals; a second outer frame section formed on the second surface; and a resin layer formed on a gap between the first outer frame and the second outer frame. Each external connection terminal buried in the resin layer has at least one projection formed on a side surface thereof throughout a side lower portion of the first surface.
    Type: Application
    Filed: March 10, 2011
    Publication date: July 7, 2011
    Applicant: Toppan Printing Co., Ltd.
    Inventors: Takehito Tsukamoto, Susumu Maniwa, Junko Toda, Yasuhiro Sakai
  • Publication number: 20110163433
    Abstract: A lead frame substrate, including: a metal plate having a first surface and a second surface; a semiconductor element mount portion and a semiconductor element electrode connection terminal that are formed on the first surface; an external connection terminal formed on the second surface and electrically connected to the semiconductor element electrode connection terminal; a conducting wire that connects the semiconductor element electrode connection terminal and the external connection terminal to each other; a resin layer formed on the metal plate; a hole portion that is partly formed in the second surface of the metal plate and does not penetrate the metal plate; and a plurality of protrusions that are formed on a bottom surface of the hole portion and protrude in a direction away from the metal plate, the protrusions having a height lower than a position of the second surface, not being in electrical conduction with the conducting wire, and being dispersed separately.
    Type: Application
    Filed: September 28, 2009
    Publication date: July 7, 2011
    Applicant: Toppan Printing Co., Ltd.
    Inventors: Junko Toda, Susumu Maniwa, Yasuhiro Sakai, Takehito Tsukamoto