Abstract: A method includes: forming a photoresist pattern to form each of a semiconductor element mounting section on which a semiconductor element is mounted, semiconductor element electrode connection terminals for connection with electrodes of the semiconductor element, and a first outer frame section on a first surface of a metal plate; forming a photoresist pattern to form each of external connection terminals, a second outer frame section, and grooves in at least a part of the second outer frame section on a second surface of the metal plate; etching a metal plate exposing section, in which the metal plate of the second surface is exposed, to form holes that do not pass through the metal plate exposing section and grooves that run from an inside to an outside of the second outer frame section; coating a pre-mold resin on the holes and the grooves, and heating the pre-mold resin under pressure using a flat-bed press to form a resin layer; and etching the first surface to form the semiconductor element mounting se

Abstract: A lead frame substrate, including: a metal plate having a first surface and a second surface; a semiconductor element mount portion and a semiconductor element electrode connection terminal that are formed on the first surface; an external connection terminal formed on the second surface and electrically connected to the semiconductor element electrode connection terminal; a conducting wire that connects the semiconductor element electrode connection terminal and the external connection terminal to each other; a resin layer formed on the metal plate; a hole portion that is partly formed in the second surface of the metal plate and does not penetrate the metal plate; and a plurality of protrusions that are formed on a bottom surface of the hole portion and protrude in a direction away from the metal plate, the protrusions having a height lower than a position of the second surface, not being in electrical conduction with the conducting wire, and being dispersed separately.

Abstract: A lead frame substrate, includes: a metal plate having first and second surfaces; a semiconductor element mounting section, semiconductor element electrode connection terminals, and a first outer frame section formed on the first surface; external connection terminals formed on the second surface and electrically connected with the semiconductor element electrode connection terminals; a second outer frame section formed on the second surface; and a resin layer formed on a gap between the first outer frame and the second outer frame. Each external connection terminal buried in the resin layer has at least one projection formed on a side surface thereof throughout a side lower portion of the first surface.

Abstract: A lead frame comprises on a same plane, a pad part including an LED chip mounting upper surface A on which at least an LED chip is to be mounted, and a lead part including an electric connection area C in which an electric connection with the LED chip is made. A relationship between an area S1 of the mounting upper surface of the pad part 2 and an area S2 of a radiating lower surface opposite to the mounting upper surface is represented by 0<S1<S2. Side surfaces of the pad part between the mounting upper surface and the radiating lower surface are provided with stepped parts or tapered parts which spread in a direction from the mounting upper surface toward the radiating lower surface and hold a resin-filled during molding.

Abstract: A method for forming micro-texture on ABS of a slider, includes steps of: positioning sliders arranged in arrays on a tray, each slider having a pole tip facing upward; loading the tray into a processing chamber, and evacuating the processing chamber to a preset pressure; introducing a mixture gas of inert gas and hydrocarbon gas into the processing chamber, and ionizing the mixture gas to produce ion beams; exposing the sliders to the ion beam for etching so as to form micro-texture with two-step structure on the ABS of the slider. The invention also discloses a method of manufacturing a slider having micro-texture.

Abstract: A method for removing an undesirable material from an electronic or electrical component and introducing a desirable material in place of the undesirable material. The method can include the replacement of a leaded material found on the component with a no-lead material to meet governmental directives including those of the European Union.

Abstract: A leadframe structure is disclosed. The leadframe structure includes a first leadframe structure portion with a first thin portion and a first thick portion, where the first thin portion is defined in part by a first recess. It also includes a second leadframe structure portion with a second thin portion and a second thick portion, where the second thin portion is defined in part by a second recess. The first thin portion faces the second recess, and the second thin portion faces the first recess.

Abstract: A method for simultaneously forming multiple line-widths, one of which is less than that achievable employing conventional lithographic techniques. The method includes providing a structure which includes a memory layer and a sidewall image transfer (SIT) layer on top of the memory layer. Then, the SIT layer is patterned resulting in a SIT region. Then, the SIT region is used as a blocking mask during directional etching of the memory layer resulting in a first memory region. Then, a side wall of the SIT region is retreated a retreating distance D in a reference direction resulting in a SIT portion. Said patterning comprises a lithographic process. The retreating distance D is less than a critical dimension CD associated with the lithographic process. The SIT region includes a first dimension W2 and a second dimension W3 in the reference direction, wherein CD<W2<2D<W3.

Abstract: A method for decapsulating a package is provided. The method comprises steps of providing a package having a chip therein, wherein the chip has an active surface and a rear surface. Further, the package further comprises a heat sink, a plurality of solder bumps, a substrate, an underfill and a plurality of solder balls. The method further comprises removing the heat sink and removing the substrate together with the solder balls. A dry etching process is performed to remove a portion of the underfill. A wet etching process is performed to remove the rest portion of the underfill. A thermal process solder bump removal process is performed to melt the solder bumps and then a solder bump removal process is performed to remove the melted solder bumps from the active surface of the chip.

Abstract: Provided are a circuit board and a method of manufacturing the same. The method includes: forming a pad portion and a lead line portion of a metal on an insulating substrate, wherein the lead line portion is connected to the pad portion; forming a conductive layer on the pad portion and the lead line portion, wherein the conductive layer has an upper surface comprising gold; forming an etching mask on the conductive layer so as to expose a portion corresponding to the lead line portion in the conductive layer; etching a portion of the lead line portion exposed by the etching mask and a portion of the conductive layer corresponding to the lead line portion using an etching solution containing an acid; and removing the etching mask.

Abstract: In conventional electronic component mounting boards, a leg section of a metal frame manufactured of a metal block attached to a circuit board is firmly adhered to a board with a solder and the like, and heat due to light emission of a LED element is dissipated through the leg section of the metal frame, and heat dissipation performance is improved. In the conventional electronic component mounting boards, however, high heat conductance of the metal frame is not efficiently exhibited due to existence of an adhesive layer and the like having a lower heat conductance. In order to improve a certain limit existed in luminance and lifetime due to temperature increase of the LED element, a frame having heat conductance is attached on an upper plane of a circuit board whereupon a plurality of conductors are formed, and the frame and one of the conductors of the circuit board are heat-conductively connected.

Abstract: A lead frame has a die pad on which a semiconductor chip is mounted, a plurality of leads, a first recess provided so as to sink in from the front surface of the die pad, and second recesses and third recesses (through holes) provided so as to sink in from the front surface and the rear surface of the leads, respectively. The inner wall surfaces of the first recess, the second recesses and the third recesses (through holes) are made uneven, respectively.

Abstract: A method for producing a wired circuit board includes the steps of integrally forming a conductive pattern, a plating lead electrically connected with the conductive pattern, and a regulation portion provided in the plating lead to regulate penetration of an etchant into the conductive pattern; and etching the plating lead with the etchant while the regulation portion regulates the penetration of the etchant into the conductive pattern.

Abstract: Provided are a lead frame, a semiconductor package, and a method of manufacturing the lead frame and the semiconductor package. The lead frame includes: a die pad on which a semiconductor chip is installable; a plurality of lead patterns formed around a circumference of the die pad; an insulating organic material filling etching spaces interposed between the die pad and the lead patterns and structurally supporting the die pad and the lead patterns; and a pre-plating layer formed on both upper and lower surfaces of the die pad and the lead patterns.

Abstract: A sensor for measuring physical parameters, wherein a sensor element, arranged on a substrate platelet, may be connected to an evaluating circuit by means of connection leads. The connection leads are a planar piece made from sheet metal. connection leads have a plurality of perforations between connection areas The perforations being preferably triangular, with adjacent triangles rotated relative to each other by 180 degrees, such that the connection lead is embodied as a planar lattice of longitudinal legs and inclined, transverse legs. The thermal conductance through the connection between sensor and evaluating circuit is reduced by means of said perforations. The response characteristics and precision of the sensor are hence improved.

Abstract: A circuit member 20 includes a lead frame material 1 having a die pad 3, a lead part 6 to be electrically connected with a semiconductor chip 30, and an outer frame 2 configured to support the die pad and the lead part. The lead frame material includes a resin sealing region 9. Roughened faces 10A to 10C and 11A to 11C, each having an average roughness Ra of 0.3 ?m or greater, are formed on a surface in the resin sealing region of the lead frame material. The surface of the lead frame material except for the resin sealing region is a flat and smooth face. A two-layer plated layer 12A formed by laminating a Ni plated layer 13 and a Pd plated layer 14 in this order or a three-layer plated layer 12B formed by laminating the Ni plated layer 13, the Pd plated layer 14 and an Au plated layer 15 in this order is formed on the whole surface of the lead frame material.

Abstract: The present invention relates to a circuit board including a flexible film provided with an extremely fine circuit pattern, a laminated member for a circuit board, and a method for making a laminated member for a circuit board with excellent productivity. A circuit board of the present invention includes a flexible film and a circuit pattern composed of a metal provided on the flexible film, and dimensional change rate of the circuit pattern is within ±0.01%. A laminated member for a circuit board of the present invention includes a reinforcing plate, a self-stick, removable organic layer, a flexible film, and a circuit pattern composed of a metal laminated in that order.

Abstract: A leadframe package includes a die pad with four unitary, outwardly extending slender bars; a plurality of leads arranged along periphery of the die pad; a separate pad segment separated from the die pad and isolated from the plurality of leads; a semiconductor die mounted on an upper side of the die pad, wherein the semiconductor die contains first bond pads wire-bonded to respective the plurality of leads and a second bond pad wire-bonded to the separate pad segment; and a molding compound encapsulating the semiconductor die, the upper side of the die pad, the first suspended pad segment and inner portions of the plurality of leads.

Abstract: A contact electrode for a device is made using an etching process to etch the surface of the contact electrode to form a corrugated contact surface wherein the outer edges of at least one grain is recessed from the outer edges of adjacent grains and is recessed by at least about 0.05 ?m from the contact plane. By having such a corrugated surface, the contact electrode is likely to contact another conductor with at least one pure metal grain. This etching treatment reduces contact resistance and contact resistance variability throughout many cycles of use of the contact electrode.

Abstract: A probe substrate includes a probe having a plurality of beams and a contactor formed at one end of the beam, and a support substrate for supporting the probe and having a bending space in which the probe moves upwards and downwards. The beam and the contactor are made of the same metal, and the sidewall of the contactor has a staircase configuration. Therefore, the probe substrate and the manufacturing method thereof repeats the lithographic process and the plating process to form the probe having the beam and the contactor combined, thereby increasing the bending degree and structural stability of the probe.

Abstract: A probe substrate includes a plurality of beams, a probe having a contactor formed at one end of the beam, and a support substrate supporting the probe and having a bending space in which the probe can be bent upwards and downwards, and a trench oxide layer is formed on the upper surface of the support substrate. Therefore, the probe substrate and a manufacturing method thereof according to the present invention forms a trench oxide layer on the boundary of the beam and the support substrate to prevent the boundary from being damaged by stress applied to the boundary according to continuous and repeated bending of the beam. Therefore, electrical insulation between the beam and the support substrate is maintained to prevent electrical leakage.

Abstract: A method for forming alignment films in LCDs includes forming a conductive film on an LCD substrate, forming an inorganic alignment film on the conductive film, and etching the alignment film with an etching apparatus that includes a nozzle that sprays a plasma at atmospheric pressure onto a surface of the alignment film without using a mask pattern so as to form an etched region in the alignment film that exposes a portion of the underlying conductive film therethrough. The novel method enables LCD alignment films having sharp thickness profiles to be patterned easily and accurately, reduces the time required to manufacture LCDs, and minimizes the number of devices required to manufacture the LCDs.

Abstract: The present invention relates to a method of manufacturing a semiconductor device. In the method, an etching-back layer consisting of aluminum or copper is formed on a base substrate and a multilayer wiring board is manufactured on the etching-back layer. After that the etching-back layer is etched to be removed under the condition that the multilayer wiring board and the base substrate are not etched, so that the base substrate is separated from the multilayer wiring board. Accordingly, the base substrate can be reused.

Abstract: Manufacturing process for manufacturing printed circuit boards from an extruded polymer, comprising the steps:-preparing an electro-conductive plate (10) and form embossments (11) by means of selective engraving on a first side (10a), corresponding to future tracks and depressions (12) corresponding to future inter-track areas;-applying a dielectric substrate material, in a pasty or semi-pasty state, according to a first sheet (20a) obtained by extrusion of a thermal-plastic material, arranging it on said first side (10a), covering said embossments (11) and filling said depressions (12), and subjecting the first sheet (20a) and plate (10) assembly to a predetermined pressure so that the dielectric substrate material completely fills said depressions and encloses said embossments (11), and-on the hardened dielectric substrate, carrying out a second selective engraving on a side opposite the first side (10a), removing the material corresponding to said future inter-track areas.

Abstract: A method for forming a recognition mark on the back surface of a substrate for a KGD that can be easily produced at a low manufacturing cost and permits repeated use of a substrate is provided. In the method, wiring patterns are formed on a surface of one side of an insulating substrate. The method includes a step of forming a conductive pattern as a recognition mark on one surface where the wiring patterns are formed, and a step of forming a through hole from a surface where the wiring pattern is not formed toward the conductive pattern. In the substrate, bumps connected with the KGD are formed on the surface on which the wiring patterns are not formed. Also, the conductive pattern may have a shape as the recognition mark or the through hole may have the shape as the recognition mark.

Abstract: A process for making a circuit board comprises the following steps of: half-etching a metal layer formed on an insulating substrate by means of a first masking which is positioned on an upper surface of the metal layer; applying a positive liquid resist on the half-etched metal layer from an upper side of the first masking; exposing the positive liquid resist with parallel light from the upper side of the first masking and developing the positive liquid resist in such a manner that a part of the positive liquid resist located under the first masking is protected to be unexposed and undeveloped; etching again the metal layer by means of a second masking composed of the first masking and the protected positive liquid resist to form a conductive pattern on the insulating substrate; and removing the first masking and the second masking from the metal layer.

Abstract: The present invention relates to a method for fabricating a wiring substrate by forming an insulating film on a metal base having openings on the metal base at positions corresponding to metal bumps to be formed later; forming at least one layer of wiring on the base made of a metal through the insulating film, the layer of wiring having a wring film formed thereon by electroplating; and selectively etching the base. The insulating film can be a liquid photosensitive polyamide, the wiring layer can be copper and the wiring film can be a conductive layer selected from the group consisting of Ni-P and Ni. In the present invention, the wiring layer can be formed through the insulating film in contact with the metal base at the openings in the insulating film and in contact with the insulating film where there are no openings in the insulating film.

Abstract: A process facilitates manufacturing a multiple layer wiring board having therein a thin-film capacitor The process includes: forming a metallic film layer having a barrier metal layer and a metal layer to be sequentially anode oxidized on an insulating layer first conductor pattern; covering a lower electrode forming region of the thin film capacitor in the first conductor pattern with a first resist film; etching to remove an uncovered portion of the metallic film layer; removing the first resist film and covering the first conductor pattern, except for part of the metallic film layer, with a second resist film; forming an anodic oxidation film on the exposed metallic film layer; removing the second resist film and attaching an adherence layer and a metal seed layer, sequentially, on the anodic oxidation film end on the first conductor pattern; and forming an upper electrode second conductor pattern on the anodic oxidation film.

Abstract: A multi-step etching process for a lead overlay structure such as a thin-film magnetic head structure using secondary ion mass spectroscopy (SIMS) whereby high selectivity of a lead material or other high conductivity metal layer is realized versus that of a metallic mask material and stopping layer. The first step includes patterning the mask layer using IBE or RIE. Advantageously, a photoresist layer is present over a portion of the mask layer and is left in place to be removed in a subsequent step. The second step includes etching the high conductivity metal layer using CAIBE or RIBE with an inert/reactive gas mixture and using SIMS to detect when the stopping layer is reached.

Abstract: Embedded flush circuitry features are provided by depositing a conductive seed layer on the front side of a sacrificial carrier; plating a layer of conductive metal onto the seed layer and personalizing circuitry features. The front side of the carrier film is embedded into a dielectric material and the sacrificial carrier film is removed.

Abstract: A connection component for making microelectronic assemblies includes a dielectric structural layer having a first surface and a plurality of conductive leads having first and second ends overlying the first surface of the dielectric structural layer. An adhesive is provided between the second ends of the leads and the dielectric structural layer such that the adhesive forms connections between the second ends of the leads and the structural layer. The formed connections have areas smaller than the areas of the second ends. The second ends of the leads are releasably attached to the structural layer by the connections. Thus, the second ends of the leads may be engaged with features on a microelectronic device and the microelectronic elements may be moved away from the structural layer so as to bend the second ends of the leads away from the structural layer.

Abstract: A method is provided for reconstructing an integrated circuit package comprising: attaching a die to exposed wire bond pads of a lead frame so that the die is electrically connected to the lead frame; and encapsulating the die and the wire bond pads in an encapsulant; and reshaping an upper surface of the encapsulant where at least a portion of the encapsulant reshaping is performed by a lapping process.

Abstract: A leadless plastic chip carrier comprising a die attach pad, a semiconductor die mounted to a portion of the die attach pad and at least one row of contact pads circumscribing the die attach pad. The row of contact pads have a thickness greater than the thickness of the portion of the die attach pad. A plurality of wire bonds connect the die attach pad and the contact pads. An overmold covers the semiconductor die and all except one surface of the at least one row of contact pads and the die attach pad.

Abstract: A metal layer, an etching resist and a photoresist are successively applied to an electrically insulating substrate. Whereupon the photoresist is patterned by photolithography in such a way that it covers a pattern of the later coarse conductor structures and the entire region of the later fine conductor structures. After the uncovered etching resist has been stripped, the photoresist is removed, whereupon the etching resist is patterned with the aid of a laser beam in such a way that it has the pattern of the fine conductor structures. The coarse conductor structures and the fine conductor structures are then formed in a common etching process.

Abstract: A semiconductor packaging part and a method of forming the part by applying a minute plating with a high positional accuracy to a semiconductor chip to be packaged. A pair of alignment holes 2, 3 are formed at a pitch equal to n-times (n=1, 2 . . .

Abstract: A gimbal formed integral with a load beam by through etching a H pattern at the end of the beam to define a pair of tabs connected by a pair of beams; half etching from the head direction one tab with an defined area masked to form a load button; and half etching the beam from the other direction to provide the proper gimbal stiffness. In practice, the head is glued to the other tab and load is applied through the button.

Abstract: A printed wiring board having a conductor pattern on which a pre-flux film of a stabilized quality is to be formed using a water-soluble pre-flux liquid. To this end, such an apparatus is used which includes an etching unit 12 for etching lands 5b, 6b formed on the printed wiring board 1, a rinsing unit 13 for rinsing the printed wiring board 1, a bubble removing unit 14 for removing air bubbles 58 attached to the printed wiring board 1 on immersing the printed wiring board 1 in a water-soluble pre-flux liquid 9a in a processing vessel 56, a pre-flux forming unit 15 for forming a pre-flux film 9 on the lands 5b, 6b of the printed wiring board 1 in the pre-flux liquid 9a using an in-liquid spraying unit 61, a liquid removing unit 16 for removing the pre-flux liquid 9a from the printed wiring board 1 transported from the processing vessel 56 and a rinsing unit 17 for rinsing the printed wiring board 1.

Abstract: A method of making a connection component for a microelectronic element includes providing a sheet comprising an electrically conductive layer, a photoresist layer overlying the conductive layer and a photoimageable dielectric layer disposed under the conductive layer. The method includes lithographically forming at least one opening in the photoresist layer to uncover a portion of the conductive layer, forming a plurality of circuit features from the conductive layer by removing the uncovered portion of the conductive layer, at least some of the circuit features being leads, and lithographically forming at least one aperture in the photoimageable dielectric layer.

Abstract: A leadless integrated circuit package, comprising an exposed semiconductor die and contact pads embedded in an over mold, and wires interconnecting the semiconductor die and contact pads.

Abstract: A method of manufacturing electronic components includes disposing a top metal layer (502) comprised of solder over a bottom metal layer (201, 202) comprised of titanium or tungsten, and selectively etching the bottom metal layer (201, 202) over the top metal layer (502) with an etchant mixture (601) comprised of an etchant, an additive to control the temperature of the etchant mixture (601), and another additive to reduce the redeposition of the top layer (502).

Abstract: According a method of manufacturing a lead frame of the present invention, a plurality of leads each having an inner lead portion and an outer lead portion are formed on a metal base having on its surface a nickel layer by copper plating. An insulative holding film for holding each of the leads is formed. A projecting electrode is formed on the outer lead portion. Respective leads are separated by selectively removing the metal base by etching.

Abstract: A method for contacting at least one printed circuit board or at least one punched grid and at least one hybrid includes the steps of: forming contact elements in a contacting foil, positioning the contacting foil over the hybrid in such a way that the contact elements are arranged at preselected positions between the printed circuit traces of the hybrid and the printed circuit traces of the printed circuit board, and etching away at least a portion of the contacting foil, such that the contact elements are at least partially freely accessible.

Abstract: A package for a microelectronic element is made by making a microelectronic component, including embossing a metal sheet to form thin and thick regions, then etching or otherwise removing metal from the sheet in a nonselective removal process and arresting the removal process when the thin regions are removed but before the thick regions are removed. A base material may be applied to the metal sheet to form a dielectric layer for the component. The component is assembled with a microelectronic element to form the package.

Abstract: A process for producing lead frames having lead tips with a minimum of side etching includes the steps of coating a metal lead frame substrate with a first photosensitive film, patterning the first photosensitive film, developing the patterned first photosensitive film, partially etching the metal surface of the lead-frame substrate beneath the developed patterned first photosensitive film, coating the partially etched metal surface with a positive second photosensitive, exposing the positive second photosensitive film to light passing through the developed first photosensitive film, developing the exposed second photosensitive film, performing fine etching through the developed second photosensitive film to a desired depth at least once, and removing the first and second photosensitive films.

Abstract: Metallic elements such as leads for connection to a semiconductor chip are made by embossing a metal sheet to form thin and thick regions, then etching or otherwise removing metal from the sheet in a nonselective removal process and arresting the removal process when the thin regions are removed but before the thick regions are removed. A base material may be applied to the metal sheet to form a dielectric layer before the removal step, so that the metallic leads left after the removal step are supported by the dielectric layer.

Abstract: Interconnection elements for electronic components, exhibiting desirable mechanical characteristics (such as resiliency, for making pressure contacts) are formed by shaping an elongate element (core) of a soft material (such as gold) to have a springable shape (including cantilever beam, S-shape, U-shape), and overcoating the shaped elongate element with a hard material (such as nickel and its alloys), to impart a desired spring (resilient) characteristic to the resulting composite interconnection element. A final overcoat of a material having superior electrical qualities (e.g., electrical conductivity and/or solderability) may be applied to the composite interconnection element. The elongate element may be formed from a wire, or from a sheet (e.g., metal foil).

Abstract: The purpose of this invention is to provide a type of carrier tape with inner leads arranged at small pitches.When first wirings 11, second wirings 12, and pitch-converting wirings 14 are formed by etching resin film 8, second wirings 12 and pitch-converting wirings 14 become thinner than first wirings 11. First wirings 11 are formed on film tape 3, and second wirings 12 are formed in hole 15 formed on the aforementioned film tape. Also, pitch-converting wirings 14 are formed on resin film 9 formed in said hole 15. In this way, second wirings 12 arranged at small pitches and first wirings 11 arranged at large pitches can be connected to each other by pitch-converting wirings 14 without creating any short circuit. First wirings 11 can be used for connection to a liquid crystal panel, and second wirings 12 can be used for connection to semiconductor elements.

Abstract: A bonding component for electrically connecting a semiconductor chip or wafer to a support substrate includes a dielectric layer having a central region, elongated slots defining the central region, and a peripheral region surrounding the slots. Metallic bonding pads are arranged on the central region, and leads extend from the bonding pads to the edge of the central region and extending partially across the elongated slots. The leads are detached from the peripheral region of the dielectric layer on the side of the slots opposite the central region. The leads are adapted to be deformed during bonding to a semiconductor chip or wafer. To form the bonding component, a dielectric layer is first provided having a central region, slots and a peripheral region. A metallic structure is also provided having bonding pads on the central region, and leads electrically connected to the bonding pads and to a plating bus disposed in the peripheral region.

Abstract: A method of forming a conductive network, having relatively flexible electrical conductor areas integral with relatively rigid electrically conductor areas including (a) providing a relatively rigid laminate having a dielectric lamina supporting, at least in part, a first electrically conductive lamina which is in electrically conductive intimate contact with a second electrically conductive lamina by way of an electrically conductive barrier layer, the first and second conductive laminae being of a material etchable by an etchant which is not an etchant for the barrier layer; (b) selectively etching desired portions of the aid second electrically conductive lamina to the barrier layer in at least the relatively flexible areas using the etchant; and (c) selectively etching desired exposed metallic portions of the laminate down to the dielectric lamina to form the conductive network using an etchant, the etchant chosen to etch both the conductive lamina and the barrier layer.

Abstract: A lead frame etching method, which is used for a semiconductor device assembling process and prevents a sharp-edged portion formed on each lateral end of a lead frame material. The method includes the steps of forming a first photoresist pattern defining the actual etching region, on both surfaces of a lead frame material, forming a second photoresist pattern as an etching buffer extending from lateral ends of the first photoresist pattern, on both surfaces of the lead frame material on which the first photoresist pattern is formed, etching the lead frame material using the second photoresist pattern as an etching mask, removing the second photoresist pattern from the etched lead frame material, etching the lead frame material using the first photoresist pattern as an etching mask, and removing the first photoresist pattern from the twice-etched lead frame material.