Abstract: A bi-layer bump comprises a base layer composed of sprayed aluminum thick film having a thickness of about 20 .mu.m formed to cover the periphery of the passivation film formed on each pad electrode, a surface layer composed of sprayed copper thick film having a thickness of about 30 .mu.m formed on the base layer. According to the above-mentioned structure, a substrate on which bumps are formed which has an excellent electric property and connecting reliability, wherein an interlayer insulating layer, an active layer and a multi-layer wiring can be provided under the pad electrode can be obtained.

Abstract: Leads are formed on a surface of an etching stop film of a base, and holes are defined in the base and a region of a substrate which corresponds to a lead-forming region is thinned by selective etching on both upper and lower surfaces of the base. A lead holder film having a device hole and an outer lead bonding slit is applied to the upper surface of the base. The thinned region of the substrate is removed by selective etching on the lower surface of the base, and the etching stop film is etched away.

Abstract: A method of manufacturing a double-sided circuit tape carrier comprising an insulating film like a polyimide tape, circuit wiring patterns on both sides thereof, and via holes through which at least a part of the circuit wiring patterns on both sides are electrically connected with each other. A copper thin film is patterned by photoetching. Via holes are formed through the insulating film by irradiating a laser beam by using the patterned copper thin film as a mask. Then, a conductive layer of a graphite conductive thin film and a copper plating layer is formed. The copper thin film is patterned by photoetching forming a chip hole and an outer lead hole through the insulating film by irradiating a laser beam. Finally, one of the copper thin films is patterned by photoetching to form circuit wiring pattern.

Abstract: A polymeric organic coating (24) used to package a semiconductor component (10) increases voltage isolation, decreases thermal resistance, and increases scratch and abrasion resistance for the semiconductor component (10). The coating (24) is applied to a leadframe (14) of the semiconductor component (10) using a chemical grafting process that involves the use of monomers, prepolymers, a catalyst, a graft initiator, and other ingredients. The coating (24) forms a polymeric organic film that is chemically bonded to the surfaces of the leadframe (14). The chemical grafting process produces a chemical bond, which improves adhesion between the coating (24) and the leadframe (14).

Abstract: A substantially continuous layer of a first metal such as copper is provided with strips of a second metal such as gold by selective electroplating of the second metal. A dielectric support layer is provided in contact with the first metal layer, and the first metal layer is etched to leave strips of the first metal contiguous with the strips of the second metal, thereby providing composite leads with the first and second metal strips connected in series. The process provides simple end economical methods of making microelectronic connection components with leads having a flexible, fatigue resistant lead potion formed from a precious metal.

Abstract: A micro-dimensional coupling conductor with a shape that is customized for a particular electronic device. A fabrication method is used in which the physical dimensions of the conductor are precisely controlled with photolithographic techniques, resulting in a conductor that is more precisely tuned to the operating frequency of the device. The conductor is fabricated on an SiO.sub.2 substrate using vacuum deposition or electroplating techniques. After fabrication, the conductor is separated from the SiO.sub.2 substrate by dissolving the SiO.sub.2. Alternatively, the conductor may be fabricated on a Teflon.TM. substrate. The use of a Teflon substrate allows a user to remove the conductor from the substrate by applying a small mechanical force to the conductor.

Abstract: One or two, or more, additional conductive layers, separated from one another (if two or more) and separated from a patterned (signal) conductive layer are formed in a flexible substrate, for mounting a semiconductor die in a semiconductor device assembly. These additional layers are used as separate planes for carrying power and/or ground from outside the assembly to the die, on a separate plane from signals entering or exiting the die. TAB processes are disclosed for cutting, bending and bonding inner and outer portions of selected signal layer traces to respective inner and outer edge portions of the additional conductive layer(s), including a two-stage process of (1) first cutting, bending and tacking the selected traces to the additional layer(s), and then (2) repositioning a bonding tool and securely bonding the selected traces to the additional layer(s). A tool (die pedestal) for aiding in the assembly process is also disclosed.

Abstract: A lead frame includes a plurality of inner leads, each of the inner leads having at least one surface defining a bonding area and two opposed side edges. The tip ends of the plurality of inner leads are connected by a connecting part so that the inner leads are arranged side by side with respect to each other. The connecting part is integrally and simultaneously formed with the inner leads by an etching process. Each of the inner leads has recesses on the two side edges at a position, between the bonding area and the connecting part, on a cutting line along which the plurality of inner leads are to be cut and separated into individual inner leads.

Abstract: A semiconductor chip connection component having numerous leads extending side-by-side across a gap in a support structure, each lead having a frangible section to permit detachment of one end of the lead from the support structure in a bonding process. The frangible sections are formed by treating the lead-forming material in an elongated treatment zone extending across the regions occupied by numerous leads. The process avoids the need for especially fine etching to form notches in the lateral edges of the leads.

Abstract: A semi-conductor device having a conductive lead with an exposed tip disposed within a first insulative material, which is in turn disposed between insulated first and second integrated circuit chips is disclosed. The first insulative material is etched to form a recess after which a second insulative material is deposited on the access plane of the chips and within the recess. The tip of the wire lead is then exposed by either a chemical mechanical polish or by a wet etch/develop process.

Abstract: A method for providing a flexible lead for a microelectronic device. A lead such as nickel or a nickel alloy is provided in elongated strips on a base material such as copper, which in turn overlies a dielectric sheet. The base material is etched from beneath bond regions of the lead material strips and a cover layer of a bondable material such as gold selectively provided around the lead material strips. The lead material strips act as plating mandrels, and allow rapid deposition of the cover material. A detachment area may be provided in each lead so that the leads may be detached and displaced within a bonding window in the dielectric sheet for attachment to chip contacts.

Abstract: In a method for forming a lead frame (1) from a metallic plate, a metallic plate (11) is first etched to form outer leads (4) and outer portions (3b) of inner leads of the lead frame (1). Inner portions (3a) of the inner leads (3) are then laser-cut under the condition that a joint portion (7) is left so as to interconnect the inner leads (3) at their distal ends. Mechanical surface treatment and chemical surface treatment are then carried out to remove dross (10), spatters (9) and oxide films deposited during the laser cutting. Inner areas of the inner leads (3) connected to respective terminals of a semiconductor chip are then plated with gold to form plated terminal portions (3A). Subsequently, the region of the lead frame other than the outer leads (4) is coated with a protective film for solder plating and the outer leads (4) are plated with solder.

Abstract: This is a system and method of fabricating hybrid integrated circuits (IC). The method may comprise: forming internal IC structures on a substrate; forming IC interlevel insulation on top of the internal IC structures; forming IC top level metal connections on top of the IC interlevel insulation; depositing a protective overcoat over the IC top level metal and the IC interlevel insulation; depositing a dry etch protective layer over the protective overcoat; and dry etching the etch protective layer and the protective overcoat to expose portions of the IC top level metal. The deposition of the protective overcoat may include depositing silicon dioxide or silicon nitride. In addition, the deposition of the dry etch protective layer may include depositing a photosensitive polymide layer. Furthermore, the dry etching may include photolithography.

Abstract: Disclosed herein is a manufacturing method for a lead frame, including the steps of forming a lead element, forming masks on a first surface and a second surface of the lead element, etching the lead element, and removing the masks. According to this method, the lead frame can be manufactured at low costs without the necessity of machining of the lead element.

Abstract: A lead frame capable of easily connecting an inner lead to an electrode of a semiconductor element by way of a bump of the inner lead, and a method of manufacturing the lead frame capable of significantly easily forming the bump. A bump forming metal layer is formed on a metal base sheet on an area where each inner lead is to be formed. The inner lead is formed on the bump forming metal layer, and the bump forming metal layer is etched using the inner lead as a mask, thus forming a bump. After that, each outer lead is formed by selective etching of the metal base sheet from the rear surface side.

Abstract: An inner lead of a lead frame has an outer end portion extending so as to be connected with a side surface of an etching stop layer and with an upper surface of an outer lead. The outer lead is formed by etching both surfaces of a metal base, and the inner lead is formed by plating metal on the metal base with a resist layer used as a mask. The pitch of the outer lead can be made fine, and a bonding strength of the inner lead to the outer lead can be increased.