Adhesive Or Autogenous Bonding Of Self-sustaining Preforms (e.g., Prefabricated Base, Etc.) Patents (Class 216/20)
  • Patent number: 10741476
    Abstract: A passive electrical component includes a substrate. A first metallization layer is formed on the substrate. A first dielectric layer is formed on the first metallization layer The first dielectric layer has a lower thermal conductivity than the substrate. A second metallization layer is formed on the first dielectric layer. An electrically conductive via provides an electrical connection between a first section of the first metallization layer and a second section of the second metallization layer. A thermally conductive via provides a thermally conductive path between the second section and the substrate. The thermally conductive via provides an open circuit termination to the second section of the second metallization layer.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: August 11, 2020
    Assignee: Infineon Technologies AG
    Inventors: Christian Schuberth, David Seebacher
  • Patent number: 10705424
    Abstract: A composition crosslinkable by broad band UV radiation, which after cross-linking is capable of cold ablation by a UV Excimer Laser emitting between 222 nm and 308 nm, where the composition is comprised of a negative tone resist developable in aqueous base comprising and is also comprised of a conjugated aryl additive absorbing ultraviolet radiation strongly in a range between from about 220 nm to about 310 nm. The present invention also encompasses a process comprising steps a), b) and c) a) coating the composition of claim 1 on a substrate; b) cross-linking the entire coating by irradiation with broadband UV exposure; c) forming a pattern in the cross-linked coating by cold laser ablating with a UV excimer laser emitting between 222 nm and 308 nm.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: July 7, 2020
    Assignee: Merck Patent GmbH
    Inventors: Chunwei Chen, Weihong Liu, Ping-Hung Lu
  • Patent number: 10651032
    Abstract: The present invention relates to the controlling of the deposition quality of an epitaxial layer, for example of gallium nitride, on a growth plate, for example of silicon, in particular at the level of the edges of the plate. The invention aims, in particular, to reduce the complexity and the production cost of known solutions. The production method according to the invention highlights the existence of a chamfer on each growth plate and provides a self-positioned deposition of a protective film on at least one part of the chamfer using a mechanical mask, preventing the deposition of the protective film on the useful zone Zu through epitaxy.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: May 12, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Hubert Moriceau, Matthew Charles, Christophe Morales
  • Patent number: 10587060
    Abstract: Printed circuit board (PCB), electrical structures including PCBs, and methods for making the same. One PCB structures includes: a substrate having a plurality of surfaces, including a first aerial main face (AMF), a second AMF, and a first peripheral end face (PEF), wherein the first PEF separates the first AMF from the second AMF, and a first plurality of contacts embedded in the first PEF, where each of the first plurality of contacts forms a contiguous contact with the first PEF and at least one of i) the second AMF, ii) the first AMF, and iii) another one of the plurality of surfaces.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Todd E. Takken, Xin Zhang, Yuan Yao, Andrew Ferencz, Paul W. Coteus
  • Patent number: 10575411
    Abstract: According to one aspect, the invention provides a method of providing conductive structures between two foils in a multi-foil system. The system comprises at least two foils, from which at least one foil comprises a terminal. The method comprises the steps of (in any order) providing at least one solid state adhesive layer, patterning adhesive layer with through-holes; filling the through-holes with conductive material, so as to form the conductive structure, connected to the terminal; and bonding the at least two foils. One advantage of the invention is that it may be used in a manufacturing process for multi-foil systems.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: February 25, 2020
    Assignee: Nederlandse Organisatie voor toegepast-natuurwetenschappelijk onderzoek TNO
    Inventors: Andreas Heinrich Dietzel, Jeroen van den Brand
  • Patent number: 10499512
    Abstract: A multi-layer circuit board including a plurality of insulation bumps, a first conductive layer, and a second conductive layer is provided. The plurality of insulation bumps are disposed between a first substrate and a second substrate. A top portion of the plurality of insulation bumps is served as a circuit connection point. The first conductive layer is disposed on the first substrate and connected to the circuit connection point. The second conductive layer is disposed on the second substrate and connected to the circuit connection point.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: December 3, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Yu-Ming Chen
  • Patent number: 10444477
    Abstract: The wafer stack (100) comprises a first wafer (OW1) referred to as optics wafer and a second wafer (SW) referred to as spacer wafer, said optics wafer (OW1) having manufacturing irregularities. The spacer wafer (SW) is structured such that it at least partially compensates for said manufacturing irregularities. The corresponding method for manufacturing a device, which in particular can be an optical device, comprises carrying out a correction step for at least partially compensating for manufacturing irregularities. Such a correction step comprises providing a wafer (SW) referred to as spacer wafer, wherein that spacer wafer is structured for at least partially compensating for said manufacturing irregularities. Those manufacturing irregularities may comprise a deviation from a nominal value, e.g., a irregularities in focal length. The invention can allow to mass produce high-precision devices at a high yield.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: October 15, 2019
    Assignee: AMS SENSORS SINGAPORE PTE. LTD.
    Inventors: Hartmut Rudmann, Matthias Maluck, Alexander Bietsch, Peter Roentgen, Stephan Heimgartner
  • Patent number: 10357951
    Abstract: A laminating apparatus includes a first jig having at least one recessed portion, a second jig disposed opposite to the first jig, a step difference portion disposed on the second jig, an elastic sheet disposed on each of the second jig and the step difference portion, and a guide portion spaced apart from the step difference portion and overlapping an edge of the elastic sheet. A width of the step difference portion is greater than a width of the recessed portion of the first jig.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: July 23, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Soochan Lee, Hirokazu Ishii, Katsuhiko Tanaka, Jeonghun Heo
  • Patent number: 10291202
    Abstract: A vibration device that includes a support member, vibration arms connected to the support member and each having an n-type Si layer which is a degenerate semiconductor, and electrodes provided so as to excite the vibration arms, and silicon oxide films containing impurities in contact with a respective lower surface of the n-type Si layers of each vibration arm.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: May 14, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hiroshi Yamada, Keiichi Umeda, Takehiko Kishi, Toshio Nishimura
  • Patent number: 10192646
    Abstract: A radiation shielding system for an x-ray digital detector array includes a first radiation shield having a plurality of shielding pads and a plurality of interstices between the plurality of shielding pads, the plurality of shielding pads having a greater thickness than the thickness of the plurality of interstices. The plurality of shielding pads is configured to be positioned over active components of the x-ray digital detector array and the interstices are configured to be positioned over passive components of the x-ray digital detector array.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: January 29, 2019
    Assignee: General Electric Company
    Inventors: Susanne Madeline Lee, Douglas Albagli, James Michael Gent, Kevin Edward Kinsey
  • Patent number: 10164167
    Abstract: A method for producing an electric component (19) is specified, wherein in a step A) a body (1) having at least one cavity (7, 8) is provided. In a step B), the cavity (7, 8) is at least partly filled with a liquid insulation material (13) by means of capillary forces. Furthermore, an electric component (19) is specified wherein a cavity (7, 8) is at least partly filled with an insulation material (13). The insulation material (13) is introduced into the cavity (7, 8) by means of capillary forces. Furthermore, an electric component (19) is specified wherein a cavity (7, 8) is at least partly filled with an organic insulation material (13) and wherein the cavity is at least partly covered by a fired external contacting (17, 18).
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: December 25, 2018
    Assignee: EPCOS AG
    Inventors: Franz Rinner, Dieter Somitsch
  • Patent number: 10117336
    Abstract: A wiring substrate includes an insulating layer, a connection pad buried in the insulating layer in a state that an upper surface of the connection pad is exposed from an upper surface of the insulating layer and a lower surface and at least a part of a side surface of the connection pad contact the insulating layer, and a concave level difference portion formed in the insulating layer around an outer periphery part of the connection pad, wherein an upper surface of the connection pad and an upper surface of the insulating layer are arranged at a same height.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: October 30, 2018
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Kentaro Kaneko, Toshimitsu Omiya, Kotaro Kodani, Junichi Nakamura, Kazuhiro Kobayashi
  • Patent number: 10067270
    Abstract: The present invention relates to an electromagnetic wave absorbing/radiating material which includes: a conductor; and a plurality of conductor discs disposed in an array above the surface of the conductor or a perforated conductor layer with a plurality of holes defined in an array above the surface of the conductor.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: September 4, 2018
    Assignee: NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Tadaaki Nagao, Thang Duy Dao, Takahiro Yokoyama, Satoshi Ishii
  • Patent number: 9982333
    Abstract: A mask frame assembly for manufacturing a display device, and a method of manufacturing the mask frame assembly are disclosed. In one aspect, the mask frame assembly includes a frame having at least one opening portion defined therein. The mask frame assembly further includes a polymer film having a plurality of slits defined therein and combined to the frame. In another aspect, the method includes coating a polymer solution on a glass and drying and hardening the polymer solution so as to form a polymer film. The method also includes combining a frame to the polymer film, desorbing the glass from the polymer film and processing a plurality of slits on the polymer film.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: May 29, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kie Hyun Nam, Hye Dong Kim, Sung Guk An
  • Patent number: 9930815
    Abstract: The present disclosure relates to a layered structure of a multi-layer PCB, and more particularly, to a structure of a high-power multi-layer PCB which can use a high current by efficiently dissipating heat generated from the inside of the multi-layered PCB and heat generated from a power semiconductor module package mounted on the PCB, and a production method thereof. The multi-layer PCB includes: a conductive plate having a plurality of heat poles protruding from at least one of a top surface and a bottom surface thereof; PCBs which are disposed on the top surface and the bottom surface of the conductive plate, and have a plurality of penetrating holes formed therethrough to allow the heat poles of the conductive plate to be inserted thereinto; and an insulation layer which is attached between the conductive plate and the PCBs in order to electrically insulate.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: March 27, 2018
    Assignee: MDM Inc.
    Inventor: Ku Yong Kim
  • Patent number: 9889653
    Abstract: A nanoprinthead including an array of nanotip cantilevers, where each nanotip cantilever includes a nanotip at an end of a cantilever, and a method for forming the nanoprinthead. Each nanotip may be individually addressable through use of an array of piezoelectric actuators. Embodiments for forming a nanoprinthead including an array of nanotip cantilevers can include an etching process from a material such as a silicon wafer, or the formation of a metal or dielectric nanotip cantilever over a substrate. The nanoprinthead may operate to provide uses for technologies such as dip-pen nanolithography, nanomachining, and nanoscratching, among others.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: February 13, 2018
    Assignee: XEROX CORPORATION
    Inventors: Peter J. Nystrom, Andrew W. Hays, Bijoyraj Sahu
  • Patent number: 9891775
    Abstract: Disclosed herein is a touch-sensitive display device comprising: a first set of metal electrodes including a first metal electrode; a second set of metal electrodes including a second metal electrode and a third metal electrode, the first metal electrode located between the second metal electrode and the third metal electrode such that the second metal electrode is physically separated from the third metal electrode; a first set of touch electrodes including a first touch electrode that is connected to the first metal electrode; a second set of touch electrodes including a second touch electrode and a third touch electrode, the second touch electrode connected to the second metal electrode and the third touch electrode connected to the third metal electrode; an insulation film having a plurality of contact holes; and a connection electrode electrically connecting the second metal electrode to the third metal electrode through the plurality of contact holes.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: February 13, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Sejong Yoo, NackBong Choi, YongChul Kim, Jonghyun Han, Haeyeon Jeong
  • Patent number: 9864474
    Abstract: A contact hole that penetrates a protective insulating film, an interlayer insulating film, and a transparent cap film and has a surface of a low-reflection film uncovered as a bottom surface is formed in a lead-out wiring region. A lower-layer terminal portion is formed by the low-reflection film and a low-resistance conductive film below the bottom surface of the contact hole. A contact hole that penetrates the protective insulating film and a transparent cap film and has a surface of a low-reflection film uncovered as a bottom surface is formed in the lead-out wiring region. An upper-layer terminal portion is formed by the low-reflection film and a low-resistance conductive film below the bottom surface of the contact hole.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: January 9, 2018
    Assignee: Mitsuibishi Electric Corporation
    Inventors: Masami Hayashi, Masaru Aoki
  • Patent number: 9804498
    Abstract: A photoresist stripping tool includes a reservoir configured to contain photoresist stripping solution and a Pb filter comprising a filter element with Tin (Sn) exterior surfaces. A semiconductor wafer fabrication system includes a semiconductor wafer attached to the photoresist stripping tool that strips photoresist from the semiconductor wafer. A photoresist stripping processes includes stripping photoresist from a leaded semiconductor wafer with photoresist stripping solution within the photoresist stripping tool, filtering Lead Pb from the photoresist stripping solution with the Pb filter, and stripping photoresist from a lead-free semiconductor wafer with the filtered photoresist stripping solution.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: October 31, 2017
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Harry D. Cox, Arthur G. Merryman, Jennifer D. Schuler
  • Patent number: 9790586
    Abstract: A mask frame assembly includes a frame, and a mask tensioned on the frame in a first direction, the mask having a deposition pattern portion having a plurality of pattern holes therethrough, a deposition material being deposited on a substrate through the pattern holes, and a dummy portion extending from the deposition pattern portion in the first direction, the dummy portion having an increased thickness in a second direction as a distance from the deposition pattern portion in the first direction increases, the second direction being oriented along a normal to the mask.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: October 17, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Junhyeuk Ko, Daewon Baek, Eunji Lee
  • Patent number: 9738782
    Abstract: An epoxy resin composition containing an epoxy resin [A1], epoxy resin [B1], epoxy resin [C1] and curing agent [D] wherein [A1] is a bisphenol-type epoxy resin with a softening point of 90° C. or more, [B1] is a tri- or higher functional amine-type epoxy resin, [C1] is a bisphenol F-type epoxy resin with a number average molecular weight of 450 or less, and the epoxy resins [A1] to [C1] satisfy the following contents per 100 parts by mass of total epoxy resin content: [A1] 20 to 50 parts by mass, [B1] 30 to 50 parts by mass and [C1] 10 to 40 parts. The present invention provides low-viscosity epoxy resin compositions that are excellent in impregnating reinforcing fibers and capable of producing cured resins with excellent modulus and toughness, as well as prepregs and fiber-reinforced composite materials based on those epoxy resin compositions.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: August 22, 2017
    Assignee: TORAY INDUSTRIES, INC.
    Inventors: Mami Hayashi, Takayuki Fujiwara, Jun Misumi, Kenichi Yoshioka
  • Patent number: 9691965
    Abstract: A method is provided for making electrical contact with an electronic component in the form of a stack formed from a plurality of material layers, which react upon application of an electric field, and a plurality of electrode layers, wherein each material layer is arranged between two of the electrode layers. An insulation structure is generated on at least one stack circumferential region of the stack, which exposes each second electrode layer of the at least one stack circumferential region for electrical contact to be made. Also, a contact-making structure is applied to the at least one stack circumferential region which is provided with the insulation structure. Before the step of generating the contact-making structure, the material layers are partially removed by a material-removing method such that the electrode layers are exposed close to the surface.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: June 27, 2017
    Assignee: CONTINENTAL AUTOMOTIVE GMBH
    Inventors: Thomas Richter, Andreas Lenk, Claus Zumstrull
  • Patent number: 9679881
    Abstract: A semiconductor wafer has a plurality of first semiconductor die with a stress sensitive region. A masking layer or screen is disposed over the stress sensitive region. An underfill material is deposited over the wafer. The masking layer or screen prevents formation of the underfill material adjacent to the sensitive region. The masking layer or screen is removed leaving a cavity in the underfill material adjacent to the sensitive region. The semiconductor wafer is singulated into the first die. The first die can be mounted to a build-up interconnect structure or to a second semiconductor die with the cavity separating the sensitive region and build-up interconnect structure or second die. A bond wire is formed between the first and second die and an encapsulant is deposited over the first and second die and bond wire. A conductive via can be formed through the first or second die.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: June 13, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Reza A. Pagaila, Byung Tai Do, Linda Pei Ee Chua
  • Patent number: 9666837
    Abstract: A mask for deposition includes a plurality of deposition pattern parts arranged spaced apart from each other in a first direction, and a plurality of pattern openings defined in each deposition pattern part; a plurality of dummy pattern parts disposed at opposing sides of the plurality of deposition pattern parts in the first direction, respectively, and a plurality of recesses defined in each dummy pattern part; and a plurality of fixing parts respectively disposed at external sides of outermost dummy pattern parts among the plurality of dummy pattern parts, in the first direction. A maximum thickness of the each dummy pattern part is equal to or larger than a maximum thickness of the each deposition pattern part, and is smaller than a maximum thickness of each fixing part.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: May 30, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD
    Inventor: Sang Yun Lee
  • Patent number: 9570715
    Abstract: A mask supported at a frame when a tensile force is applied in a first direction is provided. The mask includes a mask main body in a band shape extended in the first direction, and a plurality of pattern openings formed in the mask main body. the mask main body has ends supported by the frame, and the pattern opening are arranged in the first direction. The mask further includes a dummy opening provided between the pattern openings and one of the ends of the mask main body. The dummy opening has a form that is different from forms of the pattern openings.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: February 14, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Taek-Kyo Kang
  • Patent number: 9532465
    Abstract: The invention provides a method of fabricating an interconnect comprising aligning and stacking a plurality of printed circuit boards with at least one adhesive component, laminating the printed circuit boards and the adhesive component, preparing bonded pair holes, depositing a copper seed layer, forming a copper plate image, electroplating a copper layer, removing a plate resist and depositing an insulator layer.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: December 27, 2016
    Inventors: John Vesce, Joseph William Heery, Jr.
  • Patent number: 9457541
    Abstract: A copper foil for a current collector of a lithium secondary battery has a crystalline structure, in which a ratio of the sum of texture coefficients of a (111) surface and a (200) surface to the total sum of texture coefficients of the (111), (200) and (220) surfaces is 60 to 85%, a ratio of the texture coefficient of the (111) surface to the total sum of texture coefficients of the (111), (200) and (220) is 18 to 38%, a ratio of the texture coefficient of the (200) surface thereto is 28 to 62%, and a ratio of the texture coefficient of the (220) surface thereto is 15 to 40%. The copper foil has surface roughness (Rz-JIS) of 2 ?m or less, weight deviation of 3% or less, tensile strength of 30 to 40 kgf/mm2, elongation of 3 to 20%, and thickness of 1 to 35 ?m.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: October 4, 2016
    Assignee: LS MTRON LTD.
    Inventors: Dae-Young Kim, Byoung-Kwang Lee, Seung-Jun Choi
  • Patent number: 9435970
    Abstract: An optical connector is provided. The optical connector includes: an optical fiber line fixing block including an insertion groove in which an end portion of an optical fiber line is inserted; and a submount including first guide-walls determining a position of the optical fiber line fixing block and second guide-walls determining a position of an optical device to be connected to the optical fiber line, wherein the optical fiber line fixing block and the optical device are automatically aligned by the first guide-walls and the second guide-walls.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: September 6, 2016
    Assignee: Optics Co., Ltd.
    Inventors: Hee Dae Kim, Hyun Sik Lee
  • Patent number: 9420699
    Abstract: A non-deleterious method for producing a continuous conductive circuit upon a non-conductive substrate can begin with the application of a metallic base layer upon a surface of a non-conductive substrate. A circuit pattern can be created within the metallic base layer based upon a circuit design. The metallic base layer comprising the circuit pattern can be physically separated from the remainder of the metallic base layer on the non-conductive substrate. The region of the non-conductive substrate surface that encloses the circuit pattern can be called the plating region. The remainder of the non-conductive substrate surface can be called the non-plating region. A first metal layer can be added upon the metallic base layer. A second metal layer can be added upon the first metal layer of the plating region. The second metal layer can be electrically conductive and restricted from forming on the first metal layer of the non-plating region.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: August 16, 2016
    Assignee: Taiwan Green Point Enterprises Co., Ltd.
    Inventors: Sheng-Hung Yi, Pen-Yi Liao
  • Patent number: 9394616
    Abstract: The present invention can provide an etching composition for a chemical copper plating for the production of a printed-wiring board according to a semi-additive process, which comprises 0.2 to 5% by mass of hydrogen peroxide, 0.5 to 10% by mass of sulfuric acid, 0.001 to 0.3% by mass of phenylurea, 0.1 to 3 mass ppm of halogen ion and 0.003 to 0.3% by mass of tetrazoles, and wherein the ratio of the dissolution rate of the chemical copper plating (Y) to the dissolution rate of an electrolytic copper plating (X) at a liquid temperature of 30° C. (Y/X) is 4 to 7.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: July 19, 2016
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Kenichi Takahashi, Norifumi Tashiro
  • Patent number: 9378757
    Abstract: The disclosed methods enable the production of plasmonic near-field transducers that are useful in heat-assisted magnetic recording. The plasmonic near-field transducers have an enlarged region and a peg region. The peg region includes a peg region in proximity to an air-bearing surface above a recording medium and also includes a flared region between and in contact with the enlarged region and the peg region. The flared region can act as a heat sink and can lower the thermal resistance of the peg portion of the near-field transducer, thus reducing its temperature.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: June 28, 2016
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Yongjun Zhao, Dongsung Hong, Lijuan Zou, Mark Ostrowski
  • Patent number: 9346078
    Abstract: A mask frame assembly for thin film deposition includes a mask frame having an opening, and a mask configured to be coupled to the mask frame and including a first surface for facing a deposition substrate, a second surface opposite the first surface, and a deformation prevention part having varying thicknesses.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: May 24, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yoon-Chan Oh, Choon-Ho Lee
  • Patent number: 9297068
    Abstract: Wear parts having run-out and methods of producing the same, systems and control structures used to produce wear parts having run-out, and associated methods and software are disclosed. Some methods utilize a plasma-enhanced chemical vapor deposition process to produce a coating with a desired coating profile on a wear part.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: March 29, 2016
    Assignee: The Boeing Company
    Inventors: Liam S. Cavanaugh Pingree, Michael Howard-Edward Ware
  • Patent number: 9281479
    Abstract: An apparatus for fabricating an organic light emitting display includes a chamber, a stage having a hollow portion, a displacement sensor on the stage and configured to measure a distance between the stage and a measurement target that is on or over an upper part of the stage, and a controller. The controller includes an input unit configured to receive distance information obtained by the displacement sensor, a memory unit configured to store reference distance information, a determination unit configured to compare the distance information received by the input unit with the reference distance information, and an output unit configured to output a variable control signal according to whether or not the determination unit determines that the distance information between the stage and the measurement target corresponds to the reference distance information. A method for fabricating an organic light emitting display using the apparatus is also provided.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: March 8, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jeong Won Han, Young Uk Lee
  • Patent number: 9243998
    Abstract: A device includes a resonator having an oscillating portion with dimensions chosen to lead to a desired resonant frequency. A light source is positioned to provide light along the length of the oscillating portion at a specific wave length. A detector detects a change in oscillation of the resonator responsive to the wave pressure produced by the light source heating a gas. The light source is modulated with a frequency the same as the resonant frequency of the resonator.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: January 26, 2016
    Assignee: Honeywell International Inc.
    Inventors: Viorel Avramescu, Mihai Gologanu, Daniel Youngner, Bob Jon Carlson
  • Patent number: 9235674
    Abstract: Systems, methods, and other embodiments associated with an integrated circuit that includes a plurality of parallel pillar structures is described. In one embodiment, a system includes a design logic configured to analyze a design of an integrated circuit to identify open tracks on each layer by determining a location of structures in each layer of the design. The open tracks are spaces on each layer of the design that are free from structures that obstruct routing the plurality of pillar metals. The system also includes routing logic configured to successively route the plurality of pillar metals in each of the layers of the design based, at least in part, on the parameters and the location of the structures. The routing logic routes pillars of the plurality of pillar metals that are in adjacent layers to be perpendicular and pillar metals that are within a same layer of the design to be parallel.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: January 12, 2016
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Mark O'Brien, James G. Ballard, Kiran Vedantam, Mini Nanua, Salvatore Caruso
  • Patent number: 9182858
    Abstract: The present invention relates to a method for burying a conductive mesh in a transparent electrode, and more particularly, to a method which prevents a conductive mesh from protruding from a transparent electrode by burying the conductive mesh in the transparent electrode.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: November 10, 2015
    Assignee: KOREA INSTITUTE OF MACHINERY & MATERIALS
    Inventors: Taik Min Lee, In Young Kim, Jeong Dai Jo, Dong-Soo Kim
  • Patent number: 9136216
    Abstract: A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer insulating film is formed above the semiconductor substrate, and a thin-film resistor is disposed on the second interlayer insulating film in the resistor area. Vias that contact the thin-film resistor from below are formed in the second interlayer insulating film. A wiring line is disposed on the second interlayer insulating film in the wiring area. A dummy wiring line that covers the thin-film resistor from above is disposed in a third wiring layer that is in the same layer as the wiring line, and an insulating film is interposed between the thin-film resistor and the dummy wiring line.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: September 15, 2015
    Assignee: ROHM CO., LTD.
    Inventors: Isamu Nishimura, Michihiko Mifuji, Kazumasa Nishio
  • Patent number: 9125320
    Abstract: A method of manufacturing a passive component module includes the steps of: bonding passive components to a carrier, wherein each of the passive components has interconnection pads; forming a dielectric molding material over the carrier, so that the passive components are embedded in the molding material; separating the molding material, which has the passive components embedded therein, from the carrier; exposing all interconnection pads of the passive components; and building electrical interconnections between the passive components to obtain the passive component module. The steps of bonding, forming, separating, exposing and building are performed in the recited order.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: September 1, 2015
    Inventor: Dyi-Chung Hu
  • Patent number: 9112152
    Abstract: A method for producing a piezo actuator includes: providing a green stack including alternately successive green films and inner electrode layers; forming trenches on the outside green stack in areas in which the inner electrode layers are intended to be electrically insulated from the corresponding outer electrodes, the trenches shortening the inner electrode layers from the outside of the green stack toward the inside; filling the trenches with an electrically insulating slurry; further processing the green stack, including filling the trenches with slurry, such that the green films produce piezo electric layers and the green stack produces a piezo stack; mounting two outer electrodes on the outside of the piezo stack, such that the two outer electrodes are alternately electrically connected to the inner electrode layers. The trenches may be filled with the slurry using one of the following methods; screen printing, immersion, spraying, or vacuum infiltration.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: August 18, 2015
    Assignee: CONTINENTAL AUTOMOTIVE GMBH
    Inventors: Katrin Benkert, Hermann Bödinger, Stefan Denneler, Harald Johannes Kastl, Andreas Lenk, Carsten Schuh
  • Patent number: 9095085
    Abstract: Disclosed is a method of manufacturing a stacked multilayer structure, including the steps of forming a first circuit layer with bumps on a substrate, punching an aluminum plate to form recesses corresponding to the bumps, forming openings in a plastic film including a glass fiber layer corresponding to the bumps, pressing the aluminum plate, the plastic film and the substrate, removing the aluminum plate, polishing to level the resulting surface, forming a second circuit layer connected to the first circuit layer, and finally removing the substrate to form the stacked multilayer structure. Because the glass fiber layer in the plastic film is not exposed after polishing, the thickness of the dielectric layer is uniform and the reliability of the circuit layer is improved so as to increase the yield.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: July 28, 2015
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao Lin, Yu-Te Lu, De-Hao Lu
  • Patent number: 9095084
    Abstract: A stacked multilayer structure, including a first circuit layer having bumps, a plastic film stacked on the first circuit layer to fill up the space among the bumps so as to form a co-plane, and a second circuit layer formed on the co-plane and connected to the first circuit layer. The plastic film includes a glass fiber layer which is embedded and not exposed.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: July 28, 2015
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao Lin, Yu-Te Lu, De-Hao Lu
  • Patent number: 9084355
    Abstract: A flexible printed circuit board assembly includes a circuit board main body and a connection terminal provided at one side of the circuit board main body. The connection terminal has a shape in which a width of a portion farther from the circuit board main body is greater than a width of a portion closer to the circuit board main body.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: July 14, 2015
    Assignee: Samung Display Co., Ltd.
    Inventors: Sang-Yun Lee, Oh-Seob Kwon
  • Patent number: 9060458
    Abstract: A method for manufacturing a multi-layer printed circuit board includes: forming first bumps on one surface of a first copper layer at a predetermined interval; providing, on the first copper layer, an insulating layer through which the first bumps are penetrating; stacking a second copper layer on a top of the insulating layer; forming circuits by patterning the first copper layer and the second copper layer; laminating insulating films on top and bottom surfaces of the insulating layer on which the circuits have been formed; forming second bumps on one surface of a third copper layer and of a fourth copper layer at a predetermined interval; and stacking the third copper layer and fourth copper layer, provided with the second bumps, on the top and bottom surfaces of the insulating films.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: June 16, 2015
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yoong Oh, Cheol Ho Choi
  • Publication number: 20150131240
    Abstract: The invention concerns a method for production of electronic assembly (1) with 1.1 Supply of an electrically-conducting film (3), especially a support film (3a), 1.2 Supply of at least one electrical component (5) with at least one electrical contact site (5c), 1.3 Application of an adhesive (20) between the electrical component and a surface (30) of the electrically-conducting film, 1.4 Arrangement of the at least one component (5) with the at least one electrical contact site (5c) on the surface (30) of the electrically-conducting film (3) and fastening of the at least one component by formation of an adhesive joint between the electrical component and the surface, 1.5 Supply of the support (9), especially from a flexible material, 1.
    Type: Application
    Filed: May 22, 2012
    Publication date: May 14, 2015
    Applicant: Würth Elektronik Gmbh &Co. KG
    Inventor: Jan Kostelnik
  • Publication number: 20150129293
    Abstract: A printed circuit board and a method of manufacturing the same. In one embodiment, a printed circuit board includes: a core made of a glass material; an insulator surrounding the core; and a via connecting internal circuit layers through the core and the insulator.
    Type: Application
    Filed: November 11, 2014
    Publication date: May 14, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Suk Hyeon CHO, Hyo Seung NAM, Yong Sam LEE, Seok Hwan AHN
  • Patent number: 9031684
    Abstract: A method and system for integrated circuit fabrication is disclosed. In an example, the method includes determining a first process parameter of a wafer and a second process parameter of the wafer, the first process parameter and the second process parameter corresponding to different wafer characteristics; determining a variation of a device parameter of the wafer based on the first process parameter and the second process parameter; constructing a model for the device parameter as a function of the first process parameter and the second process parameter based on the determined variation of the device parameter of the wafer; and performing a fabrication process based on the model.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Han Cheng, Chin-Hsiang Lin, Chi-Ming Yang, Chun-Lin Chang, Chih-Hong Hwang
  • Publication number: 20150108084
    Abstract: A method of manufacturing a multilayer flexible circuit comprises providing first and second flexible substrates, each comprising a conductor layer and an insulator layer. The conductor layer of the first substrate is a patterned conductor layer. The first and second substrates are laminated together using a double belt press through which the substrates move in a continuous process. The method may include patterning the conductor layer of the first substrate and/or the conductor layer of the second substrate using an etching method that includes exposing a dry film resist on the conductor layer to a pattern by carrying out a plurality of exposures of adjacent and/or overlapping areas.
    Type: Application
    Filed: January 24, 2013
    Publication date: April 23, 2015
    Inventor: Philip Johnston
  • Publication number: 20150108085
    Abstract: The present invention provides a method of manufacturing a touch screen, comprising the steps of: a) forming a conductive layer on a substrate; b) forming an etching resist pattern on the conductive layer; and c) forming a conductive pattern having a line width smaller than the line width of the etching resist pattern by over-etching the conductive layer by using the etching resist pattern and a touch screen manufactured by the method. According to the present invention, a touch screen comprising a conductive pattern having an ultrafine line width can be economically and efficiently provided.
    Type: Application
    Filed: October 20, 2014
    Publication date: April 23, 2015
    Inventors: Ji-Young HWANG, In-Seok HWANG, Sang-Ki CHUN, Dong-Wook LEE, Yong-Koo SON, Min-Choon PARK, Seung-Heon LEE, Beom-Mo KOO, Young-Jun HONG, Ki-Hwan KIM, Su-Jin KIM, Hyeon CHOI
  • Publication number: 20150101848
    Abstract: Disclosed herein are a surface-treated copper foil, a copper-clad laminate plate including the same, a printed circuit board using the same, and a method for manufacturing the same. In detail, the copper-clad laminate plate according to one implementation embodiment of the present invention includes: carrier; a peel layer formed on the carrier; a copper-clad layer formed on the peel layer; and a surface-treated layer formed on the copper-clad layer, in which the surface-treated layer includes a thiol-based compound. Therefore, the present invention provides a printed circuit board capable of improving an adhesive force between a base and a copper-clad layer without treating a roughed surface by forming the surface-treated layer on the copper-clad layer.
    Type: Application
    Filed: September 19, 2014
    Publication date: April 16, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ji Sung CHO, Toshiko Yokota, Makoto Dobashi, Seung Min Baek, Ichiro Ogura, Eun Jung Lim, Yoon Su Kim, Sung Han