Abstract: The present disclosure relates to a mask, a mask device and a mask design method. The mask includes: a pattern area, wherein the pattern area includes a plurality of openings, among which adjacent openings are spaced apart by a first rib, and at least one of the plurality of openings has a non-straight side, two first straight sides intersecting with the non-straight side, and a second straight side opposite to the non-straight side and intersecting with the first straight sides; and a second rib located at an edge of the pattern area, wherein the second rib is provided with a cutout for compensating for stretch deformation of the non-straight side, extending lines of the two first straight sides extending toward the second rib along a first direction intersect with the second rib to obtain a first area, and the cutout is located at least within the first area.

Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a first dielectric layer, pads, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A top surface of the first dielectric layer is higher than an upper surface of each pad. The first metal layer is disposed on a first surface of the first dielectric layer. The second dielectric layer has second openings exposing part of the first metal layer. The second metal layer extends into the second openings and is electrically connected to the first metal layer. The third dielectric layer has third openings exposing part of the second metal layer. The surface treatment layer is disposed on the upper surfaces.

Abstract: A silicon-based edge coupler for coupling a fiber with a waveguide includes a cantilever member being partially suspended with its anchored end coupled to a silicon photonics die in a first part of a silicon substrate and a free end terminated near an edge region separating a second part of the silicon substrate from the first part. The edge coupler further includes a mechanical stopper formed at the edge region with a gap distance ahead of the free end of the cantilever member. Additionally, a V-groove is formed in the second part of the silicon substrate characterized by a top opening and a bottom plane symmetrically connected by two sloped side walls along a fixed Si-crystallography angle. The V-groove is configured to support a fiber with an end facet being pushed against the mechanical stopper and a core center being aligned with the free end of the cantilever member.

Abstract: In order to achieve the above-described technical benefits, according to an aspect of the present disclosure, a display device is provided. The display device includes a display panel in which a plurality of pixels is disposed, a touch panel which is disposed on the display panel, and a filling layer is disposed between the display panel and the touch panel. The display panel includes: a stretchable lower substrate; a pattern layer which is disposed on the lower substrate and includes a plurality of plate patterns in which a plurality of pixels is disposed and a plurality of line patterns.

Abstract: Provided are a method of manufacturing a mask that has a high precision configured to minimize a shadow effect, and a method of manufacturing a display device. The method of manufacturing a mask includes: tensioning a mask sheet; bonding the mask sheet that is tensioned to a mask frame; and forming an opening in the mask sheet by irradiating laser light on the mask sheet such that an inner wall of the opening has a slope with respect to a surface of the mask sheet.

Abstract: A process for the manufacture of a laminate, in particular a continuously pressed laminate, CPL, which can be used, for example, as a surface laminate in the manufacture of worktops or floor panels. The process includes the provision of a finish foil and a support structure, as well as the pressing of the finish foil with the support structure in a CPL process. The provision of a support structure includes impregnating the support structure with phenolic resin. The finish foil is provided with a decorative pattern and a three-dimensional structure that is synchronized with the decorative pattern.

Abstract: A method for manufacturing a semifinished product or component is disclosed in which a metal support embodied as a split strip is covered with at least one prepreg containing a thermally cross-linkable thermosetting matrix with endless fibers, the thermosetting matrix of the prepreg is pre-cross-linked by means of heating, and the metal support covered with the pre-cross-linked prepreg is formed into a semifinished product or component by means of roll forming. In order to enable plastic deformation in fiber-reinforced regions of the metal support, it is proposed that during the pre-cross-linking of the thermosetting matrix of the prepreg, its matrix is transferred into a viscosity state that is higher than its minimum viscosity and prior to reaching its gel point, the prepreg is formed together with the metal support.

Abstract: An apparatus and method capable of efficiently manufacturing a LED module. The method of manufacturing an Light Emitting Diode (LED) module includes preparing a substrate and a carrier on which an LED chip is disposed, disposing a mask on the substrate, the mask including an opening and a wall defining or forming the opening, picking up the LED chip from the carrier with a stamp, moving the LED chip picked up by the stamp to face the opening, moving the LED chip so that at least a part of the LED chip is inserted into the opening, and positioning the LED chip on the substrate by moving the LED chip so that the at least a part of the LED chip contacts the wall.

Abstract: A system and method to automatically determine power plane shape in a printed circuit board (PCB) involve obtaining inputs. The inputs include a size and shape of the PCB, a set of sources, and a set of sinks associated with a power plane. The method also includes determining a center of charge (CoC) as a center of largest current density for the set of sources and the set of sinks, and creating a sub-shape corresponding with a path from each source of the set of sources and from each sink of the set of sinks to the CoC. The creating the sub-shape includes determining a width of a conductor in the path corresponding with each of the sub-shapes. The sub-shapes created for the set of sources and the set of sinks are combined as the power plane shape.

Abstract: A passive electrical component includes a substrate. A first metallization layer is formed on the substrate. A first dielectric layer is formed on the first metallization layer The first dielectric layer has a lower thermal conductivity than the substrate. A second metallization layer is formed on the first dielectric layer. An electrically conductive via provides an electrical connection between a first section of the first metallization layer and a second section of the second metallization layer. A thermally conductive via provides a thermally conductive path between the second section and the substrate. The thermally conductive via provides an open circuit termination to the second section of the second metallization layer.

Abstract: A composition crosslinkable by broad band UV radiation, which after cross-linking is capable of cold ablation by a UV Excimer Laser emitting between 222 nm and 308 nm, where the composition is comprised of a negative tone resist developable in aqueous base comprising and is also comprised of a conjugated aryl additive absorbing ultraviolet radiation strongly in a range between from about 220 nm to about 310 nm. The present invention also encompasses a process comprising steps a), b) and c) a) coating the composition of claim 1 on a substrate; b) cross-linking the entire coating by irradiation with broadband UV exposure; c) forming a pattern in the cross-linked coating by cold laser ablating with a UV excimer laser emitting between 222 nm and 308 nm.

Abstract: The present invention relates to the controlling of the deposition quality of an epitaxial layer, for example of gallium nitride, on a growth plate, for example of silicon, in particular at the level of the edges of the plate. The invention aims, in particular, to reduce the complexity and the production cost of known solutions. The production method according to the invention highlights the existence of a chamfer on each growth plate and provides a self-positioned deposition of a protective film on at least one part of the chamfer using a mechanical mask, preventing the deposition of the protective film on the useful zone Zu through epitaxy.

Abstract: Printed circuit board (PCB), electrical structures including PCBs, and methods for making the same. One PCB structures includes: a substrate having a plurality of surfaces, including a first aerial main face (AMF), a second AMF, and a first peripheral end face (PEF), wherein the first PEF separates the first AMF from the second AMF, and a first plurality of contacts embedded in the first PEF, where each of the first plurality of contacts forms a contiguous contact with the first PEF and at least one of i) the second AMF, ii) the first AMF, and iii) another one of the plurality of surfaces.

Abstract: According to one aspect, the invention provides a method of providing conductive structures between two foils in a multi-foil system. The system comprises at least two foils, from which at least one foil comprises a terminal. The method comprises the steps of (in any order) providing at least one solid state adhesive layer, patterning adhesive layer with through-holes; filling the through-holes with conductive material, so as to form the conductive structure, connected to the terminal; and bonding the at least two foils. One advantage of the invention is that it may be used in a manufacturing process for multi-foil systems.

Abstract: A multi-layer circuit board including a plurality of insulation bumps, a first conductive layer, and a second conductive layer is provided. The plurality of insulation bumps are disposed between a first substrate and a second substrate. A top portion of the plurality of insulation bumps is served as a circuit connection point. The first conductive layer is disposed on the first substrate and connected to the circuit connection point. The second conductive layer is disposed on the second substrate and connected to the circuit connection point.

Abstract: The wafer stack (100) comprises a first wafer (OW1) referred to as optics wafer and a second wafer (SW) referred to as spacer wafer, said optics wafer (OW1) having manufacturing irregularities. The spacer wafer (SW) is structured such that it at least partially compensates for said manufacturing irregularities. The corresponding method for manufacturing a device, which in particular can be an optical device, comprises carrying out a correction step for at least partially compensating for manufacturing irregularities. Such a correction step comprises providing a wafer (SW) referred to as spacer wafer, wherein that spacer wafer is structured for at least partially compensating for said manufacturing irregularities. Those manufacturing irregularities may comprise a deviation from a nominal value, e.g., a irregularities in focal length. The invention can allow to mass produce high-precision devices at a high yield.

Abstract: A laminating apparatus includes a first jig having at least one recessed portion, a second jig disposed opposite to the first jig, a step difference portion disposed on the second jig, an elastic sheet disposed on each of the second jig and the step difference portion, and a guide portion spaced apart from the step difference portion and overlapping an edge of the elastic sheet. A width of the step difference portion is greater than a width of the recessed portion of the first jig.

Abstract: A vibration device that includes a support member, vibration arms connected to the support member and each having an n-type Si layer which is a degenerate semiconductor, and electrodes provided so as to excite the vibration arms, and silicon oxide films containing impurities in contact with a respective lower surface of the n-type Si layers of each vibration arm.

Abstract: A radiation shielding system for an x-ray digital detector array includes a first radiation shield having a plurality of shielding pads and a plurality of interstices between the plurality of shielding pads, the plurality of shielding pads having a greater thickness than the thickness of the plurality of interstices. The plurality of shielding pads is configured to be positioned over active components of the x-ray digital detector array and the interstices are configured to be positioned over passive components of the x-ray digital detector array.

Abstract: A method for producing an electric component (19) is specified, wherein in a step A) a body (1) having at least one cavity (7, 8) is provided. In a step B), the cavity (7, 8) is at least partly filled with a liquid insulation material (13) by means of capillary forces. Furthermore, an electric component (19) is specified wherein a cavity (7, 8) is at least partly filled with an insulation material (13). The insulation material (13) is introduced into the cavity (7, 8) by means of capillary forces. Furthermore, an electric component (19) is specified wherein a cavity (7, 8) is at least partly filled with an organic insulation material (13) and wherein the cavity is at least partly covered by a fired external contacting (17, 18).

Abstract: A wiring substrate includes an insulating layer, a connection pad buried in the insulating layer in a state that an upper surface of the connection pad is exposed from an upper surface of the insulating layer and a lower surface and at least a part of a side surface of the connection pad contact the insulating layer, and a concave level difference portion formed in the insulating layer around an outer periphery part of the connection pad, wherein an upper surface of the connection pad and an upper surface of the insulating layer are arranged at a same height.

Abstract: The present invention relates to an electromagnetic wave absorbing/radiating material which includes: a conductor; and a plurality of conductor discs disposed in an array above the surface of the conductor or a perforated conductor layer with a plurality of holes defined in an array above the surface of the conductor.

Abstract: A mask frame assembly for manufacturing a display device, and a method of manufacturing the mask frame assembly are disclosed. In one aspect, the mask frame assembly includes a frame having at least one opening portion defined therein. The mask frame assembly further includes a polymer film having a plurality of slits defined therein and combined to the frame. In another aspect, the method includes coating a polymer solution on a glass and drying and hardening the polymer solution so as to form a polymer film. The method also includes combining a frame to the polymer film, desorbing the glass from the polymer film and processing a plurality of slits on the polymer film.

Abstract: The present disclosure relates to a layered structure of a multi-layer PCB, and more particularly, to a structure of a high-power multi-layer PCB which can use a high current by efficiently dissipating heat generated from the inside of the multi-layered PCB and heat generated from a power semiconductor module package mounted on the PCB, and a production method thereof. The multi-layer PCB includes: a conductive plate having a plurality of heat poles protruding from at least one of a top surface and a bottom surface thereof; PCBs which are disposed on the top surface and the bottom surface of the conductive plate, and have a plurality of penetrating holes formed therethrough to allow the heat poles of the conductive plate to be inserted thereinto; and an insulation layer which is attached between the conductive plate and the PCBs in order to electrically insulate.

Abstract: A nanoprinthead including an array of nanotip cantilevers, where each nanotip cantilever includes a nanotip at an end of a cantilever, and a method for forming the nanoprinthead. Each nanotip may be individually addressable through use of an array of piezoelectric actuators. Embodiments for forming a nanoprinthead including an array of nanotip cantilevers can include an etching process from a material such as a silicon wafer, or the formation of a metal or dielectric nanotip cantilever over a substrate. The nanoprinthead may operate to provide uses for technologies such as dip-pen nanolithography, nanomachining, and nanoscratching, among others.

Abstract: Disclosed herein is a touch-sensitive display device comprising: a first set of metal electrodes including a first metal electrode; a second set of metal electrodes including a second metal electrode and a third metal electrode, the first metal electrode located between the second metal electrode and the third metal electrode such that the second metal electrode is physically separated from the third metal electrode; a first set of touch electrodes including a first touch electrode that is connected to the first metal electrode; a second set of touch electrodes including a second touch electrode and a third touch electrode, the second touch electrode connected to the second metal electrode and the third touch electrode connected to the third metal electrode; an insulation film having a plurality of contact holes; and a connection electrode electrically connecting the second metal electrode to the third metal electrode through the plurality of contact holes.

Abstract: A contact hole that penetrates a protective insulating film, an interlayer insulating film, and a transparent cap film and has a surface of a low-reflection film uncovered as a bottom surface is formed in a lead-out wiring region. A lower-layer terminal portion is formed by the low-reflection film and a low-resistance conductive film below the bottom surface of the contact hole. A contact hole that penetrates the protective insulating film and a transparent cap film and has a surface of a low-reflection film uncovered as a bottom surface is formed in the lead-out wiring region. An upper-layer terminal portion is formed by the low-reflection film and a low-resistance conductive film below the bottom surface of the contact hole.

Abstract: A photoresist stripping tool includes a reservoir configured to contain photoresist stripping solution and a Pb filter comprising a filter element with Tin (Sn) exterior surfaces. A semiconductor wafer fabrication system includes a semiconductor wafer attached to the photoresist stripping tool that strips photoresist from the semiconductor wafer. A photoresist stripping processes includes stripping photoresist from a leaded semiconductor wafer with photoresist stripping solution within the photoresist stripping tool, filtering Lead Pb from the photoresist stripping solution with the Pb filter, and stripping photoresist from a lead-free semiconductor wafer with the filtered photoresist stripping solution.

Abstract: A mask frame assembly includes a frame, and a mask tensioned on the frame in a first direction, the mask having a deposition pattern portion having a plurality of pattern holes therethrough, a deposition material being deposited on a substrate through the pattern holes, and a dummy portion extending from the deposition pattern portion in the first direction, the dummy portion having an increased thickness in a second direction as a distance from the deposition pattern portion in the first direction increases, the second direction being oriented along a normal to the mask.

Abstract: An epoxy resin composition containing an epoxy resin [A1], epoxy resin [B1], epoxy resin [C1] and curing agent [D] wherein [A1] is a bisphenol-type epoxy resin with a softening point of 90° C. or more, [B1] is a tri- or higher functional amine-type epoxy resin, [C1] is a bisphenol F-type epoxy resin with a number average molecular weight of 450 or less, and the epoxy resins [A1] to [C1] satisfy the following contents per 100 parts by mass of total epoxy resin content: [A1] 20 to 50 parts by mass, [B1] 30 to 50 parts by mass and [C1] 10 to 40 parts. The present invention provides low-viscosity epoxy resin compositions that are excellent in impregnating reinforcing fibers and capable of producing cured resins with excellent modulus and toughness, as well as prepregs and fiber-reinforced composite materials based on those epoxy resin compositions.

Abstract: A method is provided for making electrical contact with an electronic component in the form of a stack formed from a plurality of material layers, which react upon application of an electric field, and a plurality of electrode layers, wherein each material layer is arranged between two of the electrode layers. An insulation structure is generated on at least one stack circumferential region of the stack, which exposes each second electrode layer of the at least one stack circumferential region for electrical contact to be made. Also, a contact-making structure is applied to the at least one stack circumferential region which is provided with the insulation structure. Before the step of generating the contact-making structure, the material layers are partially removed by a material-removing method such that the electrode layers are exposed close to the surface.

Abstract: A semiconductor wafer has a plurality of first semiconductor die with a stress sensitive region. A masking layer or screen is disposed over the stress sensitive region. An underfill material is deposited over the wafer. The masking layer or screen prevents formation of the underfill material adjacent to the sensitive region. The masking layer or screen is removed leaving a cavity in the underfill material adjacent to the sensitive region. The semiconductor wafer is singulated into the first die. The first die can be mounted to a build-up interconnect structure or to a second semiconductor die with the cavity separating the sensitive region and build-up interconnect structure or second die. A bond wire is formed between the first and second die and an encapsulant is deposited over the first and second die and bond wire. A conductive via can be formed through the first or second die.

Abstract: A mask for deposition includes a plurality of deposition pattern parts arranged spaced apart from each other in a first direction, and a plurality of pattern openings defined in each deposition pattern part; a plurality of dummy pattern parts disposed at opposing sides of the plurality of deposition pattern parts in the first direction, respectively, and a plurality of recesses defined in each dummy pattern part; and a plurality of fixing parts respectively disposed at external sides of outermost dummy pattern parts among the plurality of dummy pattern parts, in the first direction. A maximum thickness of the each dummy pattern part is equal to or larger than a maximum thickness of the each deposition pattern part, and is smaller than a maximum thickness of each fixing part.

Abstract: A mask supported at a frame when a tensile force is applied in a first direction is provided. The mask includes a mask main body in a band shape extended in the first direction, and a plurality of pattern openings formed in the mask main body. the mask main body has ends supported by the frame, and the pattern opening are arranged in the first direction. The mask further includes a dummy opening provided between the pattern openings and one of the ends of the mask main body. The dummy opening has a form that is different from forms of the pattern openings.

Abstract: The invention provides a method of fabricating an interconnect comprising aligning and stacking a plurality of printed circuit boards with at least one adhesive component, laminating the printed circuit boards and the adhesive component, preparing bonded pair holes, depositing a copper seed layer, forming a copper plate image, electroplating a copper layer, removing a plate resist and depositing an insulator layer.

Abstract: A copper foil for a current collector of a lithium secondary battery has a crystalline structure, in which a ratio of the sum of texture coefficients of a (111) surface and a (200) surface to the total sum of texture coefficients of the (111), (200) and (220) surfaces is 60 to 85%, a ratio of the texture coefficient of the (111) surface to the total sum of texture coefficients of the (111), (200) and (220) is 18 to 38%, a ratio of the texture coefficient of the (200) surface thereto is 28 to 62%, and a ratio of the texture coefficient of the (220) surface thereto is 15 to 40%. The copper foil has surface roughness (Rz-JIS) of 2 ?m or less, weight deviation of 3% or less, tensile strength of 30 to 40 kgf/mm2, elongation of 3 to 20%, and thickness of 1 to 35 ?m.

Abstract: An optical connector is provided. The optical connector includes: an optical fiber line fixing block including an insertion groove in which an end portion of an optical fiber line is inserted; and a submount including first guide-walls determining a position of the optical fiber line fixing block and second guide-walls determining a position of an optical device to be connected to the optical fiber line, wherein the optical fiber line fixing block and the optical device are automatically aligned by the first guide-walls and the second guide-walls.

Abstract: A non-deleterious method for producing a continuous conductive circuit upon a non-conductive substrate can begin with the application of a metallic base layer upon a surface of a non-conductive substrate. A circuit pattern can be created within the metallic base layer based upon a circuit design. The metallic base layer comprising the circuit pattern can be physically separated from the remainder of the metallic base layer on the non-conductive substrate. The region of the non-conductive substrate surface that encloses the circuit pattern can be called the plating region. The remainder of the non-conductive substrate surface can be called the non-plating region. A first metal layer can be added upon the metallic base layer. A second metal layer can be added upon the first metal layer of the plating region. The second metal layer can be electrically conductive and restricted from forming on the first metal layer of the non-plating region.

Abstract: The present invention can provide an etching composition for a chemical copper plating for the production of a printed-wiring board according to a semi-additive process, which comprises 0.2 to 5% by mass of hydrogen peroxide, 0.5 to 10% by mass of sulfuric acid, 0.001 to 0.3% by mass of phenylurea, 0.1 to 3 mass ppm of halogen ion and 0.003 to 0.3% by mass of tetrazoles, and wherein the ratio of the dissolution rate of the chemical copper plating (Y) to the dissolution rate of an electrolytic copper plating (X) at a liquid temperature of 30° C. (Y/X) is 4 to 7.

Abstract: The disclosed methods enable the production of plasmonic near-field transducers that are useful in heat-assisted magnetic recording. The plasmonic near-field transducers have an enlarged region and a peg region. The peg region includes a peg region in proximity to an air-bearing surface above a recording medium and also includes a flared region between and in contact with the enlarged region and the peg region. The flared region can act as a heat sink and can lower the thermal resistance of the peg portion of the near-field transducer, thus reducing its temperature.

Abstract: A mask frame assembly for thin film deposition includes a mask frame having an opening, and a mask configured to be coupled to the mask frame and including a first surface for facing a deposition substrate, a second surface opposite the first surface, and a deformation prevention part having varying thicknesses.

Abstract: Wear parts having run-out and methods of producing the same, systems and control structures used to produce wear parts having run-out, and associated methods and software are disclosed. Some methods utilize a plasma-enhanced chemical vapor deposition process to produce a coating with a desired coating profile on a wear part.

Abstract: An apparatus for fabricating an organic light emitting display includes a chamber, a stage having a hollow portion, a displacement sensor on the stage and configured to measure a distance between the stage and a measurement target that is on or over an upper part of the stage, and a controller. The controller includes an input unit configured to receive distance information obtained by the displacement sensor, a memory unit configured to store reference distance information, a determination unit configured to compare the distance information received by the input unit with the reference distance information, and an output unit configured to output a variable control signal according to whether or not the determination unit determines that the distance information between the stage and the measurement target corresponds to the reference distance information. A method for fabricating an organic light emitting display using the apparatus is also provided.

Abstract: A device includes a resonator having an oscillating portion with dimensions chosen to lead to a desired resonant frequency. A light source is positioned to provide light along the length of the oscillating portion at a specific wave length. A detector detects a change in oscillation of the resonator responsive to the wave pressure produced by the light source heating a gas. The light source is modulated with a frequency the same as the resonant frequency of the resonator.

Abstract: Systems, methods, and other embodiments associated with an integrated circuit that includes a plurality of parallel pillar structures is described. In one embodiment, a system includes a design logic configured to analyze a design of an integrated circuit to identify open tracks on each layer by determining a location of structures in each layer of the design. The open tracks are spaces on each layer of the design that are free from structures that obstruct routing the plurality of pillar metals. The system also includes routing logic configured to successively route the plurality of pillar metals in each of the layers of the design based, at least in part, on the parameters and the location of the structures. The routing logic routes pillars of the plurality of pillar metals that are in adjacent layers to be perpendicular and pillar metals that are within a same layer of the design to be parallel.

Abstract: The present invention relates to a method for burying a conductive mesh in a transparent electrode, and more particularly, to a method which prevents a conductive mesh from protruding from a transparent electrode by burying the conductive mesh in the transparent electrode.

Abstract: A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer insulating film is formed above the semiconductor substrate, and a thin-film resistor is disposed on the second interlayer insulating film in the resistor area. Vias that contact the thin-film resistor from below are formed in the second interlayer insulating film. A wiring line is disposed on the second interlayer insulating film in the wiring area. A dummy wiring line that covers the thin-film resistor from above is disposed in a third wiring layer that is in the same layer as the wiring line, and an insulating film is interposed between the thin-film resistor and the dummy wiring line.

Abstract: A method of manufacturing a passive component module includes the steps of: bonding passive components to a carrier, wherein each of the passive components has interconnection pads; forming a dielectric molding material over the carrier, so that the passive components are embedded in the molding material; separating the molding material, which has the passive components embedded therein, from the carrier; exposing all interconnection pads of the passive components; and building electrical interconnections between the passive components to obtain the passive component module. The steps of bonding, forming, separating, exposing and building are performed in the recited order.

Abstract: A method for producing a piezo actuator includes: providing a green stack including alternately successive green films and inner electrode layers; forming trenches on the outside green stack in areas in which the inner electrode layers are intended to be electrically insulated from the corresponding outer electrodes, the trenches shortening the inner electrode layers from the outside of the green stack toward the inside; filling the trenches with an electrically insulating slurry; further processing the green stack, including filling the trenches with slurry, such that the green films produce piezo electric layers and the green stack produces a piezo stack; mounting two outer electrodes on the outside of the piezo stack, such that the two outer electrodes are alternately electrically connected to the inner electrode layers. The trenches may be filled with the slurry using one of the following methods; screen printing, immersion, spraying, or vacuum infiltration.

Abstract: Disclosed is a method of manufacturing a stacked multilayer structure, including the steps of forming a first circuit layer with bumps on a substrate, punching an aluminum plate to form recesses corresponding to the bumps, forming openings in a plastic film including a glass fiber layer corresponding to the bumps, pressing the aluminum plate, the plastic film and the substrate, removing the aluminum plate, polishing to level the resulting surface, forming a second circuit layer connected to the first circuit layer, and finally removing the substrate to form the stacked multilayer structure. Because the glass fiber layer in the plastic film is not exposed after polishing, the thickness of the dielectric layer is uniform and the reliability of the circuit layer is improved so as to increase the yield.