Adhesive Or Autogenous Bonding Of Self-sustaining Preforms (e.g., Prefabricated Base, Etc.) Patents (Class 216/20)
  • Publication number: 20120043121
    Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same. The printed circuit board includes: an insulating layer; a first circuit layer including a first metal layer and a first plating layer provided on an outer side of the first metal layer and embedded in one surface of the insulating layer; a second circuit layer including a second metal layer and a second plating layer provided on an outer side of the second metal layer and embedded in the other surface of the insulating layer; and a bump interconnecting the first circuit layer and the second circuit layer while penetrating through the insulating layer. The bump is used, such that there is no need to perform hole plating. Therefore, an increase in the surface plating thickness due to the hole plating is previously prevented.
    Type: Application
    Filed: August 17, 2011
    Publication date: February 23, 2012
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Jong Seok Bae
  • Publication number: 20120031874
    Abstract: A method for making a micro-device including at least one receiving site for components, formed in a thickness of a substrate. The method includes: a) making in at least one first substrate adhesively bonded to a second substrate via a discontinuous adhesive bonding interface, at least one first trench around at least one sacrificial block of the first substrate, by etching the first substrate so as to expose the adhesive bonding interface; and b) removing the sacrificial block so as to make at least one first cavity in the first substrate.
    Type: Application
    Filed: April 20, 2010
    Publication date: February 9, 2012
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
    Inventors: Damien Saint-Patrice, Sebastien Bolis, Fabrice Jacquet
  • Patent number: 8110118
    Abstract: An adhesive layer, an insulating layer and a copper foil are laminated together on both surfaces of a metallic base material by way of for example thermal press molding. In this case, openings (window holes) are formed in opposed positions on a portion of the adhesive layer. A circuit pattern is formed by etching on the copper foil in this state, followed by an external shape machining step of executing separation treatment reaching the metallic base material in predetermined positions including the openings. After that, a part of the insulating layer is cut off along the edge of the opening to obtain a circuit board with the end of the metallic base material exposed.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: February 7, 2012
    Assignee: Yazaki Corporation
    Inventors: Hiroyuki Fujita, Yasutaka Ochiai, Minoru Kubota
  • Publication number: 20120026112
    Abstract: Provided are a stereographic image display apparatus and a manufacturing method thereof. The stereographic image display apparatus includes an image display unit and a touch sensing unit which is positioned on the image display unit and is configured to interpose a lens array between a first transparent electrode layer and a second transparent electrode layer. The manufacturing method of the stereographic image display apparatus includes: allowing a transparent conductive material to be deposited on both surfaces of a lens array; forming first and second transparent electrode layers by etching the transparent conductive material deposited on the both surfaces of the lens array thereby generating a touch sensing unit; and adhering the touch sensing unit to an upper surface of an image display unit.
    Type: Application
    Filed: June 29, 2011
    Publication date: February 2, 2012
    Applicant: PANTECH CO., LTD.
    Inventors: Jin Woo SEOK, Myoung Hoon KWAK, Chong Kuk PAEK, Sang Yun WOO, Dong Gul CHA, Sung Ho CHUN, Hey Kyoung HAN
  • Publication number: 20120027994
    Abstract: Provided is a low-cost transparent conductive film which has high optical transparency and excellent surface conductivity and surface smoothness. A method for manufacturing such transparent conductive film is also provided. The transparent conductive film has, on a transparent base material, a conductive fiber layer which includes at least a transparent resin and a conductive fiber. At least a part of the conductive fiber is exposed from the surface of the transparent conductive film, and the relationship between the surface roughness (Rz) of the transparent conductive film and the average diameter (D) of the conductive fiber satisfies the inequalities of 0<Rz<D.
    Type: Application
    Filed: March 1, 2010
    Publication date: February 2, 2012
    Applicant: KONICA MINOLTA HOLDINGS, INC.
    Inventors: Hiroshi Takada, Hirokazu Koyama
  • Publication number: 20120009665
    Abstract: Microfluidic devices are prepared by providing a substrate material having a solid adhesive thin sheet, printing solid ink on the substrate using a conventional printer, selectively etching the substrate using a wax masking layer to obtain a desired pattern, removing the masking layer from the substrate, aligning and bonding together the pattern of the substrate to a pattern of a second substrate to form a layer of substrates, and curing the layer of substrates to result in a three-dimensional microfluidic device.
    Type: Application
    Filed: July 6, 2010
    Publication date: January 12, 2012
    Applicant: XEROX CORPORATION
    Inventor: Pinyen LIN
  • Publication number: 20110318609
    Abstract: It is an object of the present invention to provide a substrate for suspension reduced in the generation of cracks in an insulating layer at the boundary region between a region where a metal supporting substrate exists and a region where no metal supporting substrate exist.
    Type: Application
    Filed: June 29, 2011
    Publication date: December 29, 2011
    Inventors: Yoichi MIURA, Tsuyoshi YAMAZAKI
  • Publication number: 20110297644
    Abstract: A method for manufacturing printed circuit board includes steps below. An inner substrate including a first electrically conductive layer is provided. A first electrically conductive pattern is formed in the first electrically conductive layer. The first electrically conductive pattern includes an exposed region and an attaching region. A protective layer is formed on the entire exposed region. A first adhesive layer and a second electrically conductive layer are laminated on a surface of the first electrically conductive pattern in the attaching region and a surface of the protective layer. A slit along a boundary of the exposed region passing through the second electrically conductive pattern and the first adhesive layer is defined. The second electrically conductive layer corresponding to the exposed region, the first adhesive layer corresponding to the exposed region and the protective layer is removed.
    Type: Application
    Filed: April 21, 2011
    Publication date: December 8, 2011
    Applicants: FOXCONN ADVANCED TECHNOLOGY INC., FUKUI PRECISION COMPONENT (SHENZHEN) CO., LTD.
    Inventors: XUE-JUN CAI, ZHI-YONG LI
  • Patent number: 8066891
    Abstract: The present invention provides a laminate comprising an insulating layer having suppressed dusting properties, an insulating film comprising the insulating layer, and an electronic circuit component comprising a pattern of the insulating layer. The laminate has a layer construction of first inorganic material layer-insulating layer-second inorganic material layer or a layer construction of inorganic material layer-insulating layer. The insulating layer comprises a laminate of two or more wet etchable insulating unit layers. At the interface between the inorganic material layer and the insulating layer, surface irregularities of the inorganic material layer have been transferred onto the surface of the insulating layer. The average height of the surface irregularities transferred onto the insulating layer is less than the thickness of the outermost insulating unit layer in the insulating layer.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: November 29, 2011
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Katsuya Sakayori, Terutoshi Momose, Tomoko Togashi, Shigeki Kawano, Michiaki Uchiyama, Kazuto Okamura, Kazutoshi Taguchi, Kazunori Ohmizo, Makoto Shimose
  • Publication number: 20110284496
    Abstract: Provided is a method of forming an electronic circuit, wherein a nickel or nickel alloy layer is formed on an etching side of a rolled copper foil or an electrolytic copper foil, the rolled copper foil or the electrolytic copper foil is bonded to a resin substrate to obtain a copper-clad laminate, a resist pattern for forming a circuit is subsequently applied on the copper foil, any unwanted portion of the copper foil and the nickel or nickel alloy layer of the copper-clad laminate other than the portion to which the resist pattern was applied is removed using an etching solution of an aqueous ferric chloride, the resist is further removed, and soft etching is additionally performed in order to remove the remnant nickel or nickel alloy layer and thereby form a circuit in which the space between copper circuit lines is of a width that is double or more from the thickness of copper.
    Type: Application
    Filed: December 22, 2009
    Publication date: November 24, 2011
    Applicant: JX NIPPON MINING & METALS CORPORATION
    Inventors: Keisuke Yamanishi, Kengo Kaminaga, Ryo Fukuchi
  • Patent number: 8062537
    Abstract: Method for manufacturing an electronic module, which electronic module includes a component (6), which has contact areas (17), which are connected electrically to a conductor-pattern layer (14). The manufacture according to the method starts from a layered membrane, which comprises at least a conductor layer (4) and an insulator layer (10) on the first surface of the conductor layer (4). Contact openings (17), the mutual positions of which correspond to the mutual positions of the contact areas (7) of the component (6), and which penetrate both the conductor layer (4) and the insulator layer (10), are made in the membrane. After the manufacture of the contact openings (17), the component (6) is attached to the surface of the insulator layer (10), in such a way that the contact areas (7) of the component (6) line up next to the contact openings (17).
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: November 22, 2011
    Assignee: Imbera Electronics Oy
    Inventors: Risto Tuominen, Antti Iihola
  • Publication number: 20110278258
    Abstract: A system and method of indirectly modifying an environmental condition at a test site in one embodiment includes providing a test site on a substrate, providing a first activatable stimulant at the test site, providing an actuator configured to activate the first activatable stimulant at the test site, controlling the actuator to activate the first activatable stimulant, and modifying the local chemical environment at the test site with the first activated stimulant.
    Type: Application
    Filed: May 13, 2010
    Publication date: November 17, 2011
    Applicant: ROBERT BOSCH GMBH
    Inventors: Sam Kavusi, Yi Wei Chen, Michael Chen, Christoph Lang
  • Patent number: 8053367
    Abstract: A wafer polishing method is provided. First, a wafer, having a first surface, a second surface, and a plurality of opening portions depressed on the first surface, is provided. A plastic adhesive is filled in the opening portions and cured later. A polishing step is performed to thin the thickness of the wafer. Therefore, the yield of the wafer in the polishing process can be improved by the protection of the plastic adhesive.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: November 8, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Wei-Min Hsiao
  • Patent number: 8052881
    Abstract: A method for manufacturing a multilayer printed circuit board includes the following steps. A number of laminate units are provided. Each of the laminate units includes an electrically conductive layer with a circuit pattern defined therein, and a release layer releasably attached to the electrically conductive layer. A number of insulation layers are provided. Each of the insulation layers definies a metalized through hole therein. The electrically conductive layers and the insulation layers are stacked alternately one on another such that adjacent electrically conductive layers are insulated by one insulation layer and the metalized through holes electrically connects the circuit patterns of the adjacent electrically conductive layers. In the stacking step, the release layer is removed from the laminate unit after the electrically conductive layer is stacked onto the respective insulation layer, thereby obtaining a pre-laminated multilayer printed circuit board.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: November 8, 2011
    Assignees: FuKui Precision Component (Shenzhen) Co., Ltd., Zhen Ding Technology Co., Ltd.
    Inventors: Yun-Li Zhu, Yung-Wei Lai, Shing-Tza Liou
  • Publication number: 20110254171
    Abstract: Stretchable multi-chip modules (SMCMs) are capable of withstanding large mechanical deformations and conforming to curved surfaces. These SMCMs may find their utilities in elastic consumer electronics such as elastic displays, skin-like electronic sensors, etc. In particular, stretchable neural implants provide improved performances as to cause less mechanical stress and thus fewer traumas to surrounding soft tissues. Such SMCMs usually comprise of various electronic components attached to or embedded in a polydimethylsiloxane (PDMS) substrate and wired through stretchable interconnects. However, reliably and compactly connecting the electronic components to PDMS-based stretchable interconnects is very challenging. This invention describes an integrated method for high-density interconnection of electronic components through stretchable interconnects in an SMCM. This invention has applications in high-density SMCMs, as well as high-density stretchable/conformable neural interfaces.
    Type: Application
    Filed: April 8, 2011
    Publication date: October 20, 2011
    Inventors: Liang Guo, Stephen P. DeWeerth
  • Publication number: 20110233055
    Abstract: A cathode for receiving electro deposition of metal, the cathode comprising a planar conductive sheet and raised portions disposed on at least one surface of the planar conductive sheet, wherein the planar conductive sheet and the raised portions are integrally formed.
    Type: Application
    Filed: September 8, 2009
    Publication date: September 29, 2011
    Applicant: STEELMORE HOLDINGD PTY LTD
    Inventor: Jason Robert Cerezo
  • Publication number: 20110232950
    Abstract: The present invention relates to a method for manufacturing a substrate, including: providing a metal base; forming an oxide layer on one surface of the metal base; forming a chemical barrier layer on the oxide layer; forming an intermediate layer on the chemical barrier layer; forming a first metal layer on the intermediate layer; and removing parts of the intermediate layer and the first metal layer by etching to form a first metal wiring layer. Moreover, the present invention may include the following steps alternatively: laminating an insulating adhesive layer and a second metal layer on an exposed area of the chemical barrier layer; forming a second metal wiring layer by etching a part of the second metal layer; forming a surface metal layer; and forming a chip layer on the surface metal layer. The present invention also provides a structure of a substrate obtained according to the aforementioned method.
    Type: Application
    Filed: July 14, 2010
    Publication date: September 29, 2011
    Inventors: Shao-Chung HU, Ming-Chi Kan, Chien-Min Sung
  • Publication number: 20110226731
    Abstract: Provided are a crystal substrate etching method capable of processing with high accuracy, a piezoelectric vibrating reed of which the outer shape is formed by the method, a piezoelectric vibrator having the piezoelectric vibrating reed, and an oscillator, an electronic device, and a radio-controlled timepiece having the piezo-electric vibrator. A crystal substrate and an auxiliary substrate are successively dry-etched from a second surface side of the crystal substrate in a state where the auxiliary substrate having approximately the same etching rate as the crystal substrate is bonded to a first surface of the crystal substrate.
    Type: Application
    Filed: March 17, 2011
    Publication date: September 22, 2011
    Inventors: Yoichi Funabiki, Kiyoshi Aratake
  • Publication number: 20110222228
    Abstract: One embodiment of the invention relates to an electronic card containing a clear display window. The electronic card includes a printed circuit board, having a top surface and a bottom surface and a plurality of circuit components including a display disposed on the top surface of the printed circuit board. The electronic card further includes a bottom overlay disposed on the bottom surface of the printed circuit board, a top overlay disposed above the top surface of the printed circuit board, and a core layer positioned between the top surface of the bottom overlay and the bottom surface of the top overlay. The top overlay comprises a display window aligned with the display.
    Type: Application
    Filed: March 14, 2011
    Publication date: September 15, 2011
    Inventor: Robert SINGLETON
  • Publication number: 20110220397
    Abstract: A method of manufacturing an electronic component includes forming a resin layer over an underlying layer, pressing a conductor plate including a pattern formed on one major surface thereof against the resin layer, and embedding the pattern in the resin layer, and performing polishing, Chemical Mechanical Polishing, or cutting by the use of a diamond bit on another major surface of the conductor plate until the resin layer appears, and leaving the pattern in the resin layer as a conductor pattern.
    Type: Application
    Filed: May 23, 2011
    Publication date: September 15, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Masataka Mizukoshi, Yoshikatsu Ishizuki
  • Patent number: 8007673
    Abstract: An adhesive layer, an insulating layer and a copper foil are laminated together on both surfaces of a metallic base material by way of for example thermal press molding. In this case, openings (window holes) are formed in opposed positions on a portion of the adhesive layer. A circuit pattern is formed by etching on the copper foil in this state, followed by an external shape machining step of executing separation treatment reaching the metallic base material in predetermined positions including the openings. After that, a part of the insulating layer is cut off along the edge of the opening to obtain a circuit board with the end of the metallic base material exposed.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: August 30, 2011
    Assignee: Yazaki Corporation
    Inventors: Hiroyuki Fujita, Yasutaka Ochiai, Minoru Kubota
  • Publication number: 20110204021
    Abstract: A method of making fine-pitch circuit lines includes steps of preparing an insulative substrate, disposing a conductive metal layer on the insulative substrate, disposing on a whole or a part of a top surface of the conductive metal layer a hetero layer having an etching rate smaller than that of the conductive metal layer, forming a patterned mask of circuit lines on the hetero layer, wet etching the hetero layer and the conductive metal layer, and removing the patterned mask and the hetero layer so as to form fin-pitch circuit lines having a high etching factor on the insulative substrate.
    Type: Application
    Filed: April 13, 2010
    Publication date: August 25, 2011
    Applicant: SUBTRON TECHNOLOGY CO., LTD
    Inventors: Chien-Nan WU, Guan-Wei Huang
  • Publication number: 20110163064
    Abstract: Disclosed is a carrier for manufacturing a printed circuit board, which includes a first carrier including a first binder having a first opening and a first metal layer formed in the first opening of the first binder, and a second carrier, stacked with the first carrier and including a second binder having a second opening and a second metal layer which is formed in the second opening of the second binder and which partially overlaps with the first metal layer, so that the carrier is simply configured and the binders are formed not only on the lateral surfaces of the metal layers but also on the upper surfaces thereof, thus improving the reliability of bonding of the carrier at the periphery. A method of manufacturing the carrier and a method of manufacturing a printed circuit board using the carrier are also provided.
    Type: Application
    Filed: March 2, 2010
    Publication date: July 7, 2011
    Inventors: Jae Joon LEE, Jin Yong Ahn, Suk Hyeon Cho, Ki Hwan Kim, Seok Kyu Lee
  • Publication number: 20110156830
    Abstract: Provided is a microelectromechanical system (MEMS) that includes a first structure and second structure. The first structure and second structure may each include a first substrate and a second substrate. The first substrate of each structure may have first and second surfaces that face each other. The first substrate may include a via etching hole pattern penetrating the first surface and the second surface and a first non-via etching hole pattern penetrating the first surface. The second substrate of each structure may have third and fourth surfaces that face each other. The second substrate may include a second non-via etching hole pattern penetrating the third surface in a position corresponding to the via etching hole pattern of the first substrate. In the microelectromechanical system (MEMS) the second surface of the first substrate and the third surface of the second substrate may be bonded together.
    Type: Application
    Filed: July 6, 2010
    Publication date: June 30, 2011
    Inventors: Chan-wook Baik, Seog-woo Hong, Hwan-soo Suh
  • Patent number: 7951302
    Abstract: A method for forming a bump of a probe card is disclosed. In accordance with the method, a bump having a high aspect ratio for supporting a probe tip and a probe beam is formed using a semiconductor substrate as a mold eliminating a need for a photoresist film.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: May 31, 2011
    Assignee: Will Technology Co., Ltd
    Inventors: Bong Hwan Kim, Jong Bok Kim
  • Patent number: 7943052
    Abstract: A method for self-assembling a plurality of microstructures onto a substrate comprising using a bonding material to make the microstructure assembled onto the substrate by a physical attraction force. The microstructures are self-aligned with the substrate, and further permanently fixed on and electrical connection with the substrate by the solder bumps between the microstructures and the substrate, which is formed by the solder bumps via reflow process. There is no need for the using of the conventional pick-and-place device in the present method. The present method could be applied to light emitting diodes, RFID tags, micro-integrated circuits or other types of microstructures.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: May 17, 2011
    Assignee: National Taiwan University
    Inventors: Enboa Wu, Chia-Shou Chang
  • Publication number: 20110100952
    Abstract: A method of manufacturing a printed circuit board having a bump is disclosed. The method includes preparing a first carrier having a first circuit formed thereon, compressing the first carrier to one surface of an insulation layer such that the first circuit is buried, stacking an etching resist on the first carrier in accordance with where the bump is to be formed and forming the bump by etching the first carrier. In accordance with an embodiment of the present invention, the difference in height between a bump and its adjacent bump in a printed circuit board can be reduced, and thus electrical connection between an electronic component and the printed circuit board can be better implemented.
    Type: Application
    Filed: September 28, 2010
    Publication date: May 5, 2011
    Inventors: Ji-Eun KIM, Nam-Keun Oh, Jung-Hyun Park, Young-Ji Kim, Jong-Gyu Choi, Sang-Duck Kim
  • Patent number: 7922920
    Abstract: Systems, methods and apparatus are provided through which in some embodiments a mass spectrometer micro-leak includes a number of channels fabricated by semiconductor processing tools and that includes a number of inlet holes that provide access to the channels.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: April 12, 2011
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Dan N. Harpold, Hasso B. Niemann, Brian G. Jamieson, Bernard A. Lynch
  • Publication number: 20110076849
    Abstract: A method of fabricating a multilayer substrate may include bonding a front face of a donor substrate to a front face of a receiver substrate by molecular adhesion to form a stack and applying a heat treatment to the stack to consolidate a bond interface between the donor substrate and the receiver substrate. The method may further include thinning a back face of the donor substrate, trimming a periphery of the donor substrate and at least a portion of a periphery of the receiver substrate, and etching the back face of the donor substrate, the periphery of the donor substrate, and the at least a portion of the periphery of the receiver substrate subsequent to thinning the back face of the donor substrate and trimming the periphery of the donor substrate and the at least a portion of the periphery of the receiver substrate.
    Type: Application
    Filed: August 5, 2010
    Publication date: March 31, 2011
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventor: Chrystelle Lagahe Blanchard
  • Publication number: 20110064352
    Abstract: An optical waveguide electro-optic device including: a support substrate; an optical waveguide which has a core layer formed of a ferroelectric material, and is formed on an upper side of the support substrate; a lower electrode layer formed on a lower side of the core layer and which is adhered to the support substrate through an adhesion layer; an upper electrode layer formed on an upper side of the core layer; and an external electrode part, wherein the optical waveguide has an incidence plane from where light enters and an outgoing plane from where the light exits, the core layer has a polarization inversion region and a polarization non-inversion region, the upper electrode layer has a plane in such a shape that a width of the plane expands from a side of the incidence plane toward a side of the outgoing plane, to cover the polarization inversion region of the core layer, and the lower electrode layer is connected electrically to the external electrode part on the side of the incidence plane.
    Type: Application
    Filed: August 31, 2010
    Publication date: March 17, 2011
    Inventors: Jun NAKAGAWA, Shuichi Suzuki, Atsushi Sakai, Koichiro Nakamura
  • Publication number: 20110045695
    Abstract: A film-shaped electrically-connecting body 1 is used for electrically connecting a plurality of electronic devices and includes: two insulation sheets having a plurality of opening portions formed therein at a regular interval, and a plurality of plate-shaped connection elements; a part of each of the connection elements being held between the two insulation sheets, the other part where the connection element is not held being extended from the portion held to the opening portion and bent to form a contact point with a terminal of the electric device, and the two insulation sheets being unified at a portion where the connection element is not present therebetween. The two insulation sheets are formed by screen printing using a material having electrical insulation and elasticity and being dissolved in a solvent as an ink for printing.
    Type: Application
    Filed: June 23, 2010
    Publication date: February 24, 2011
    Applicant: NGK Insulators, Ltd.
    Inventor: Kazuiku MIWA
  • Publication number: 20110017704
    Abstract: A method of making a microelectronic connection component is disclosed. A plurality of portions of a conductive, etch-resistant material is provided on a surface of a metallic sheet. The sheet is etched from the surface to form posts extending generally parallel to one another aligned with the portions of the etch-resistant material. A microelectronic device is provided having one of a front face or a rear face overlying first ends of the posts. Second ends of the posts remote from the first ends face away from the microelectronic device as interconnection terminals for the connection component. At least some of the posts are electrically connected to the microelectronic device.
    Type: Application
    Filed: September 30, 2010
    Publication date: January 27, 2011
    Applicant: TESSERA, INC.
    Inventor: Joseph C. FJELSTAD
  • Patent number: 7875195
    Abstract: The presently disclosed invention provides for the fabrication of porous anodic alumina (PAA) films on a wide variety of substrates. The substrate comprises a wafer layer and may further include an adhesion layer deposited on the wafer layer. An anodic alumina template is formed on the substrate. When a rigid substrate such as Si is used, the resulting anodic alumina film is more tractable, easily grown on extensive areas in a uniform manner, and manipulated without danger of cracking. The substrate can be manipulated to obtain free-standing alumina templates of high optical quality and substantially flat surfaces. PAA films can also be grown this way on patterned and non-planar surfaces. Furthermore, under certain conditions, the resulting PAA is missing the barrier layer (partially or completely) and the bottom of the pores can be readily accessed electrically.
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: January 25, 2011
    Assignee: Massachusetts Institute of Technology
    Inventors: Oded Rabin, Paul R. Herz, Mildred S. Dresselhaus, Akintunde I. Akinwande, Yu-Ming Lin
  • Publication number: 20100301006
    Abstract: Electrical components, e.g., a radiator for a cell phone circuit, are manufactured by a method comprising the steps of: (A) providing a substrate, e.g., a polymeric film, having a first facial side that has a metal coating, e.g., copper, and a second facial side that does not have a metal coating; (B) applying a covering material that is impervious to etching and plating, e.g., solder-mask, to the metal coating to define a trace except for its contact spot; (C) applying etch-resist to the metal coating to define the contact spot; (D) etching the metal coating from the substrate that is not covered by the covering material or etch-resist; (E) removing the etch-resist from the metal coating; and (F) plating the uncovered metal coating with a plating material comprising at least one of silver, gold, and nickel.
    Type: Application
    Filed: May 29, 2009
    Publication date: December 2, 2010
    Inventor: Peter L.J. Nilsson
  • Publication number: 20100300201
    Abstract: A micromachined thermal and mechanical isolator for MEMS die that may include two layers, a first layer with an active temperature regulator comprising a built-in heater and temperature sensor and a second layer having mechanical isolation beams supporting the die. The isolator may be inserted between a MEMS die of a disc resonator gyroscope (DRG) chip and the leadless chip carrier (LCC) package to isolate the die from stress and temperature gradients. Thermal and mechanical stress to the DRG can be significantly reduced in addition to mitigating temperature sensitivity of the DRG chip. The small form can drastically reduce cost and power consumption of the MEMS inertial sensor and enable new applications such as smart munitions, compact and integrated space navigation solutions, with significant potential cost savings over the existing inertial systems.
    Type: Application
    Filed: May 27, 2009
    Publication date: December 2, 2010
    Applicant: The Boeing Company
    Inventors: Howard H. Ge, A. Dorian Challoner
  • Publication number: 20100288726
    Abstract: A method of manufacturing a printed circuit board including: forming a heat dissipating coating layer on the surface of a heat dissipating layer; forming circuit patterns on the surface of an insulating layer, and forming an inter-layer conductive part joining with the insulating layer by passing through the insulating layer and electrically connected with the circuit patterns; and laminating the insulating layer on the heat dissipating layer such that the inter-layer conductive part is connected with the heat dissipating coating layer.
    Type: Application
    Filed: July 27, 2010
    Publication date: November 18, 2010
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Eung-Suek Lee, Dek-Gin Yang, Keun-Ho Kim
  • Patent number: 7810355
    Abstract: Methods and apparatus for protecting the thin films during chemical and/or thermal edge strengthening treatment. In one embodiment, a portion of each individual sheet is laminated. Pairs of sheets are then sealed together such that the thin film sides face inward to form a thin film sandwich. In some embodiments, the sandwich in then immersed in a chemical strengthener. In other embodiments, a localized treatment is applied to the unstrengthened edges.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: October 12, 2010
    Assignee: Apple Inc.
    Inventors: Casey J. Feinstein, John Z. Zhong
  • Publication number: 20100243601
    Abstract: Provided is a method for manufacturing a multilayer wiring board, whereby even if the multilayer wiring board suffers warping or irregularities, thin-film patterns with great uniformity that are to be used as a mask for forming a wiring layer can be obtained in a simple way. A primer-coated metal foil 20 composed of a primer resin layer 21 and a metal layer 22 is placed on a surface of a double-face CCL 10, which is prepared by applying metal layers 12 and 13 onto the surfaces of a support base 11, and the primer-coated metal foil 20 and the double-face CCL 10 are bonded and the primer resin layer 21 is cured. A via Vb is thereafter formed from the metal layer 22 side, and a metal-plate layer 30 is formed on the resulting metal layer 22. After that, the etched down metal-plate layer 30 and the metal layer 22 are patterned, and using the patterned layers as a mask, the primer resin layer 21 is patterned.
    Type: Application
    Filed: March 24, 2010
    Publication date: September 30, 2010
    Applicant: TDK CORPORATION
    Inventors: Hiroyuki Uematsu, Kenichi Kawabata, Kenji Nagase
  • Publication number: 20100230156
    Abstract: A method for making a packaging device for an electronic element includes: preparing a ceramic frame body defined with a hollow space for receiving the electronic element therein; preparing a ceramic substrate having a copper layer formed thereon; etching the copper layer to form a predetermined copper pattern on an upper surface of the ceramic substrate; placing the ceramic frame body onto the upper surface of the ceramic substrate and in contact with the copper pattern ; and heating the ceramic frame body and the ceramic substrate such that the copper pattern bonds the ceramic frame body to the ceramic substrate. A packaging device for an electronic element is also disclosed.
    Type: Application
    Filed: March 9, 2010
    Publication date: September 16, 2010
    Applicant: High Conduction Scientific Co., Ltd.
    Inventors: Wen-Chung Chiang, Keng-Chung Wu, Ying-Chi Hsieh, Cheng-Kang Lu, Ming-Huang Fu
  • Publication number: 20100233226
    Abstract: The present invention relates to a nanowire array (15, 16) for electrically-controlled elution of a therapeutic composition (5) comprising a plurality of nanoscopic-sized wires (12, 12), nanowires, attached to an electrically conducting solid support (7), said nanowires formed from electroactive conjugated polymer (4) containing or doped with said therapeutic composition (5) coated over a plurality of nanoscopic sized electrically conducting protrusions (8). It also relates to a method for preparing a nanowire array and an electrode.
    Type: Application
    Filed: October 14, 2008
    Publication date: September 16, 2010
    Applicant: Université Catholique de Louvain
    Inventors: Etienne Ferain, Delphine Magnin, Sophie Demoustier-Champagne, Marie-Anne Thil, Jean Delbeke, Ides Colin
  • Patent number: 7767102
    Abstract: The present invention is directed to methods to harvest, integrate and exploit nanomaterials, and particularly elongated nanowire materials. The invention provides methods for harvesting nanowires that include selectively etching a sacrificial layer placed on a nanowire growth substrate to remove nanowires. The invention also provides methods for integrating nanowires into electronic devices that include placing an outer surface of a cylinder in contact with a fluid suspension of nanowires and rolling the nanowire coated cylinder to deposit nanowires onto a surface. Methods are also provided to deposit nanowires using an ink-jet printer or an aperture to align nanowires. Additional aspects of the invention provide methods for preventing gate shorts in nanowire based transistors. Additional methods for harvesting and integrating nanowires are provided.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: August 3, 2010
    Assignee: Nanosys, Inc.
    Inventors: Francesco Lemmi, David P. Stumbo
  • Publication number: 20100163290
    Abstract: A method for manufacturing printed wiring board including preparing an electronic component having first and second surfaces and electrode on the first surface, forming in an adhesive tape a mark, mounting based on the mark the component on the tape such that the second surface faces the adhesive of the tape, forming another mark on insulative substrate having first and second surfaces, forming in the substrate an opening larger than the component, mounting based on the marks the substrate on the tape such that the component is in the opening of the substrate, fixing the component to the substrate using resin, forming an insulation layer on the first surface of the substrate where the component is accommodated, removing the tape, forming in the layer an opening reaching the electrode, forming a conductive circuit on the layer, and forming in the opening of the layer a via connected to the electrode.
    Type: Application
    Filed: October 27, 2009
    Publication date: July 1, 2010
    Applicant: IBIDEN CO., LTD.
    Inventor: Hiroyasu Nagata
  • Publication number: 20100139955
    Abstract: A patterned substrate for a touch screen sensor assembly that includes a plurality of electrodes that are formed from a first transparent conductive layer that has a first surface resistivity. The substrate also has a plurality of traces that may be used to couple the electrodes controller associated with the touch screen sensor assembly. The traces are formed from a second conductive layer that has a second surface resistivity that is less than the surface resistivity of the first conductive layer. The first and second conductive layers may be formed from indium tin oxide (ITO) having different surface resistivities. A second, similarly configured substrate can be provided and may be spaced apart from the first substrate by a dielectric spacer.
    Type: Application
    Filed: December 2, 2009
    Publication date: June 10, 2010
    Inventors: Ding Hua Long, Hai Long Zhang, Ying Yu
  • Publication number: 20100126958
    Abstract: A method of fabricating a circuit includes bonding an electrically conductive layer to a donor film, removing selected portions of the electrically conductive layer from the donor film to provide a circuit arrangement, and transferring the circuit arrangement from the donor film to a substrate.
    Type: Application
    Filed: November 25, 2008
    Publication date: May 27, 2010
    Inventors: Paul Attridge, Foster P. Lamm
  • Publication number: 20100096358
    Abstract: A ladder filter includes a series resonator having a first film laminate in which an upper electrode and a lower electrode face each other across a piezoelectric film, and a first film provided on the first film laminate, and a parallel resonator having a second film laminate having a structure similar to that of the first film laminate, a second film provided on the second film laminate, and another first film identical to the first film.
    Type: Application
    Filed: December 28, 2009
    Publication date: April 22, 2010
    Applicants: Fujitsu Media Devices Limited, Fujitsu Limited
    Inventors: Shinji TANIGUCHI, Tokihiro Nishihara, Tsuyoshi Yokoyama, Masafumi Iwaki, Go Endo, Yasuyuki Saitou, Hisanori Ehara, Masanori Ueda
  • Publication number: 20100089626
    Abstract: It is an object of the invention to provide a composite with sufficiently reliable bonding and adequately minimized generation of fluff from flaking resin dust and fibers. This object is achieved by the composite (100) of the invention that comprises a fiber sheet (101) impregnated with a resin composition (102), wherein the 20° C. storage elastic modulus of the cured resin composition (102) is 100-2000 MPa. The composite (100) optionally contains perforations (103).
    Type: Application
    Filed: November 25, 2009
    Publication date: April 15, 2010
    Applicant: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Nozomu Takano, Masaki Kamiya
  • Publication number: 20100084267
    Abstract: A pair of measuring electrodes comprising a first and a second, preferably in each case sheet-like electrode comprises an insulation layer arranged between said electrodes. One or more nanopores, which extend through said insulation layer as far as said first electrode, the surface of which is at least partially uncovered by said nanopores, are provided in each second electrode. The invention also describes a biosensor comprising a pair of measuring electrodes of this type, an electrochemical cell comprising a biosensor of this type and a process for producing said pair of measuring electrodes.
    Type: Application
    Filed: September 25, 2009
    Publication date: April 8, 2010
    Applicant: NMI NATURWISSENSCHAFTLICHES UND MEDIZINISCHES INSTITUT AN DER UNIVERSITAT TEUBIN
    Inventors: Martin Stelzle, Wilfried Nisch
  • Publication number: 20100078200
    Abstract: A flex circuit comprises a base film, a first adhesive layer coupled with the base film, at least two signal traces coupled with the first adhesive layer, and at least one dummy trace positioned between the two signal traces and coupled with the first adhesive layer. The flex circuit comprises a second adhesive layer coupled with the signal traces, the dummy trace, and the first adhesive layer, and a cover film coupled with the second adhesive layer.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Inventor: Jr-Yi SHEN
  • Publication number: 20100078213
    Abstract: A method for manufacturing a printed wiring board, in which filled vias with a reduction in faulty connections are formed, and providing such a printed wiring board. After an electroless plated film is formed on an inner wall of a via opening, electrolytic plating is performed on insulative resin base material; the via opening is filled with plating metal and a filled via is formed. Therefore, during electrolytic plating, a plating metal is deposited from electroless plated film on the side wall of the via opening as well as from the bottom of the via opening. As a result, the via opening may be completely filled through electrolytic plating, forming a filled via with a reduction in faulty connections.
    Type: Application
    Filed: July 31, 2009
    Publication date: April 1, 2010
    Applicant: IBIDEN CO., LTD
    Inventors: Toshiki FURUTANI, Takeshi Furusawa
  • Patent number: 7678587
    Abstract: Disclosed is a cantilever-type probe and methods of fabricating the same. The probe is comprised of a cantilever being longer lengthwise relative to the directions of width and height, and a tip extending from the bottom of the cantilever and formed at an end of the cantilever. A section of the tip parallel to the bottom of the cantilever is rectangular, having four sides slant to the lengthwise direction of the cantilever.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: March 16, 2010
    Assignee: Phicom Corporation
    Inventors: Ki-Joon Kim, Yong-Hwi Jo